staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / net / ethernet / intel / ice / ice_txrx.h
blob31bc998fe2006f7fa515a4b05917abdae50cb7c0
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018, Intel Corporation. */
4 #ifndef _ICE_TXRX_H_
5 #define _ICE_TXRX_H_
7 #define ICE_DFLT_IRQ_WORK 256
8 #define ICE_RXBUF_2048 2048
9 #define ICE_MAX_CHAINED_RX_BUFS 5
10 #define ICE_MAX_BUF_TXD 8
11 #define ICE_MIN_TX_LEN 17
13 /* The size limit for a transmit buffer in a descriptor is (16K - 1).
14 * In order to align with the read requests we will align the value to
15 * the nearest 4K which represents our maximum read request size.
17 #define ICE_MAX_READ_REQ_SIZE 4096
18 #define ICE_MAX_DATA_PER_TXD (16 * 1024 - 1)
19 #define ICE_MAX_DATA_PER_TXD_ALIGNED \
20 (~(ICE_MAX_READ_REQ_SIZE - 1) & ICE_MAX_DATA_PER_TXD)
22 #define ICE_RX_BUF_WRITE 16 /* Must be power of 2 */
23 #define ICE_MAX_TXQ_PER_TXQG 128
25 /* Tx Descriptors needed, worst case */
26 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
27 #define ICE_DESC_UNUSED(R) \
28 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
29 (R)->next_to_clean - (R)->next_to_use - 1)
31 #define ICE_TX_FLAGS_TSO BIT(0)
32 #define ICE_TX_FLAGS_HW_VLAN BIT(1)
33 #define ICE_TX_FLAGS_SW_VLAN BIT(2)
34 #define ICE_TX_FLAGS_VLAN_M 0xffff0000
35 #define ICE_TX_FLAGS_VLAN_S 16
37 struct ice_tx_buf {
38 struct ice_tx_desc *next_to_watch;
39 struct sk_buff *skb;
40 unsigned int bytecount;
41 unsigned short gso_segs;
42 u32 tx_flags;
43 DEFINE_DMA_UNMAP_ADDR(dma);
44 DEFINE_DMA_UNMAP_LEN(len);
47 struct ice_tx_offload_params {
48 u8 header_len;
49 u32 td_cmd;
50 u32 td_offset;
51 u32 td_l2tag1;
52 u16 cd_l2tag2;
53 u32 cd_tunnel_params;
54 u64 cd_qw1;
55 struct ice_ring *tx_ring;
58 struct ice_rx_buf {
59 struct sk_buff *skb;
60 dma_addr_t dma;
61 struct page *page;
62 unsigned int page_offset;
65 struct ice_q_stats {
66 u64 pkts;
67 u64 bytes;
70 struct ice_txq_stats {
71 u64 restart_q;
72 u64 tx_busy;
73 u64 tx_linearize;
76 struct ice_rxq_stats {
77 u64 non_eop_descs;
78 u64 alloc_page_failed;
79 u64 alloc_buf_failed;
80 u64 page_reuse_count;
83 /* this enum matches hardware bits and is meant to be used by DYN_CTLN
84 * registers and QINT registers or more generally anywhere in the manual
85 * mentioning ITR_INDX, ITR_NONE cannot be used as an index 'n' into any
86 * register but instead is a special value meaning "don't update" ITR0/1/2.
88 enum ice_dyn_idx_t {
89 ICE_IDX_ITR0 = 0,
90 ICE_IDX_ITR1 = 1,
91 ICE_IDX_ITR2 = 2,
92 ICE_ITR_NONE = 3 /* ITR_NONE must not be used as an index */
95 /* Header split modes defined by DTYPE field of Rx RLAN context */
96 enum ice_rx_dtype {
97 ICE_RX_DTYPE_NO_SPLIT = 0,
98 ICE_RX_DTYPE_HEADER_SPLIT = 1,
99 ICE_RX_DTYPE_SPLIT_ALWAYS = 2,
102 /* indices into GLINT_ITR registers */
103 #define ICE_RX_ITR ICE_IDX_ITR0
104 #define ICE_TX_ITR ICE_IDX_ITR1
105 #define ICE_ITR_DYNAMIC 0x8000 /* use top bit as a flag */
106 #define ICE_ITR_8K 0x003E
108 /* apply ITR HW granularity translation to program the HW registers */
109 #define ITR_TO_REG(val, itr_gran) (((val) & ~ICE_ITR_DYNAMIC) >> (itr_gran))
111 /* Legacy or Advanced Mode Queue */
112 #define ICE_TX_ADVANCED 0
113 #define ICE_TX_LEGACY 1
115 /* descriptor ring, associated with a VSI */
116 struct ice_ring {
117 struct ice_ring *next; /* pointer to next ring in q_vector */
118 void *desc; /* Descriptor ring memory */
119 struct device *dev; /* Used for DMA mapping */
120 struct net_device *netdev; /* netdev ring maps to */
121 struct ice_vsi *vsi; /* Backreference to associated VSI */
122 struct ice_q_vector *q_vector; /* Backreference to associated vector */
123 u8 __iomem *tail;
124 union {
125 struct ice_tx_buf *tx_buf;
126 struct ice_rx_buf *rx_buf;
128 u16 q_index; /* Queue number of ring */
129 u32 txq_teid; /* Added Tx queue TEID */
131 /* high bit set means dynamic, use accessor routines to read/write.
132 * hardware supports 2us/1us resolution for the ITR registers.
133 * these values always store the USER setting, and must be converted
134 * before programming to a register.
136 u16 rx_itr_setting;
137 u16 tx_itr_setting;
139 u16 count; /* Number of descriptors */
140 u16 reg_idx; /* HW register index of the ring */
142 /* used in interrupt processing */
143 u16 next_to_use;
144 u16 next_to_clean;
146 u8 ring_active; /* is ring online or not */
148 /* stats structs */
149 struct ice_q_stats stats;
150 struct u64_stats_sync syncp;
151 union {
152 struct ice_txq_stats tx_stats;
153 struct ice_rxq_stats rx_stats;
156 unsigned int size; /* length of descriptor ring in bytes */
157 dma_addr_t dma; /* physical address of ring */
158 struct rcu_head rcu; /* to avoid race on free */
159 u16 next_to_alloc;
160 } ____cacheline_internodealigned_in_smp;
162 enum ice_latency_range {
163 ICE_LOWEST_LATENCY = 0,
164 ICE_LOW_LATENCY = 1,
165 ICE_BULK_LATENCY = 2,
166 ICE_ULTRA_LATENCY = 3,
169 struct ice_ring_container {
170 /* array of pointers to rings */
171 struct ice_ring *ring;
172 unsigned int total_bytes; /* total bytes processed this int */
173 unsigned int total_pkts; /* total packets processed this int */
174 enum ice_latency_range latency_range;
175 u16 itr;
178 /* iterator for handling rings in ring container */
179 #define ice_for_each_ring(pos, head) \
180 for (pos = (head).ring; pos; pos = pos->next)
182 bool ice_alloc_rx_bufs(struct ice_ring *rxr, u16 cleaned_count);
183 netdev_tx_t ice_start_xmit(struct sk_buff *skb, struct net_device *netdev);
184 void ice_clean_tx_ring(struct ice_ring *tx_ring);
185 void ice_clean_rx_ring(struct ice_ring *rx_ring);
186 int ice_setup_tx_ring(struct ice_ring *tx_ring);
187 int ice_setup_rx_ring(struct ice_ring *rx_ring);
188 void ice_free_tx_ring(struct ice_ring *tx_ring);
189 void ice_free_rx_ring(struct ice_ring *rx_ring);
190 int ice_napi_poll(struct napi_struct *napi, int budget);
192 #endif /* _ICE_TXRX_H_ */