drivers/pci/hotplug/pciehp.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * PCI Express Hot Plug Controller Driver
   4  *
   5  * Copyright (C) 1995,2001 Compaq Computer Corporation
   6  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   7  * Copyright (C) 2001 IBM Corp.
   8  * Copyright (C) 2003-2004 Intel Corporation
   9  *
  10  * All rights reserved.
  11  *
  12  * Send feedback to <greg@kroah.com>, <kristen.c.accardi@intel.com>
  13  *
  14  */
  15 #ifndef _PCIEHP_H
  16 #define _PCIEHP_H
  17
  18 #include <linux/types.h>
  19 #include <linux/pci.h>
  20 #include <linux/pci_hotplug.h>
  21 #include <linux/delay.h>
  22 #include <linux/sched/signal.h>         /* signal_pending() */
  23 #include <linux/mutex.h>
  24 #include <linux/rwsem.h>
  25 #include <linux/workqueue.h>
  26
  27 #include "../pcie/portdrv.h"
  28
  29 #define MY_NAME "pciehp"
  30
  31 extern bool pciehp_poll_mode;
  32 extern int pciehp_poll_time;
  33 extern bool pciehp_debug;
  34
  35 #define dbg(format, arg...)                                             \
  36 do {                                                                    \
  37         if (pciehp_debug)                                               \
  38                 printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg);      \
  39 } while (0)
  40 #define err(format, arg...)                                             \
  41         printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
  42 #define info(format, arg...)                                            \
  43         printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
  44 #define warn(format, arg...)                                            \
  45         printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
  46
  47 #define ctrl_dbg(ctrl, format, arg...)                                  \
  48         do {                                                            \
  49                 if (pciehp_debug)                                       \
  50                         dev_printk(KERN_DEBUG, &ctrl->pcie->device,     \
  51                                         format, ## arg);                \
  52         } while (0)
  53 #define ctrl_err(ctrl, format, arg...)                                  \
  54         dev_err(&ctrl->pcie->device, format, ## arg)
  55 #define ctrl_info(ctrl, format, arg...)                                 \
  56         dev_info(&ctrl->pcie->device, format, ## arg)
  57 #define ctrl_warn(ctrl, format, arg...)                                 \
  58         dev_warn(&ctrl->pcie->device, format, ## arg)
  59
  60 #define SLOT_NAME_SIZE 10
  61
  62 /**
  63  * struct slot - PCIe hotplug slot
  64  * @state: current state machine position
  65  * @ctrl: pointer to the slot's controller structure
  66  * @hotplug_slot: pointer to the structure registered with the PCI hotplug core
  67  * @work: work item to turn the slot on or off after 5 seconds in response to
  68  *      an Attention Button press
  69  * @lock: protects reads and writes of @state;
  70  *      protects scheduling, execution and cancellation of @work
  71  */
  72 struct slot {
  73         u8 state;
  74         struct controller *ctrl;
  75         struct hotplug_slot *hotplug_slot;
  76         struct delayed_work work;
  77         struct mutex lock;
  78 };
  79
  80 /**
  81  * struct controller - PCIe hotplug controller
  82  * @ctrl_lock: serializes writes to the Slot Control register
  83  * @pcie: pointer to the controller's PCIe port service device
  84  * @reset_lock: prevents access to the Data Link Layer Link Active bit in the
  85  *      Link Status register and to the Presence Detect State bit in the Slot
  86  *      Status register during a slot reset which may cause them to flap
  87  * @slot: pointer to the controller's slot structure
  88  * @queue: wait queue to wake up on reception of a Command Completed event,
  89  *      used for synchronous writes to the Slot Control register
  90  * @slot_cap: cached copy of the Slot Capabilities register
  91  * @slot_ctrl: cached copy of the Slot Control register
  92  * @poll_thread: thread to poll for slot events if no IRQ is available,
  93  *      enabled with pciehp_poll_mode module parameter
  94  * @cmd_started: jiffies when the Slot Control register was last written;
  95  *      the next write is allowed 1 second later, absent a Command Completed
  96  *      interrupt (PCIe r4.0, sec 6.7.3.2)
  97  * @cmd_busy: flag set on Slot Control register write, cleared by IRQ handler
  98  *      on reception of a Command Completed event
  99  * @link_active_reporting: cached copy of Data Link Layer Link Active Reporting
 100  *      Capable bit in Link Capabilities register; if this bit is zero, the
 101  *      Data Link Layer Link Active bit in the Link Status register will never
 102  *      be set and the driver is thus confined to wait 1 second before assuming
 103  *      the link to a hotplugged device is up and accessing it
 104  * @notification_enabled: whether the IRQ was requested successfully
 105  * @power_fault_detected: whether a power fault was detected by the hardware
 106  *      that has not yet been cleared by the user
 107  * @pending_events: used by the IRQ handler to save events retrieved from the
 108  *      Slot Status register for later consumption by the IRQ thread
 109  * @request_result: result of last user request submitted to the IRQ thread
 110  * @requester: wait queue to wake up on completion of user request,
 111  *      used for synchronous slot enable/disable request via sysfs
 112  */
 113 struct controller {
 114         struct mutex ctrl_lock;
 115         struct pcie_device *pcie;
 116         struct rw_semaphore reset_lock;
 117         struct slot *slot;
 118         wait_queue_head_t queue;
 119         u32 slot_cap;
 120         u16 slot_ctrl;
 121         struct task_struct *poll_thread;
 122         unsigned long cmd_started;      /* jiffies */
 123         unsigned int cmd_busy:1;
 124         unsigned int link_active_reporting:1;
 125         unsigned int notification_enabled:1;
 126         unsigned int power_fault_detected;
 127         atomic_t pending_events;
 128         int request_result;
 129         wait_queue_head_t requester;
 130 };
 131
 132 /**
 133  * DOC: Slot state
 134  *
 135  * @OFF_STATE: slot is powered off, no subordinate devices are enumerated
 136  * @BLINKINGON_STATE: slot will be powered on after the 5 second delay,
 137  *      green led is blinking
 138  * @BLINKINGOFF_STATE: slot will be powered off after the 5 second delay,
 139  *      green led is blinking
 140  * @POWERON_STATE: slot is currently powering on
 141  * @POWEROFF_STATE: slot is currently powering off
 142  * @ON_STATE: slot is powered on, subordinate devices have been enumerated
 143  */
 144 #define OFF_STATE                       0
 145 #define BLINKINGON_STATE                1
 146 #define BLINKINGOFF_STATE               2
 147 #define POWERON_STATE                   3
 148 #define POWEROFF_STATE                  4
 149 #define ON_STATE                        5
 150
 151 /**
 152  * DOC: Flags to request an action from the IRQ thread
 153  *
 154  * These are stored together with events read from the Slot Status register,
 155  * hence must be greater than its 16-bit width.
 156  *
 157  * %DISABLE_SLOT: Disable the slot in response to a user request via sysfs or
 158  *      an Attention Button press after the 5 second delay
 159  * %RERUN_ISR: Used by the IRQ handler to inform the IRQ thread that the
 160  *      hotplug port was inaccessible when the interrupt occurred, requiring
 161  *      that the IRQ handler is rerun by the IRQ thread after it has made the
 162  *      hotplug port accessible by runtime resuming its parents to D0
 163  */
 164 #define DISABLE_SLOT            (1 << 16)
 165 #define RERUN_ISR               (1 << 17)
 166
 167 #define ATTN_BUTTN(ctrl)        ((ctrl)->slot_cap & PCI_EXP_SLTCAP_ABP)
 168 #define POWER_CTRL(ctrl)        ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PCP)
 169 #define MRL_SENS(ctrl)          ((ctrl)->slot_cap & PCI_EXP_SLTCAP_MRLSP)
 170 #define ATTN_LED(ctrl)          ((ctrl)->slot_cap & PCI_EXP_SLTCAP_AIP)
 171 #define PWR_LED(ctrl)           ((ctrl)->slot_cap & PCI_EXP_SLTCAP_PIP)
 172 #define HP_SUPR_RM(ctrl)        ((ctrl)->slot_cap & PCI_EXP_SLTCAP_HPS)
 173 #define EMI(ctrl)               ((ctrl)->slot_cap & PCI_EXP_SLTCAP_EIP)
 174 #define NO_CMD_CMPL(ctrl)       ((ctrl)->slot_cap & PCI_EXP_SLTCAP_NCCS)
 175 #define PSN(ctrl)               (((ctrl)->slot_cap & PCI_EXP_SLTCAP_PSN) >> 19)
 176
 177 int pciehp_sysfs_enable_slot(struct slot *slot);
 178 int pciehp_sysfs_disable_slot(struct slot *slot);
 179 void pciehp_request(struct controller *ctrl, int action);
 180 void pciehp_handle_button_press(struct slot *slot);
 181 void pciehp_handle_disable_request(struct slot *slot);
 182 void pciehp_handle_presence_or_link_change(struct slot *slot, u32 events);
 183 int pciehp_configure_device(struct slot *p_slot);
 184 void pciehp_unconfigure_device(struct slot *p_slot);
 185 void pciehp_queue_pushbutton_work(struct work_struct *work);
 186 struct controller *pcie_init(struct pcie_device *dev);
 187 int pcie_init_notification(struct controller *ctrl);
 188 void pcie_shutdown_notification(struct controller *ctrl);
 189 void pcie_clear_hotplug_events(struct controller *ctrl);
 190 int pciehp_power_on_slot(struct slot *slot);
 191 void pciehp_power_off_slot(struct slot *slot);
 192 void pciehp_get_power_status(struct slot *slot, u8 *status);
 193 void pciehp_get_attention_status(struct slot *slot, u8 *status);
 194
 195 void pciehp_set_attention_status(struct slot *slot, u8 status);
 196 void pciehp_get_latch_status(struct slot *slot, u8 *status);
 197 void pciehp_get_adapter_status(struct slot *slot, u8 *status);
 198 int pciehp_query_power_fault(struct slot *slot);
 199 void pciehp_green_led_on(struct slot *slot);
 200 void pciehp_green_led_off(struct slot *slot);
 201 void pciehp_green_led_blink(struct slot *slot);
 202 int pciehp_check_link_status(struct controller *ctrl);
 203 bool pciehp_check_link_active(struct controller *ctrl);
 204 void pciehp_release_ctrl(struct controller *ctrl);
 205 int pciehp_reset_slot(struct slot *slot, int probe);
 206
 207 int pciehp_set_raw_indicator_status(struct hotplug_slot *h_slot, u8 status);
 208 int pciehp_get_raw_indicator_status(struct hotplug_slot *h_slot, u8 *status);
 209
 210 static inline const char *slot_name(struct slot *slot)
 211 {
 212         return hotplug_slot_name(slot->hotplug_slot);
 213 }
 214
 215 #endif                          /* _PCIEHP_H */