1 // SPDX-License-Identifier: GPL-2.0
3 * Implement the AER root port service driver. The driver registers an IRQ
4 * handler. When a root port triggers an AER interrupt, the IRQ handler
5 * collects root port status and schedules work.
7 * Copyright (C) 2006 Intel Corp.
8 * Tom Long Nguyen (tom.l.nguyen@intel.com)
9 * Zhang Yanmin (yanmin.zhang@intel.com)
11 * (C) Copyright 2009 Hewlett-Packard Development Company, L.P.
12 * Andrew Patterson <andrew.patterson@hp.com>
15 #include <linux/cper.h>
16 #include <linux/pci.h>
17 #include <linux/pci-acpi.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/kfifo.h>
26 #include <linux/slab.h>
27 #include <acpi/apei.h>
28 #include <ras/ras_event.h>
33 #define AER_ERROR_SOURCES_MAX 100
35 #define AER_MAX_TYPEOF_COR_ERRS 16 /* as per PCI_ERR_COR_STATUS */
36 #define AER_MAX_TYPEOF_UNCOR_ERRS 26 /* as per PCI_ERR_UNCOR_STATUS*/
38 struct aer_err_source
{
44 struct pci_dev
*rpd
; /* Root Port device */
45 struct work_struct dpc_handler
;
46 struct aer_err_source e_sources
[AER_ERROR_SOURCES_MAX
];
47 struct aer_err_info e_info
;
48 unsigned short prod_idx
; /* Error Producer Index */
49 unsigned short cons_idx
; /* Error Consumer Index */
52 * Lock access to Error Status/ID Regs
53 * and error producer/consumer index
55 struct mutex rpc_mutex
; /*
56 * only one thread could do
57 * recovery on the same
62 /* AER stats for the device */
66 * Fields for all AER capable devices. They indicate the errors
67 * "as seen by this device". Note that this may mean that if an
68 * end point is causing problems, the AER counters may increment
69 * at its link partner (e.g. root port) because the errors will be
70 * "seen" by the link partner and not the the problematic end point
71 * itself (which may report all counters as 0 as it never saw any
74 /* Counters for different type of correctable errors */
75 u64 dev_cor_errs
[AER_MAX_TYPEOF_COR_ERRS
];
76 /* Counters for different type of fatal uncorrectable errors */
77 u64 dev_fatal_errs
[AER_MAX_TYPEOF_UNCOR_ERRS
];
78 /* Counters for different type of nonfatal uncorrectable errors */
79 u64 dev_nonfatal_errs
[AER_MAX_TYPEOF_UNCOR_ERRS
];
80 /* Total number of ERR_COR sent by this device */
81 u64 dev_total_cor_errs
;
82 /* Total number of ERR_FATAL sent by this device */
83 u64 dev_total_fatal_errs
;
84 /* Total number of ERR_NONFATAL sent by this device */
85 u64 dev_total_nonfatal_errs
;
88 * Fields for Root ports & root complex event collectors only, these
89 * indicate the total number of ERR_COR, ERR_FATAL, and ERR_NONFATAL
90 * messages received by the root port / event collector, INCLUDING the
91 * ones that are generated internally (by the rootport itself)
93 u64 rootport_total_cor_errs
;
94 u64 rootport_total_fatal_errs
;
95 u64 rootport_total_nonfatal_errs
;
98 #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
101 PCI_ERR_UNC_COMP_ABORT| \
102 PCI_ERR_UNC_UNX_COMP| \
103 PCI_ERR_UNC_MALF_TLP)
105 #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
106 PCI_EXP_RTCTL_SENFEE| \
108 #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
109 PCI_ERR_ROOT_CMD_NONFATAL_EN| \
110 PCI_ERR_ROOT_CMD_FATAL_EN)
111 #define ERR_COR_ID(d) (d & 0xffff)
112 #define ERR_UNCOR_ID(d) (d >> 16)
114 static int pcie_aer_disable
;
116 void pci_no_aer(void)
118 pcie_aer_disable
= 1;
121 bool pci_aer_available(void)
123 return !pcie_aer_disable
&& pci_msi_enabled();
126 #ifdef CONFIG_PCIE_ECRC
128 #define ECRC_POLICY_DEFAULT 0 /* ECRC set by BIOS */
129 #define ECRC_POLICY_OFF 1 /* ECRC off for performance */
130 #define ECRC_POLICY_ON 2 /* ECRC on for data integrity */
132 static int ecrc_policy
= ECRC_POLICY_DEFAULT
;
134 static const char *ecrc_policy_str
[] = {
135 [ECRC_POLICY_DEFAULT
] = "bios",
136 [ECRC_POLICY_OFF
] = "off",
137 [ECRC_POLICY_ON
] = "on"
141 * enable_ercr_checking - enable PCIe ECRC checking for a device
142 * @dev: the PCI device
144 * Returns 0 on success, or negative on failure.
146 static int enable_ecrc_checking(struct pci_dev
*dev
)
151 if (!pci_is_pcie(dev
))
158 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
159 if (reg32
& PCI_ERR_CAP_ECRC_GENC
)
160 reg32
|= PCI_ERR_CAP_ECRC_GENE
;
161 if (reg32
& PCI_ERR_CAP_ECRC_CHKC
)
162 reg32
|= PCI_ERR_CAP_ECRC_CHKE
;
163 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
169 * disable_ercr_checking - disables PCIe ECRC checking for a device
170 * @dev: the PCI device
172 * Returns 0 on success, or negative on failure.
174 static int disable_ecrc_checking(struct pci_dev
*dev
)
179 if (!pci_is_pcie(dev
))
186 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
187 reg32
&= ~(PCI_ERR_CAP_ECRC_GENE
| PCI_ERR_CAP_ECRC_CHKE
);
188 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
194 * pcie_set_ecrc_checking - set/unset PCIe ECRC checking for a device based on global policy
195 * @dev: the PCI device
197 void pcie_set_ecrc_checking(struct pci_dev
*dev
)
199 switch (ecrc_policy
) {
200 case ECRC_POLICY_DEFAULT
:
202 case ECRC_POLICY_OFF
:
203 disable_ecrc_checking(dev
);
206 enable_ecrc_checking(dev
);
214 * pcie_ecrc_get_policy - parse kernel command-line ecrc option
216 void pcie_ecrc_get_policy(char *str
)
220 for (i
= 0; i
< ARRAY_SIZE(ecrc_policy_str
); i
++)
221 if (!strncmp(str
, ecrc_policy_str
[i
],
222 strlen(ecrc_policy_str
[i
])))
224 if (i
>= ARRAY_SIZE(ecrc_policy_str
))
229 #endif /* CONFIG_PCIE_ECRC */
231 #ifdef CONFIG_ACPI_APEI
232 static inline int hest_match_pci(struct acpi_hest_aer_common
*p
,
235 return ACPI_HEST_SEGMENT(p
->bus
) == pci_domain_nr(pci
->bus
) &&
236 ACPI_HEST_BUS(p
->bus
) == pci
->bus
->number
&&
237 p
->device
== PCI_SLOT(pci
->devfn
) &&
238 p
->function
== PCI_FUNC(pci
->devfn
);
241 static inline bool hest_match_type(struct acpi_hest_header
*hest_hdr
,
244 u16 hest_type
= hest_hdr
->type
;
245 u8 pcie_type
= pci_pcie_type(dev
);
247 if ((hest_type
== ACPI_HEST_TYPE_AER_ROOT_PORT
&&
248 pcie_type
== PCI_EXP_TYPE_ROOT_PORT
) ||
249 (hest_type
== ACPI_HEST_TYPE_AER_ENDPOINT
&&
250 pcie_type
== PCI_EXP_TYPE_ENDPOINT
) ||
251 (hest_type
== ACPI_HEST_TYPE_AER_BRIDGE
&&
252 (dev
->class >> 16) == PCI_BASE_CLASS_BRIDGE
))
257 struct aer_hest_parse_info
{
258 struct pci_dev
*pci_dev
;
262 static int hest_source_is_pcie_aer(struct acpi_hest_header
*hest_hdr
)
264 if (hest_hdr
->type
== ACPI_HEST_TYPE_AER_ROOT_PORT
||
265 hest_hdr
->type
== ACPI_HEST_TYPE_AER_ENDPOINT
||
266 hest_hdr
->type
== ACPI_HEST_TYPE_AER_BRIDGE
)
271 static int aer_hest_parse(struct acpi_hest_header
*hest_hdr
, void *data
)
273 struct aer_hest_parse_info
*info
= data
;
274 struct acpi_hest_aer_common
*p
;
277 if (!hest_source_is_pcie_aer(hest_hdr
))
280 p
= (struct acpi_hest_aer_common
*)(hest_hdr
+ 1);
281 ff
= !!(p
->flags
& ACPI_HEST_FIRMWARE_FIRST
);
284 * If no specific device is supplied, determine whether
285 * FIRMWARE_FIRST is set for *any* PCIe device.
287 if (!info
->pci_dev
) {
288 info
->firmware_first
|= ff
;
292 /* Otherwise, check the specific device */
293 if (p
->flags
& ACPI_HEST_GLOBAL
) {
294 if (hest_match_type(hest_hdr
, info
->pci_dev
))
295 info
->firmware_first
= ff
;
297 if (hest_match_pci(p
, info
->pci_dev
))
298 info
->firmware_first
= ff
;
303 static void aer_set_firmware_first(struct pci_dev
*pci_dev
)
306 struct aer_hest_parse_info info
= {
311 rc
= apei_hest_parse(aer_hest_parse
, &info
);
314 pci_dev
->__aer_firmware_first
= 0;
316 pci_dev
->__aer_firmware_first
= info
.firmware_first
;
317 pci_dev
->__aer_firmware_first_valid
= 1;
320 int pcie_aer_get_firmware_first(struct pci_dev
*dev
)
322 if (!pci_is_pcie(dev
))
325 if (pcie_ports_native
)
328 if (!dev
->__aer_firmware_first_valid
)
329 aer_set_firmware_first(dev
);
330 return dev
->__aer_firmware_first
;
333 static bool aer_firmware_first
;
336 * aer_acpi_firmware_first - Check if APEI should control AER.
338 bool aer_acpi_firmware_first(void)
340 static bool parsed
= false;
341 struct aer_hest_parse_info info
= {
342 .pci_dev
= NULL
, /* Check all PCIe devices */
346 if (pcie_ports_native
)
350 apei_hest_parse(aer_hest_parse
, &info
);
351 aer_firmware_first
= info
.firmware_first
;
354 return aer_firmware_first
;
358 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \
359 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE)
361 int pci_enable_pcie_error_reporting(struct pci_dev
*dev
)
363 if (pcie_aer_get_firmware_first(dev
))
369 return pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_AER_FLAGS
);
371 EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting
);
373 int pci_disable_pcie_error_reporting(struct pci_dev
*dev
)
375 if (pcie_aer_get_firmware_first(dev
))
378 return pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
381 EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting
);
383 void pci_aer_clear_device_status(struct pci_dev
*dev
)
387 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &sta
);
388 pcie_capability_write_word(dev
, PCI_EXP_DEVSTA
, sta
);
391 int pci_cleanup_aer_uncorrect_error_status(struct pci_dev
*dev
)
400 if (pcie_aer_get_firmware_first(dev
))
403 /* Clear status bits for ERR_NONFATAL errors only */
404 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
405 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, &sev
);
408 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, status
);
412 EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status
);
414 void pci_aer_clear_fatal_status(struct pci_dev
*dev
)
423 if (pcie_aer_get_firmware_first(dev
))
426 /* Clear status bits for ERR_FATAL errors only */
427 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
428 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, &sev
);
431 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, status
);
434 int pci_cleanup_aer_error_status_regs(struct pci_dev
*dev
)
440 if (!pci_is_pcie(dev
))
447 if (pcie_aer_get_firmware_first(dev
))
450 port_type
= pci_pcie_type(dev
);
451 if (port_type
== PCI_EXP_TYPE_ROOT_PORT
) {
452 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, &status
);
453 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, status
);
456 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, &status
);
457 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, status
);
459 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
460 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, status
);
465 void pci_aer_init(struct pci_dev
*dev
)
467 dev
->aer_cap
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
470 dev
->aer_stats
= kzalloc(sizeof(struct aer_stats
), GFP_KERNEL
);
472 pci_cleanup_aer_error_status_regs(dev
);
475 void pci_aer_exit(struct pci_dev
*dev
)
477 kfree(dev
->aer_stats
);
478 dev
->aer_stats
= NULL
;
481 #define AER_AGENT_RECEIVER 0
482 #define AER_AGENT_REQUESTER 1
483 #define AER_AGENT_COMPLETER 2
484 #define AER_AGENT_TRANSMITTER 3
486 #define AER_AGENT_REQUESTER_MASK(t) ((t == AER_CORRECTABLE) ? \
487 0 : (PCI_ERR_UNC_COMP_TIME|PCI_ERR_UNC_UNSUP))
488 #define AER_AGENT_COMPLETER_MASK(t) ((t == AER_CORRECTABLE) ? \
489 0 : PCI_ERR_UNC_COMP_ABORT)
490 #define AER_AGENT_TRANSMITTER_MASK(t) ((t == AER_CORRECTABLE) ? \
491 (PCI_ERR_COR_REP_ROLL|PCI_ERR_COR_REP_TIMER) : 0)
493 #define AER_GET_AGENT(t, e) \
494 ((e & AER_AGENT_COMPLETER_MASK(t)) ? AER_AGENT_COMPLETER : \
495 (e & AER_AGENT_REQUESTER_MASK(t)) ? AER_AGENT_REQUESTER : \
496 (e & AER_AGENT_TRANSMITTER_MASK(t)) ? AER_AGENT_TRANSMITTER : \
499 #define AER_PHYSICAL_LAYER_ERROR 0
500 #define AER_DATA_LINK_LAYER_ERROR 1
501 #define AER_TRANSACTION_LAYER_ERROR 2
503 #define AER_PHYSICAL_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
504 PCI_ERR_COR_RCVR : 0)
505 #define AER_DATA_LINK_LAYER_ERROR_MASK(t) ((t == AER_CORRECTABLE) ? \
506 (PCI_ERR_COR_BAD_TLP| \
507 PCI_ERR_COR_BAD_DLLP| \
508 PCI_ERR_COR_REP_ROLL| \
509 PCI_ERR_COR_REP_TIMER) : PCI_ERR_UNC_DLP)
511 #define AER_GET_LAYER_ERROR(t, e) \
512 ((e & AER_PHYSICAL_LAYER_ERROR_MASK(t)) ? AER_PHYSICAL_LAYER_ERROR : \
513 (e & AER_DATA_LINK_LAYER_ERROR_MASK(t)) ? AER_DATA_LINK_LAYER_ERROR : \
514 AER_TRANSACTION_LAYER_ERROR)
519 static const char *aer_error_severity_string
[] = {
520 "Uncorrected (Non-Fatal)",
521 "Uncorrected (Fatal)",
525 static const char *aer_error_layer
[] = {
531 static const char *aer_correctable_error_string
[AER_MAX_TYPEOF_COR_ERRS
] = {
532 "RxErr", /* Bit Position 0 */
538 "BadTLP", /* Bit Position 6 */
539 "BadDLLP", /* Bit Position 7 */
540 "Rollover", /* Bit Position 8 */
544 "Timeout", /* Bit Position 12 */
545 "NonFatalErr", /* Bit Position 13 */
546 "CorrIntErr", /* Bit Position 14 */
547 "HeaderOF", /* Bit Position 15 */
550 static const char *aer_uncorrectable_error_string
[AER_MAX_TYPEOF_UNCOR_ERRS
] = {
551 "Undefined", /* Bit Position 0 */
555 "DLP", /* Bit Position 4 */
556 "SDES", /* Bit Position 5 */
563 "TLP", /* Bit Position 12 */
564 "FCP", /* Bit Position 13 */
565 "CmpltTO", /* Bit Position 14 */
566 "CmpltAbrt", /* Bit Position 15 */
567 "UnxCmplt", /* Bit Position 16 */
568 "RxOF", /* Bit Position 17 */
569 "MalfTLP", /* Bit Position 18 */
570 "ECRC", /* Bit Position 19 */
571 "UnsupReq", /* Bit Position 20 */
572 "ACSViol", /* Bit Position 21 */
573 "UncorrIntErr", /* Bit Position 22 */
574 "BlockedTLP", /* Bit Position 23 */
575 "AtomicOpBlocked", /* Bit Position 24 */
576 "TLPBlockedErr", /* Bit Position 25 */
579 static const char *aer_agent_string
[] = {
586 #define aer_stats_dev_attr(name, stats_array, strings_array, \
587 total_string, total_field) \
589 name##_show(struct device *dev, struct device_attribute *attr, \
594 struct pci_dev *pdev = to_pci_dev(dev); \
595 u64 *stats = pdev->aer_stats->stats_array; \
597 for (i = 0; i < ARRAY_SIZE(strings_array); i++) { \
598 if (strings_array[i]) \
599 str += sprintf(str, "%s %llu\n", \
600 strings_array[i], stats[i]); \
602 str += sprintf(str, #stats_array "_bit[%d] %llu\n",\
605 str += sprintf(str, "TOTAL_%s %llu\n", total_string, \
606 pdev->aer_stats->total_field); \
609 static DEVICE_ATTR_RO(name)
611 aer_stats_dev_attr(aer_dev_correctable
, dev_cor_errs
,
612 aer_correctable_error_string
, "ERR_COR",
614 aer_stats_dev_attr(aer_dev_fatal
, dev_fatal_errs
,
615 aer_uncorrectable_error_string
, "ERR_FATAL",
616 dev_total_fatal_errs
);
617 aer_stats_dev_attr(aer_dev_nonfatal
, dev_nonfatal_errs
,
618 aer_uncorrectable_error_string
, "ERR_NONFATAL",
619 dev_total_nonfatal_errs
);
621 #define aer_stats_rootport_attr(name, field) \
623 name##_show(struct device *dev, struct device_attribute *attr, \
626 struct pci_dev *pdev = to_pci_dev(dev); \
627 return sprintf(buf, "%llu\n", pdev->aer_stats->field); \
629 static DEVICE_ATTR_RO(name)
631 aer_stats_rootport_attr(aer_rootport_total_err_cor
,
632 rootport_total_cor_errs
);
633 aer_stats_rootport_attr(aer_rootport_total_err_fatal
,
634 rootport_total_fatal_errs
);
635 aer_stats_rootport_attr(aer_rootport_total_err_nonfatal
,
636 rootport_total_nonfatal_errs
);
638 static struct attribute
*aer_stats_attrs
[] __ro_after_init
= {
639 &dev_attr_aer_dev_correctable
.attr
,
640 &dev_attr_aer_dev_fatal
.attr
,
641 &dev_attr_aer_dev_nonfatal
.attr
,
642 &dev_attr_aer_rootport_total_err_cor
.attr
,
643 &dev_attr_aer_rootport_total_err_fatal
.attr
,
644 &dev_attr_aer_rootport_total_err_nonfatal
.attr
,
648 static umode_t
aer_stats_attrs_are_visible(struct kobject
*kobj
,
649 struct attribute
*a
, int n
)
651 struct device
*dev
= kobj_to_dev(kobj
);
652 struct pci_dev
*pdev
= to_pci_dev(dev
);
654 if (!pdev
->aer_stats
)
657 if ((a
== &dev_attr_aer_rootport_total_err_cor
.attr
||
658 a
== &dev_attr_aer_rootport_total_err_fatal
.attr
||
659 a
== &dev_attr_aer_rootport_total_err_nonfatal
.attr
) &&
660 pci_pcie_type(pdev
) != PCI_EXP_TYPE_ROOT_PORT
)
666 const struct attribute_group aer_stats_attr_group
= {
667 .attrs
= aer_stats_attrs
,
668 .is_visible
= aer_stats_attrs_are_visible
,
671 static void pci_dev_aer_stats_incr(struct pci_dev
*pdev
,
672 struct aer_err_info
*info
)
674 int status
, i
, max
= -1;
676 struct aer_stats
*aer_stats
= pdev
->aer_stats
;
681 switch (info
->severity
) {
682 case AER_CORRECTABLE
:
683 aer_stats
->dev_total_cor_errs
++;
684 counter
= &aer_stats
->dev_cor_errs
[0];
685 max
= AER_MAX_TYPEOF_COR_ERRS
;
688 aer_stats
->dev_total_nonfatal_errs
++;
689 counter
= &aer_stats
->dev_nonfatal_errs
[0];
690 max
= AER_MAX_TYPEOF_UNCOR_ERRS
;
693 aer_stats
->dev_total_fatal_errs
++;
694 counter
= &aer_stats
->dev_fatal_errs
[0];
695 max
= AER_MAX_TYPEOF_UNCOR_ERRS
;
699 status
= (info
->status
& ~info
->mask
);
700 for (i
= 0; i
< max
; i
++)
701 if (status
& (1 << i
))
705 static void pci_rootport_aer_stats_incr(struct pci_dev
*pdev
,
706 struct aer_err_source
*e_src
)
708 struct aer_stats
*aer_stats
= pdev
->aer_stats
;
713 if (e_src
->status
& PCI_ERR_ROOT_COR_RCV
)
714 aer_stats
->rootport_total_cor_errs
++;
716 if (e_src
->status
& PCI_ERR_ROOT_UNCOR_RCV
) {
717 if (e_src
->status
& PCI_ERR_ROOT_FATAL_RCV
)
718 aer_stats
->rootport_total_fatal_errs
++;
720 aer_stats
->rootport_total_nonfatal_errs
++;
724 static void __print_tlp_header(struct pci_dev
*dev
,
725 struct aer_header_log_regs
*t
)
727 pci_err(dev
, " TLP Header: %08x %08x %08x %08x\n",
728 t
->dw0
, t
->dw1
, t
->dw2
, t
->dw3
);
731 static void __aer_print_error(struct pci_dev
*dev
,
732 struct aer_err_info
*info
)
735 const char *errmsg
= NULL
;
736 status
= (info
->status
& ~info
->mask
);
738 for (i
= 0; i
< 32; i
++) {
739 if (!(status
& (1 << i
)))
742 if (info
->severity
== AER_CORRECTABLE
)
743 errmsg
= i
< ARRAY_SIZE(aer_correctable_error_string
) ?
744 aer_correctable_error_string
[i
] : NULL
;
746 errmsg
= i
< ARRAY_SIZE(aer_uncorrectable_error_string
) ?
747 aer_uncorrectable_error_string
[i
] : NULL
;
750 pci_err(dev
, " [%2d] %-22s%s\n", i
, errmsg
,
751 info
->first_error
== i
? " (First)" : "");
753 pci_err(dev
, " [%2d] Unknown Error Bit%s\n",
754 i
, info
->first_error
== i
? " (First)" : "");
756 pci_dev_aer_stats_incr(dev
, info
);
759 void aer_print_error(struct pci_dev
*dev
, struct aer_err_info
*info
)
762 int id
= ((dev
->bus
->number
<< 8) | dev
->devfn
);
765 pci_err(dev
, "PCIe Bus Error: severity=%s, type=Inaccessible, (Unregistered Agent ID)\n",
766 aer_error_severity_string
[info
->severity
]);
770 layer
= AER_GET_LAYER_ERROR(info
->severity
, info
->status
);
771 agent
= AER_GET_AGENT(info
->severity
, info
->status
);
773 pci_err(dev
, "PCIe Bus Error: severity=%s, type=%s, (%s)\n",
774 aer_error_severity_string
[info
->severity
],
775 aer_error_layer
[layer
], aer_agent_string
[agent
]);
777 pci_err(dev
, " device [%04x:%04x] error status/mask=%08x/%08x\n",
778 dev
->vendor
, dev
->device
,
779 info
->status
, info
->mask
);
781 __aer_print_error(dev
, info
);
783 if (info
->tlp_header_valid
)
784 __print_tlp_header(dev
, &info
->tlp
);
787 if (info
->id
&& info
->error_dev_num
> 1 && info
->id
== id
)
788 pci_err(dev
, " Error of this Agent is reported first\n");
790 trace_aer_event(dev_name(&dev
->dev
), (info
->status
& ~info
->mask
),
791 info
->severity
, info
->tlp_header_valid
, &info
->tlp
);
794 static void aer_print_port_info(struct pci_dev
*dev
, struct aer_err_info
*info
)
796 u8 bus
= info
->id
>> 8;
797 u8 devfn
= info
->id
& 0xff;
799 pci_info(dev
, "AER: %s%s error received: %04x:%02x:%02x.%d\n",
800 info
->multi_error_valid
? "Multiple " : "",
801 aer_error_severity_string
[info
->severity
],
802 pci_domain_nr(dev
->bus
), bus
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
805 #ifdef CONFIG_ACPI_APEI_PCIEAER
806 int cper_severity_to_aer(int cper_severity
)
808 switch (cper_severity
) {
809 case CPER_SEV_RECOVERABLE
:
814 return AER_CORRECTABLE
;
817 EXPORT_SYMBOL_GPL(cper_severity_to_aer
);
819 void cper_print_aer(struct pci_dev
*dev
, int aer_severity
,
820 struct aer_capability_regs
*aer
)
822 int layer
, agent
, tlp_header_valid
= 0;
824 struct aer_err_info info
;
826 if (aer_severity
== AER_CORRECTABLE
) {
827 status
= aer
->cor_status
;
828 mask
= aer
->cor_mask
;
830 status
= aer
->uncor_status
;
831 mask
= aer
->uncor_mask
;
832 tlp_header_valid
= status
& AER_LOG_TLP_MASKS
;
835 layer
= AER_GET_LAYER_ERROR(aer_severity
, status
);
836 agent
= AER_GET_AGENT(aer_severity
, status
);
838 memset(&info
, 0, sizeof(info
));
839 info
.severity
= aer_severity
;
840 info
.status
= status
;
842 info
.first_error
= PCI_ERR_CAP_FEP(aer
->cap_control
);
844 pci_err(dev
, "aer_status: 0x%08x, aer_mask: 0x%08x\n", status
, mask
);
845 __aer_print_error(dev
, &info
);
846 pci_err(dev
, "aer_layer=%s, aer_agent=%s\n",
847 aer_error_layer
[layer
], aer_agent_string
[agent
]);
849 if (aer_severity
!= AER_CORRECTABLE
)
850 pci_err(dev
, "aer_uncor_severity: 0x%08x\n",
851 aer
->uncor_severity
);
853 if (tlp_header_valid
)
854 __print_tlp_header(dev
, &aer
->header_log
);
856 trace_aer_event(dev_name(&dev
->dev
), (status
& ~mask
),
857 aer_severity
, tlp_header_valid
, &aer
->header_log
);
862 * add_error_device - list device to be handled
863 * @e_info: pointer to error info
864 * @dev: pointer to pci_dev to be added
866 static int add_error_device(struct aer_err_info
*e_info
, struct pci_dev
*dev
)
868 if (e_info
->error_dev_num
< AER_MAX_MULTI_ERR_DEVICES
) {
869 e_info
->dev
[e_info
->error_dev_num
] = dev
;
870 e_info
->error_dev_num
++;
877 * is_error_source - check whether the device is source of reported error
878 * @dev: pointer to pci_dev to be checked
879 * @e_info: pointer to reported error info
881 static bool is_error_source(struct pci_dev
*dev
, struct aer_err_info
*e_info
)
888 * When bus id is equal to 0, it might be a bad id
889 * reported by root port.
891 if ((PCI_BUS_NUM(e_info
->id
) != 0) &&
892 !(dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_AERSID
)) {
893 /* Device ID match? */
894 if (e_info
->id
== ((dev
->bus
->number
<< 8) | dev
->devfn
))
897 /* Continue id comparing if there is no multiple error */
898 if (!e_info
->multi_error_valid
)
904 * 1) bus id is equal to 0. Some ports might lose the bus
905 * id of error source id;
906 * 2) bus flag PCI_BUS_FLAGS_NO_AERSID is set
907 * 3) There are multiple errors and prior ID comparing fails;
908 * We check AER status registers to find possible reporter.
910 if (atomic_read(&dev
->enable_cnt
) == 0)
913 /* Check if AER is enabled */
914 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, ®16
);
915 if (!(reg16
& PCI_EXP_AER_FLAGS
))
922 /* Check if error is recorded */
923 if (e_info
->severity
== AER_CORRECTABLE
) {
924 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
, &status
);
925 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, &mask
);
927 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
, &status
);
928 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, &mask
);
936 static int find_device_iter(struct pci_dev
*dev
, void *data
)
938 struct aer_err_info
*e_info
= (struct aer_err_info
*)data
;
940 if (is_error_source(dev
, e_info
)) {
941 /* List this device */
942 if (add_error_device(e_info
, dev
)) {
943 /* We cannot handle more... Stop iteration */
944 /* TODO: Should print error message here? */
948 /* If there is only a single error, stop iteration */
949 if (!e_info
->multi_error_valid
)
956 * find_source_device - search through device hierarchy for source device
957 * @parent: pointer to Root Port pci_dev data structure
958 * @e_info: including detailed error information such like id
960 * Return true if found.
962 * Invoked by DPC when error is detected at the Root Port.
963 * Caller of this function must set id, severity, and multi_error_valid of
964 * struct aer_err_info pointed by @e_info properly. This function must fill
965 * e_info->error_dev_num and e_info->dev[], based on the given information.
967 static bool find_source_device(struct pci_dev
*parent
,
968 struct aer_err_info
*e_info
)
970 struct pci_dev
*dev
= parent
;
973 /* Must reset in this function */
974 e_info
->error_dev_num
= 0;
976 /* Is Root Port an agent that sends error message? */
977 result
= find_device_iter(dev
, e_info
);
981 pci_walk_bus(parent
->subordinate
, find_device_iter
, e_info
);
983 if (!e_info
->error_dev_num
) {
984 pci_printk(KERN_DEBUG
, parent
, "can't find device of ID%04x\n",
992 * handle_error_source - handle logging error into an event log
993 * @dev: pointer to pci_dev data structure of error source device
994 * @info: comprehensive error information
996 * Invoked when an error being detected by Root Port.
998 static void handle_error_source(struct pci_dev
*dev
, struct aer_err_info
*info
)
1002 if (info
->severity
== AER_CORRECTABLE
) {
1004 * Correctable error does not need software intervention.
1005 * No need to go through error recovery process.
1009 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
,
1011 pci_aer_clear_device_status(dev
);
1012 } else if (info
->severity
== AER_NONFATAL
)
1013 pcie_do_nonfatal_recovery(dev
);
1014 else if (info
->severity
== AER_FATAL
)
1015 pcie_do_fatal_recovery(dev
, PCIE_PORT_SERVICE_AER
);
1018 #ifdef CONFIG_ACPI_APEI_PCIEAER
1020 #define AER_RECOVER_RING_ORDER 4
1021 #define AER_RECOVER_RING_SIZE (1 << AER_RECOVER_RING_ORDER)
1023 struct aer_recover_entry
{
1028 struct aer_capability_regs
*regs
;
1031 static DEFINE_KFIFO(aer_recover_ring
, struct aer_recover_entry
,
1032 AER_RECOVER_RING_SIZE
);
1034 static void aer_recover_work_func(struct work_struct
*work
)
1036 struct aer_recover_entry entry
;
1037 struct pci_dev
*pdev
;
1039 while (kfifo_get(&aer_recover_ring
, &entry
)) {
1040 pdev
= pci_get_domain_bus_and_slot(entry
.domain
, entry
.bus
,
1043 pr_err("AER recover: Can not find pci_dev for %04x:%02x:%02x:%x\n",
1044 entry
.domain
, entry
.bus
,
1045 PCI_SLOT(entry
.devfn
), PCI_FUNC(entry
.devfn
));
1048 cper_print_aer(pdev
, entry
.severity
, entry
.regs
);
1049 if (entry
.severity
== AER_NONFATAL
)
1050 pcie_do_nonfatal_recovery(pdev
);
1051 else if (entry
.severity
== AER_FATAL
)
1052 pcie_do_fatal_recovery(pdev
, PCIE_PORT_SERVICE_AER
);
1058 * Mutual exclusion for writers of aer_recover_ring, reader side don't
1059 * need lock, because there is only one reader and lock is not needed
1060 * between reader and writer.
1062 static DEFINE_SPINLOCK(aer_recover_ring_lock
);
1063 static DECLARE_WORK(aer_recover_work
, aer_recover_work_func
);
1065 void aer_recover_queue(int domain
, unsigned int bus
, unsigned int devfn
,
1066 int severity
, struct aer_capability_regs
*aer_regs
)
1068 unsigned long flags
;
1069 struct aer_recover_entry entry
= {
1073 .severity
= severity
,
1077 spin_lock_irqsave(&aer_recover_ring_lock
, flags
);
1078 if (kfifo_put(&aer_recover_ring
, entry
))
1079 schedule_work(&aer_recover_work
);
1081 pr_err("AER recover: Buffer overflow when recovering AER for %04x:%02x:%02x:%x\n",
1082 domain
, bus
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
1083 spin_unlock_irqrestore(&aer_recover_ring_lock
, flags
);
1085 EXPORT_SYMBOL_GPL(aer_recover_queue
);
1089 * aer_get_device_error_info - read error status from dev and store it to info
1090 * @dev: pointer to the device expected to have a error record
1091 * @info: pointer to structure to store the error record
1093 * Return 1 on success, 0 on error.
1095 * Note that @info is reused among all error devices. Clear fields properly.
1097 int aer_get_device_error_info(struct pci_dev
*dev
, struct aer_err_info
*info
)
1101 /* Must reset in this function */
1103 info
->tlp_header_valid
= 0;
1107 /* The device might not support AER */
1111 if (info
->severity
== AER_CORRECTABLE
) {
1112 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_STATUS
,
1114 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
,
1116 if (!(info
->status
& ~info
->mask
))
1118 } else if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1119 info
->severity
== AER_NONFATAL
) {
1121 /* Link is still healthy for IO reads */
1122 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_STATUS
,
1124 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
,
1126 if (!(info
->status
& ~info
->mask
))
1129 /* Get First Error Pointer */
1130 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, &temp
);
1131 info
->first_error
= PCI_ERR_CAP_FEP(temp
);
1133 if (info
->status
& AER_LOG_TLP_MASKS
) {
1134 info
->tlp_header_valid
= 1;
1135 pci_read_config_dword(dev
,
1136 pos
+ PCI_ERR_HEADER_LOG
, &info
->tlp
.dw0
);
1137 pci_read_config_dword(dev
,
1138 pos
+ PCI_ERR_HEADER_LOG
+ 4, &info
->tlp
.dw1
);
1139 pci_read_config_dword(dev
,
1140 pos
+ PCI_ERR_HEADER_LOG
+ 8, &info
->tlp
.dw2
);
1141 pci_read_config_dword(dev
,
1142 pos
+ PCI_ERR_HEADER_LOG
+ 12, &info
->tlp
.dw3
);
1149 static inline void aer_process_err_devices(struct aer_err_info
*e_info
)
1153 /* Report all before handle them, not to lost records by reset etc. */
1154 for (i
= 0; i
< e_info
->error_dev_num
&& e_info
->dev
[i
]; i
++) {
1155 if (aer_get_device_error_info(e_info
->dev
[i
], e_info
))
1156 aer_print_error(e_info
->dev
[i
], e_info
);
1158 for (i
= 0; i
< e_info
->error_dev_num
&& e_info
->dev
[i
]; i
++) {
1159 if (aer_get_device_error_info(e_info
->dev
[i
], e_info
))
1160 handle_error_source(e_info
->dev
[i
], e_info
);
1165 * aer_isr_one_error - consume an error detected by root port
1166 * @rpc: pointer to the root port which holds an error
1167 * @e_src: pointer to an error source
1169 static void aer_isr_one_error(struct aer_rpc
*rpc
,
1170 struct aer_err_source
*e_src
)
1172 struct pci_dev
*pdev
= rpc
->rpd
;
1173 struct aer_err_info
*e_info
= &rpc
->e_info
;
1175 pci_rootport_aer_stats_incr(pdev
, e_src
);
1178 * There is a possibility that both correctable error and
1179 * uncorrectable error being logged. Report correctable error first.
1181 if (e_src
->status
& PCI_ERR_ROOT_COR_RCV
) {
1182 e_info
->id
= ERR_COR_ID(e_src
->id
);
1183 e_info
->severity
= AER_CORRECTABLE
;
1185 if (e_src
->status
& PCI_ERR_ROOT_MULTI_COR_RCV
)
1186 e_info
->multi_error_valid
= 1;
1188 e_info
->multi_error_valid
= 0;
1189 aer_print_port_info(pdev
, e_info
);
1191 if (find_source_device(pdev
, e_info
))
1192 aer_process_err_devices(e_info
);
1195 if (e_src
->status
& PCI_ERR_ROOT_UNCOR_RCV
) {
1196 e_info
->id
= ERR_UNCOR_ID(e_src
->id
);
1198 if (e_src
->status
& PCI_ERR_ROOT_FATAL_RCV
)
1199 e_info
->severity
= AER_FATAL
;
1201 e_info
->severity
= AER_NONFATAL
;
1203 if (e_src
->status
& PCI_ERR_ROOT_MULTI_UNCOR_RCV
)
1204 e_info
->multi_error_valid
= 1;
1206 e_info
->multi_error_valid
= 0;
1208 aer_print_port_info(pdev
, e_info
);
1210 if (find_source_device(pdev
, e_info
))
1211 aer_process_err_devices(e_info
);
1216 * get_e_source - retrieve an error source
1217 * @rpc: pointer to the root port which holds an error
1218 * @e_src: pointer to store retrieved error source
1220 * Return 1 if an error source is retrieved, otherwise 0.
1222 * Invoked by DPC handler to consume an error.
1224 static int get_e_source(struct aer_rpc
*rpc
, struct aer_err_source
*e_src
)
1226 unsigned long flags
;
1228 /* Lock access to Root error producer/consumer index */
1229 spin_lock_irqsave(&rpc
->e_lock
, flags
);
1230 if (rpc
->prod_idx
== rpc
->cons_idx
) {
1231 spin_unlock_irqrestore(&rpc
->e_lock
, flags
);
1235 *e_src
= rpc
->e_sources
[rpc
->cons_idx
];
1237 if (rpc
->cons_idx
== AER_ERROR_SOURCES_MAX
)
1239 spin_unlock_irqrestore(&rpc
->e_lock
, flags
);
1245 * aer_isr - consume errors detected by root port
1246 * @work: definition of this work item
1248 * Invoked, as DPC, when root port records new detected error
1250 static void aer_isr(struct work_struct
*work
)
1252 struct aer_rpc
*rpc
= container_of(work
, struct aer_rpc
, dpc_handler
);
1253 struct aer_err_source
uninitialized_var(e_src
);
1255 mutex_lock(&rpc
->rpc_mutex
);
1256 while (get_e_source(rpc
, &e_src
))
1257 aer_isr_one_error(rpc
, &e_src
);
1258 mutex_unlock(&rpc
->rpc_mutex
);
1262 * aer_irq - Root Port's ISR
1263 * @irq: IRQ assigned to Root Port
1264 * @context: pointer to Root Port data structure
1266 * Invoked when Root Port detects AER messages.
1268 irqreturn_t
aer_irq(int irq
, void *context
)
1270 unsigned int status
, id
;
1271 struct pcie_device
*pdev
= (struct pcie_device
*)context
;
1272 struct aer_rpc
*rpc
= get_service_data(pdev
);
1274 unsigned long flags
;
1277 pos
= pdev
->port
->aer_cap
;
1279 * Must lock access to Root Error Status Reg, Root Error ID Reg,
1280 * and Root error producer/consumer index
1282 spin_lock_irqsave(&rpc
->e_lock
, flags
);
1284 /* Read error status */
1285 pci_read_config_dword(pdev
->port
, pos
+ PCI_ERR_ROOT_STATUS
, &status
);
1286 if (!(status
& (PCI_ERR_ROOT_UNCOR_RCV
|PCI_ERR_ROOT_COR_RCV
))) {
1287 spin_unlock_irqrestore(&rpc
->e_lock
, flags
);
1291 /* Read error source and clear error status */
1292 pci_read_config_dword(pdev
->port
, pos
+ PCI_ERR_ROOT_ERR_SRC
, &id
);
1293 pci_write_config_dword(pdev
->port
, pos
+ PCI_ERR_ROOT_STATUS
, status
);
1295 /* Store error source for later DPC handler */
1296 next_prod_idx
= rpc
->prod_idx
+ 1;
1297 if (next_prod_idx
== AER_ERROR_SOURCES_MAX
)
1299 if (next_prod_idx
== rpc
->cons_idx
) {
1301 * Error Storm Condition - possibly the same error occurred.
1304 spin_unlock_irqrestore(&rpc
->e_lock
, flags
);
1307 rpc
->e_sources
[rpc
->prod_idx
].status
= status
;
1308 rpc
->e_sources
[rpc
->prod_idx
].id
= id
;
1309 rpc
->prod_idx
= next_prod_idx
;
1310 spin_unlock_irqrestore(&rpc
->e_lock
, flags
);
1312 /* Invoke DPC handler */
1313 schedule_work(&rpc
->dpc_handler
);
1317 EXPORT_SYMBOL_GPL(aer_irq
);
1319 static int set_device_error_reporting(struct pci_dev
*dev
, void *data
)
1321 bool enable
= *((bool *)data
);
1322 int type
= pci_pcie_type(dev
);
1324 if ((type
== PCI_EXP_TYPE_ROOT_PORT
) ||
1325 (type
== PCI_EXP_TYPE_UPSTREAM
) ||
1326 (type
== PCI_EXP_TYPE_DOWNSTREAM
)) {
1328 pci_enable_pcie_error_reporting(dev
);
1330 pci_disable_pcie_error_reporting(dev
);
1334 pcie_set_ecrc_checking(dev
);
1340 * set_downstream_devices_error_reporting - enable/disable the error reporting bits on the root port and its downstream ports.
1341 * @dev: pointer to root port's pci_dev data structure
1342 * @enable: true = enable error reporting, false = disable error reporting.
1344 static void set_downstream_devices_error_reporting(struct pci_dev
*dev
,
1347 set_device_error_reporting(dev
, &enable
);
1349 if (!dev
->subordinate
)
1351 pci_walk_bus(dev
->subordinate
, set_device_error_reporting
, &enable
);
1355 * aer_enable_rootport - enable Root Port's interrupts when receiving messages
1356 * @rpc: pointer to a Root Port data structure
1358 * Invoked when PCIe bus loads AER service driver.
1360 static void aer_enable_rootport(struct aer_rpc
*rpc
)
1362 struct pci_dev
*pdev
= rpc
->rpd
;
1367 /* Clear PCIe Capability's Device Status */
1368 pcie_capability_read_word(pdev
, PCI_EXP_DEVSTA
, ®16
);
1369 pcie_capability_write_word(pdev
, PCI_EXP_DEVSTA
, reg16
);
1371 /* Disable system error generation in response to error messages */
1372 pcie_capability_clear_word(pdev
, PCI_EXP_RTCTL
,
1373 SYSTEM_ERROR_INTR_ON_MESG_MASK
);
1375 aer_pos
= pdev
->aer_cap
;
1376 /* Clear error status */
1377 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_STATUS
, ®32
);
1378 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_STATUS
, reg32
);
1379 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_COR_STATUS
, ®32
);
1380 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_COR_STATUS
, reg32
);
1381 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_UNCOR_STATUS
, ®32
);
1382 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_UNCOR_STATUS
, reg32
);
1385 * Enable error reporting for the root port device and downstream port
1388 set_downstream_devices_error_reporting(pdev
, true);
1390 /* Enable Root Port's interrupt in response to error messages */
1391 pci_read_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1392 reg32
|= ROOT_PORT_INTR_ON_MESG_MASK
;
1393 pci_write_config_dword(pdev
, aer_pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1397 * aer_disable_rootport - disable Root Port's interrupts when receiving messages
1398 * @rpc: pointer to a Root Port data structure
1400 * Invoked when PCIe bus unloads AER service driver.
1402 static void aer_disable_rootport(struct aer_rpc
*rpc
)
1404 struct pci_dev
*pdev
= rpc
->rpd
;
1409 * Disable error reporting for the root port device and downstream port
1412 set_downstream_devices_error_reporting(pdev
, false);
1414 pos
= pdev
->aer_cap
;
1415 /* Disable Root's interrupt in response to error messages */
1416 pci_read_config_dword(pdev
, pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1417 reg32
&= ~ROOT_PORT_INTR_ON_MESG_MASK
;
1418 pci_write_config_dword(pdev
, pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1420 /* Clear Root's error status reg */
1421 pci_read_config_dword(pdev
, pos
+ PCI_ERR_ROOT_STATUS
, ®32
);
1422 pci_write_config_dword(pdev
, pos
+ PCI_ERR_ROOT_STATUS
, reg32
);
1426 * aer_alloc_rpc - allocate Root Port data structure
1427 * @dev: pointer to the pcie_dev data structure
1429 * Invoked when Root Port's AER service is loaded.
1431 static struct aer_rpc
*aer_alloc_rpc(struct pcie_device
*dev
)
1433 struct aer_rpc
*rpc
;
1435 rpc
= kzalloc(sizeof(struct aer_rpc
), GFP_KERNEL
);
1439 /* Initialize Root lock access, e_lock, to Root Error Status Reg */
1440 spin_lock_init(&rpc
->e_lock
);
1442 rpc
->rpd
= dev
->port
;
1443 INIT_WORK(&rpc
->dpc_handler
, aer_isr
);
1444 mutex_init(&rpc
->rpc_mutex
);
1446 /* Use PCIe bus function to store rpc into PCIe device */
1447 set_service_data(dev
, rpc
);
1453 * aer_remove - clean up resources
1454 * @dev: pointer to the pcie_dev data structure
1456 * Invoked when PCI Express bus unloads or AER probe fails.
1458 static void aer_remove(struct pcie_device
*dev
)
1460 struct aer_rpc
*rpc
= get_service_data(dev
);
1463 /* If register interrupt service, it must be free. */
1465 free_irq(dev
->irq
, dev
);
1467 flush_work(&rpc
->dpc_handler
);
1468 aer_disable_rootport(rpc
);
1470 set_service_data(dev
, NULL
);
1475 * aer_probe - initialize resources
1476 * @dev: pointer to the pcie_dev data structure
1478 * Invoked when PCI Express bus loads AER service driver.
1480 static int aer_probe(struct pcie_device
*dev
)
1483 struct aer_rpc
*rpc
;
1484 struct device
*device
= &dev
->port
->dev
;
1486 /* Alloc rpc data structure */
1487 rpc
= aer_alloc_rpc(dev
);
1489 dev_printk(KERN_DEBUG
, device
, "alloc AER rpc failed\n");
1494 /* Request IRQ ISR */
1495 status
= request_irq(dev
->irq
, aer_irq
, IRQF_SHARED
, "aerdrv", dev
);
1497 dev_printk(KERN_DEBUG
, device
, "request AER IRQ %d failed\n",
1505 aer_enable_rootport(rpc
);
1506 dev_info(device
, "AER enabled with IRQ %d\n", dev
->irq
);
1511 * aer_root_reset - reset link on Root Port
1512 * @dev: pointer to Root Port's pci_dev data structure
1514 * Invoked by Port Bus driver when performing link reset at Root Port.
1516 static pci_ers_result_t
aer_root_reset(struct pci_dev
*dev
)
1524 /* Disable Root's interrupt in response to error messages */
1525 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1526 reg32
&= ~ROOT_PORT_INTR_ON_MESG_MASK
;
1527 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1529 rc
= pci_bridge_secondary_bus_reset(dev
);
1530 pci_printk(KERN_DEBUG
, dev
, "Root Port link has been reset\n");
1532 /* Clear Root Error Status */
1533 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, ®32
);
1534 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_STATUS
, reg32
);
1536 /* Enable Root Port's interrupt in response to error messages */
1537 pci_read_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, ®32
);
1538 reg32
|= ROOT_PORT_INTR_ON_MESG_MASK
;
1539 pci_write_config_dword(dev
, pos
+ PCI_ERR_ROOT_COMMAND
, reg32
);
1541 return rc
? PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_RECOVERED
;
1545 * aer_error_resume - clean up corresponding error status bits
1546 * @dev: pointer to Root Port's pci_dev data structure
1548 * Invoked by Port Bus driver during nonfatal recovery.
1550 static void aer_error_resume(struct pci_dev
*dev
)
1552 pci_aer_clear_device_status(dev
);
1553 pci_cleanup_aer_uncorrect_error_status(dev
);
1556 static struct pcie_port_service_driver aerdriver
= {
1558 .port_type
= PCI_EXP_TYPE_ROOT_PORT
,
1559 .service
= PCIE_PORT_SERVICE_AER
,
1562 .remove
= aer_remove
,
1563 .error_resume
= aer_error_resume
,
1564 .reset_link
= aer_root_reset
,
1568 * aer_service_init - register AER root service driver
1570 * Invoked when AER root service driver is loaded.
1572 static int __init
aer_service_init(void)
1574 if (!pci_aer_available() || aer_acpi_firmware_first())
1576 return pcie_port_service_register(&aerdriver
);
1578 device_initcall(aer_service_init
);