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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / spi / spi-imx.c
blob08dd3a31a3e5f7d49a40400300f85477ef6a464e
1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 // Copyright (C) 2008 Juergen Beisert
4
5 #include <linux/clk.h>
6 #include <linux/completion.h>
7 #include <linux/delay.h>
8 #include <linux/dmaengine.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/err.h>
11 #include <linux/gpio.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/irq.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi_bitbang.h>
21 #include <linux/types.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/of_gpio.h>
25
26 #include <linux/platform_data/dma-imx.h>
27 #include <linux/platform_data/spi-imx.h>
28
29 #define DRIVER_NAME "spi_imx"
30
31 #define MXC_CSPIRXDATA 0x00
32 #define MXC_CSPITXDATA 0x04
33 #define MXC_CSPICTRL 0x08
34 #define MXC_CSPIINT 0x0c
35 #define MXC_RESET 0x1c
36
37 /* generic defines to abstract from the different register layouts */
38 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
39 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
40 #define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
41
42 /* The maximum bytes that a sdma BD can transfer.*/
43 #define MAX_SDMA_BD_BYTES (1 << 15)
44 #define MX51_ECSPI_CTRL_MAX_BURST 512
45 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
46 #define MX53_MAX_TRANSFER_BYTES 512
47
48 enum spi_imx_devtype {
49 IMX1_CSPI,
50 IMX21_CSPI,
51 IMX27_CSPI,
52 IMX31_CSPI,
53 IMX35_CSPI, /* CSPI on all i.mx except above */
54 IMX51_ECSPI, /* ECSPI on i.mx51 */
55 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
56 };
57
58 struct spi_imx_data;
59
60 struct spi_imx_devtype_data {
61 void (*intctrl)(struct spi_imx_data *, int);
62 int (*config)(struct spi_device *);
63 void (*trigger)(struct spi_imx_data *);
64 int (*rx_available)(struct spi_imx_data *);
65 void (*reset)(struct spi_imx_data *);
66 void (*disable)(struct spi_imx_data *);
67 bool has_dmamode;
68 bool has_slavemode;
69 unsigned int fifo_size;
70 bool dynamic_burst;
71 enum spi_imx_devtype devtype;
72 };
73
74 struct spi_imx_data {
75 struct spi_bitbang bitbang;
76 struct device *dev;
77
78 struct completion xfer_done;
79 void __iomem *base;
80 unsigned long base_phys;
81
82 struct clk *clk_per;
83 struct clk *clk_ipg;
84 unsigned long spi_clk;
85 unsigned int spi_bus_clk;
86
87 unsigned int speed_hz;
88 unsigned int bits_per_word;
89 unsigned int spi_drctl;
90
91 unsigned int count, remainder;
92 void (*tx)(struct spi_imx_data *);
93 void (*rx)(struct spi_imx_data *);
94 void *rx_buf;
95 const void *tx_buf;
96 unsigned int txfifo; /* number of words pushed in tx FIFO */
97 unsigned int dynamic_burst;
98
99 /* Slave mode */
100 bool slave_mode;
101 bool slave_aborted;
102 unsigned int slave_burst;
103
104 /* DMA */
105 bool usedma;
106 u32 wml;
107 struct completion dma_rx_completion;
108 struct completion dma_tx_completion;
109
110 const struct spi_imx_devtype_data *devtype_data;
111 };
112
113 static inline int is_imx27_cspi(struct spi_imx_data *d)
114 {
115 return d->devtype_data->devtype == IMX27_CSPI;
116 }
117
118 static inline int is_imx35_cspi(struct spi_imx_data *d)
119 {
120 return d->devtype_data->devtype == IMX35_CSPI;
121 }
122
123 static inline int is_imx51_ecspi(struct spi_imx_data *d)
124 {
125 return d->devtype_data->devtype == IMX51_ECSPI;
126 }
127
128 static inline int is_imx53_ecspi(struct spi_imx_data *d)
129 {
130 return d->devtype_data->devtype == IMX53_ECSPI;
131 }
132
133 #define MXC_SPI_BUF_RX(type) \
134 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
135 { \
136 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
137 \
138 if (spi_imx->rx_buf) { \
139 *(type *)spi_imx->rx_buf = val; \
140 spi_imx->rx_buf += sizeof(type); \
141 } \
142 \
143 spi_imx->remainder -= sizeof(type); \
144 }
145
146 #define MXC_SPI_BUF_TX(type) \
147 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
148 { \
149 type val = 0; \
150 \
151 if (spi_imx->tx_buf) { \
152 val = *(type *)spi_imx->tx_buf; \
153 spi_imx->tx_buf += sizeof(type); \
154 } \
155 \
156 spi_imx->count -= sizeof(type); \
157 \
158 writel(val, spi_imx->base + MXC_CSPITXDATA); \
159 }
160
161 MXC_SPI_BUF_RX(u8)
162 MXC_SPI_BUF_TX(u8)
163 MXC_SPI_BUF_RX(u16)
164 MXC_SPI_BUF_TX(u16)
165 MXC_SPI_BUF_RX(u32)
166 MXC_SPI_BUF_TX(u32)
167
168 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
169 * (which is currently not the case in this driver)
170 */
171 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
172 256, 384, 512, 768, 1024};
173
174 /* MX21, MX27 */
175 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
176 unsigned int fspi, unsigned int max, unsigned int *fres)
177 {
178 int i;
179
180 for (i = 2; i < max; i++)
181 if (fspi * mxc_clkdivs[i] >= fin)
182 break;
183
184 *fres = fin / mxc_clkdivs[i];
185 return i;
186 }
187
188 /* MX1, MX31, MX35, MX51 CSPI */
189 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
190 unsigned int fspi, unsigned int *fres)
191 {
192 int i, div = 4;
193
194 for (i = 0; i < 7; i++) {
195 if (fspi * div >= fin)
196 goto out;
197 div <<= 1;
198 }
199
200 out:
201 *fres = fin / div;
202 return i;
203 }
204
205 static int spi_imx_bytes_per_word(const int bits_per_word)
206 {
207 if (bits_per_word <= 8)
208 return 1;
209 else if (bits_per_word <= 16)
210 return 2;
211 else
212 return 4;
213 }
214
215 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
216 struct spi_transfer *transfer)
217 {
218 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
219 unsigned int bytes_per_word, i;
220
221 if (!master->dma_rx)
222 return false;
223
224 if (spi_imx->slave_mode)
225 return false;
226
227 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
228
229 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
230 if (!(transfer->len % (i * bytes_per_word)))
231 break;
232 }
233
234 spi_imx->wml = i;
235 spi_imx->dynamic_burst = 0;
236
237 return true;
238 }
239
240 #define MX51_ECSPI_CTRL 0x08
241 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
242 #define MX51_ECSPI_CTRL_XCH (1 << 2)
243 #define MX51_ECSPI_CTRL_SMC (1 << 3)
244 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
245 #define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
246 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
247 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
248 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
249 #define MX51_ECSPI_CTRL_BL_OFFSET 20
250 #define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
251
252 #define MX51_ECSPI_CONFIG 0x0c
253 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
254 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
255 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
256 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
257 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
258
259 #define MX51_ECSPI_INT 0x10
260 #define MX51_ECSPI_INT_TEEN (1 << 0)
261 #define MX51_ECSPI_INT_RREN (1 << 3)
262 #define MX51_ECSPI_INT_RDREN (1 << 4)
263
264 #define MX51_ECSPI_DMA 0x14
265 #define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
266 #define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
267 #define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
268
269 #define MX51_ECSPI_DMA_TEDEN (1 << 7)
270 #define MX51_ECSPI_DMA_RXDEN (1 << 23)
271 #define MX51_ECSPI_DMA_RXTDEN (1 << 31)
272
273 #define MX51_ECSPI_STAT 0x18
274 #define MX51_ECSPI_STAT_RR (1 << 3)
275
276 #define MX51_ECSPI_TESTREG 0x20
277 #define MX51_ECSPI_TESTREG_LBC BIT(31)
278
279 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
280 {
281 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
282 #ifdef __LITTLE_ENDIAN
283 unsigned int bytes_per_word;
284 #endif
285
286 if (spi_imx->rx_buf) {
287 #ifdef __LITTLE_ENDIAN
288 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
289 if (bytes_per_word == 1)
290 val = cpu_to_be32(val);
291 else if (bytes_per_word == 2)
292 val = (val << 16) | (val >> 16);
293 #endif
294 *(u32 *)spi_imx->rx_buf = val;
295 spi_imx->rx_buf += sizeof(u32);
296 }
297
298 spi_imx->remainder -= sizeof(u32);
299 }
300
301 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
302 {
303 int unaligned;
304 u32 val;
305
306 unaligned = spi_imx->remainder % 4;
307
308 if (!unaligned) {
309 spi_imx_buf_rx_swap_u32(spi_imx);
310 return;
311 }
312
313 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
314 spi_imx_buf_rx_u16(spi_imx);
315 return;
316 }
317
318 val = readl(spi_imx->base + MXC_CSPIRXDATA);
319
320 while (unaligned--) {
321 if (spi_imx->rx_buf) {
322 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
323 spi_imx->rx_buf++;
324 }
325 spi_imx->remainder--;
326 }
327 }
328
329 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
330 {
331 u32 val = 0;
332 #ifdef __LITTLE_ENDIAN
333 unsigned int bytes_per_word;
334 #endif
335
336 if (spi_imx->tx_buf) {
337 val = *(u32 *)spi_imx->tx_buf;
338 spi_imx->tx_buf += sizeof(u32);
339 }
340
341 spi_imx->count -= sizeof(u32);
342 #ifdef __LITTLE_ENDIAN
343 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
344
345 if (bytes_per_word == 1)
346 val = cpu_to_be32(val);
347 else if (bytes_per_word == 2)
348 val = (val << 16) | (val >> 16);
349 #endif
350 writel(val, spi_imx->base + MXC_CSPITXDATA);
351 }
352
353 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
354 {
355 int unaligned;
356 u32 val = 0;
357
358 unaligned = spi_imx->count % 4;
359
360 if (!unaligned) {
361 spi_imx_buf_tx_swap_u32(spi_imx);
362 return;
363 }
364
365 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
366 spi_imx_buf_tx_u16(spi_imx);
367 return;
368 }
369
370 while (unaligned--) {
371 if (spi_imx->tx_buf) {
372 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
373 spi_imx->tx_buf++;
374 }
375 spi_imx->count--;
376 }
377
378 writel(val, spi_imx->base + MXC_CSPITXDATA);
379 }
380
381 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
382 {
383 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
384
385 if (spi_imx->rx_buf) {
386 int n_bytes = spi_imx->slave_burst % sizeof(val);
387
388 if (!n_bytes)
389 n_bytes = sizeof(val);
390
391 memcpy(spi_imx->rx_buf,
392 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
393
394 spi_imx->rx_buf += n_bytes;
395 spi_imx->slave_burst -= n_bytes;
396 }
397
398 spi_imx->remainder -= sizeof(u32);
399 }
400
401 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
402 {
403 u32 val = 0;
404 int n_bytes = spi_imx->count % sizeof(val);
405
406 if (!n_bytes)
407 n_bytes = sizeof(val);
408
409 if (spi_imx->tx_buf) {
410 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
411 spi_imx->tx_buf, n_bytes);
412 val = cpu_to_be32(val);
413 spi_imx->tx_buf += n_bytes;
414 }
415
416 spi_imx->count -= n_bytes;
417
418 writel(val, spi_imx->base + MXC_CSPITXDATA);
419 }
420
421 /* MX51 eCSPI */
422 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
423 unsigned int fspi, unsigned int *fres)
424 {
425 /*
426 * there are two 4-bit dividers, the pre-divider divides by
427 * $pre, the post-divider by 2^$post
428 */
429 unsigned int pre, post;
430 unsigned int fin = spi_imx->spi_clk;
431
432 if (unlikely(fspi > fin))
433 return 0;
434
435 post = fls(fin) - fls(fspi);
436 if (fin > fspi << post)
437 post++;
438
439 /* now we have: (fin <= fspi << post) with post being minimal */
440
441 post = max(4U, post) - 4;
442 if (unlikely(post > 0xf)) {
443 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
444 fspi, fin);
445 return 0xff;
446 }
447
448 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
449
450 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
451 __func__, fin, fspi, post, pre);
452
453 /* Resulting frequency for the SCLK line. */
454 *fres = (fin / (pre + 1)) >> post;
455
456 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
457 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
458 }
459
460 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
461 {
462 unsigned val = 0;
463
464 if (enable & MXC_INT_TE)
465 val |= MX51_ECSPI_INT_TEEN;
466
467 if (enable & MXC_INT_RR)
468 val |= MX51_ECSPI_INT_RREN;
469
470 if (enable & MXC_INT_RDR)
471 val |= MX51_ECSPI_INT_RDREN;
472
473 writel(val, spi_imx->base + MX51_ECSPI_INT);
474 }
475
476 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
477 {
478 u32 reg;
479
480 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
481 reg |= MX51_ECSPI_CTRL_XCH;
482 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
483 }
484
485 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
486 {
487 u32 ctrl;
488
489 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
490 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
491 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
492 }
493
494 static int mx51_ecspi_config(struct spi_device *spi)
495 {
496 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
497 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
498 u32 clk = spi_imx->speed_hz, delay, reg;
499 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
500
501 /* set Master or Slave mode */
502 if (spi_imx->slave_mode)
503 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
504 else
505 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
506
507 /*
508 * Enable SPI_RDY handling (falling edge/level triggered).
509 */
510 if (spi->mode & SPI_READY)
511 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
512
513 /* set clock speed */
514 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
515 spi_imx->spi_bus_clk = clk;
516
517 /* set chip select to use */
518 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
519
520 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
521 ctrl |= (spi_imx->slave_burst * 8 - 1)
522 << MX51_ECSPI_CTRL_BL_OFFSET;
523 else
524 ctrl |= (spi_imx->bits_per_word - 1)
525 << MX51_ECSPI_CTRL_BL_OFFSET;
526
527 /*
528 * eCSPI burst completion by Chip Select signal in Slave mode
529 * is not functional for imx53 Soc, config SPI burst completed when
530 * BURST_LENGTH + 1 bits are received
531 */
532 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
533 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
534 else
535 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
536
537 if (spi->mode & SPI_CPHA)
538 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
539 else
540 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
541
542 if (spi->mode & SPI_CPOL) {
543 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
544 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
545 } else {
546 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
547 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
548 }
549 if (spi->mode & SPI_CS_HIGH)
550 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
551 else
552 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
553
554 if (spi_imx->usedma)
555 ctrl |= MX51_ECSPI_CTRL_SMC;
556
557 /* CTRL register always go first to bring out controller from reset */
558 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
559
560 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
561 if (spi->mode & SPI_LOOP)
562 reg |= MX51_ECSPI_TESTREG_LBC;
563 else
564 reg &= ~MX51_ECSPI_TESTREG_LBC;
565 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
566
567 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
568
569 /*
570 * Wait until the changes in the configuration register CONFIGREG
571 * propagate into the hardware. It takes exactly one tick of the
572 * SCLK clock, but we will wait two SCLK clock just to be sure. The
573 * effect of the delay it takes for the hardware to apply changes
574 * is noticable if the SCLK clock run very slow. In such a case, if
575 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
576 * be asserted before the SCLK polarity changes, which would disrupt
577 * the SPI communication as the device on the other end would consider
578 * the change of SCLK polarity as a clock tick already.
579 */
580 delay = (2 * 1000000) / clk;
581 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
582 udelay(delay);
583 else /* SCLK is _very_ slow */
584 usleep_range(delay, delay + 10);
585
586 /*
587 * Configure the DMA register: setup the watermark
588 * and enable DMA request.
589 */
590
591 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
592 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
593 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
594 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
595 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
596
597 return 0;
598 }
599
600 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
601 {
602 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
603 }
604
605 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
606 {
607 /* drain receive buffer */
608 while (mx51_ecspi_rx_available(spi_imx))
609 readl(spi_imx->base + MXC_CSPIRXDATA);
610 }
611
612 #define MX31_INTREG_TEEN (1 << 0)
613 #define MX31_INTREG_RREN (1 << 3)
614
615 #define MX31_CSPICTRL_ENABLE (1 << 0)
616 #define MX31_CSPICTRL_MASTER (1 << 1)
617 #define MX31_CSPICTRL_XCH (1 << 2)
618 #define MX31_CSPICTRL_SMC (1 << 3)
619 #define MX31_CSPICTRL_POL (1 << 4)
620 #define MX31_CSPICTRL_PHA (1 << 5)
621 #define MX31_CSPICTRL_SSCTL (1 << 6)
622 #define MX31_CSPICTRL_SSPOL (1 << 7)
623 #define MX31_CSPICTRL_BC_SHIFT 8
624 #define MX35_CSPICTRL_BL_SHIFT 20
625 #define MX31_CSPICTRL_CS_SHIFT 24
626 #define MX35_CSPICTRL_CS_SHIFT 12
627 #define MX31_CSPICTRL_DR_SHIFT 16
628
629 #define MX31_CSPI_DMAREG 0x10
630 #define MX31_DMAREG_RH_DEN (1<<4)
631 #define MX31_DMAREG_TH_DEN (1<<1)
632
633 #define MX31_CSPISTATUS 0x14
634 #define MX31_STATUS_RR (1 << 3)
635
636 #define MX31_CSPI_TESTREG 0x1C
637 #define MX31_TEST_LBC (1 << 14)
638
639 /* These functions also work for the i.MX35, but be aware that
640 * the i.MX35 has a slightly different register layout for bits
641 * we do not use here.
642 */
643 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
644 {
645 unsigned int val = 0;
646
647 if (enable & MXC_INT_TE)
648 val |= MX31_INTREG_TEEN;
649 if (enable & MXC_INT_RR)
650 val |= MX31_INTREG_RREN;
651
652 writel(val, spi_imx->base + MXC_CSPIINT);
653 }
654
655 static void mx31_trigger(struct spi_imx_data *spi_imx)
656 {
657 unsigned int reg;
658
659 reg = readl(spi_imx->base + MXC_CSPICTRL);
660 reg |= MX31_CSPICTRL_XCH;
661 writel(reg, spi_imx->base + MXC_CSPICTRL);
662 }
663
664 static int mx31_config(struct spi_device *spi)
665 {
666 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
667 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
668 unsigned int clk;
669
670 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
671 MX31_CSPICTRL_DR_SHIFT;
672 spi_imx->spi_bus_clk = clk;
673
674 if (is_imx35_cspi(spi_imx)) {
675 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
676 reg |= MX31_CSPICTRL_SSCTL;
677 } else {
678 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
679 }
680
681 if (spi->mode & SPI_CPHA)
682 reg |= MX31_CSPICTRL_PHA;
683 if (spi->mode & SPI_CPOL)
684 reg |= MX31_CSPICTRL_POL;
685 if (spi->mode & SPI_CS_HIGH)
686 reg |= MX31_CSPICTRL_SSPOL;
687 if (!gpio_is_valid(spi->cs_gpio))
688 reg |= (spi->chip_select) <<
689 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
690 MX31_CSPICTRL_CS_SHIFT);
691
692 if (spi_imx->usedma)
693 reg |= MX31_CSPICTRL_SMC;
694
695 writel(reg, spi_imx->base + MXC_CSPICTRL);
696
697 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
698 if (spi->mode & SPI_LOOP)
699 reg |= MX31_TEST_LBC;
700 else
701 reg &= ~MX31_TEST_LBC;
702 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
703
704 if (spi_imx->usedma) {
705 /* configure DMA requests when RXFIFO is half full and
706 when TXFIFO is half empty */
707 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
708 spi_imx->base + MX31_CSPI_DMAREG);
709 }
710
711 return 0;
712 }
713
714 static int mx31_rx_available(struct spi_imx_data *spi_imx)
715 {
716 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
717 }
718
719 static void mx31_reset(struct spi_imx_data *spi_imx)
720 {
721 /* drain receive buffer */
722 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
723 readl(spi_imx->base + MXC_CSPIRXDATA);
724 }
725
726 #define MX21_INTREG_RR (1 << 4)
727 #define MX21_INTREG_TEEN (1 << 9)
728 #define MX21_INTREG_RREN (1 << 13)
729
730 #define MX21_CSPICTRL_POL (1 << 5)
731 #define MX21_CSPICTRL_PHA (1 << 6)
732 #define MX21_CSPICTRL_SSPOL (1 << 8)
733 #define MX21_CSPICTRL_XCH (1 << 9)
734 #define MX21_CSPICTRL_ENABLE (1 << 10)
735 #define MX21_CSPICTRL_MASTER (1 << 11)
736 #define MX21_CSPICTRL_DR_SHIFT 14
737 #define MX21_CSPICTRL_CS_SHIFT 19
738
739 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
740 {
741 unsigned int val = 0;
742
743 if (enable & MXC_INT_TE)
744 val |= MX21_INTREG_TEEN;
745 if (enable & MXC_INT_RR)
746 val |= MX21_INTREG_RREN;
747
748 writel(val, spi_imx->base + MXC_CSPIINT);
749 }
750
751 static void mx21_trigger(struct spi_imx_data *spi_imx)
752 {
753 unsigned int reg;
754
755 reg = readl(spi_imx->base + MXC_CSPICTRL);
756 reg |= MX21_CSPICTRL_XCH;
757 writel(reg, spi_imx->base + MXC_CSPICTRL);
758 }
759
760 static int mx21_config(struct spi_device *spi)
761 {
762 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
763 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
764 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
765 unsigned int clk;
766
767 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
768 << MX21_CSPICTRL_DR_SHIFT;
769 spi_imx->spi_bus_clk = clk;
770
771 reg |= spi_imx->bits_per_word - 1;
772
773 if (spi->mode & SPI_CPHA)
774 reg |= MX21_CSPICTRL_PHA;
775 if (spi->mode & SPI_CPOL)
776 reg |= MX21_CSPICTRL_POL;
777 if (spi->mode & SPI_CS_HIGH)
778 reg |= MX21_CSPICTRL_SSPOL;
779 if (!gpio_is_valid(spi->cs_gpio))
780 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
781
782 writel(reg, spi_imx->base + MXC_CSPICTRL);
783
784 return 0;
785 }
786
787 static int mx21_rx_available(struct spi_imx_data *spi_imx)
788 {
789 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
790 }
791
792 static void mx21_reset(struct spi_imx_data *spi_imx)
793 {
794 writel(1, spi_imx->base + MXC_RESET);
795 }
796
797 #define MX1_INTREG_RR (1 << 3)
798 #define MX1_INTREG_TEEN (1 << 8)
799 #define MX1_INTREG_RREN (1 << 11)
800
801 #define MX1_CSPICTRL_POL (1 << 4)
802 #define MX1_CSPICTRL_PHA (1 << 5)
803 #define MX1_CSPICTRL_XCH (1 << 8)
804 #define MX1_CSPICTRL_ENABLE (1 << 9)
805 #define MX1_CSPICTRL_MASTER (1 << 10)
806 #define MX1_CSPICTRL_DR_SHIFT 13
807
808 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
809 {
810 unsigned int val = 0;
811
812 if (enable & MXC_INT_TE)
813 val |= MX1_INTREG_TEEN;
814 if (enable & MXC_INT_RR)
815 val |= MX1_INTREG_RREN;
816
817 writel(val, spi_imx->base + MXC_CSPIINT);
818 }
819
820 static void mx1_trigger(struct spi_imx_data *spi_imx)
821 {
822 unsigned int reg;
823
824 reg = readl(spi_imx->base + MXC_CSPICTRL);
825 reg |= MX1_CSPICTRL_XCH;
826 writel(reg, spi_imx->base + MXC_CSPICTRL);
827 }
828
829 static int mx1_config(struct spi_device *spi)
830 {
831 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
832 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
833 unsigned int clk;
834
835 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
836 MX1_CSPICTRL_DR_SHIFT;
837 spi_imx->spi_bus_clk = clk;
838
839 reg |= spi_imx->bits_per_word - 1;
840
841 if (spi->mode & SPI_CPHA)
842 reg |= MX1_CSPICTRL_PHA;
843 if (spi->mode & SPI_CPOL)
844 reg |= MX1_CSPICTRL_POL;
845
846 writel(reg, spi_imx->base + MXC_CSPICTRL);
847
848 return 0;
849 }
850
851 static int mx1_rx_available(struct spi_imx_data *spi_imx)
852 {
853 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
854 }
855
856 static void mx1_reset(struct spi_imx_data *spi_imx)
857 {
858 writel(1, spi_imx->base + MXC_RESET);
859 }
860
861 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
862 .intctrl = mx1_intctrl,
863 .config = mx1_config,
864 .trigger = mx1_trigger,
865 .rx_available = mx1_rx_available,
866 .reset = mx1_reset,
867 .fifo_size = 8,
868 .has_dmamode = false,
869 .dynamic_burst = false,
870 .has_slavemode = false,
871 .devtype = IMX1_CSPI,
872 };
873
874 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
875 .intctrl = mx21_intctrl,
876 .config = mx21_config,
877 .trigger = mx21_trigger,
878 .rx_available = mx21_rx_available,
879 .reset = mx21_reset,
880 .fifo_size = 8,
881 .has_dmamode = false,
882 .dynamic_burst = false,
883 .has_slavemode = false,
884 .devtype = IMX21_CSPI,
885 };
886
887 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
888 /* i.mx27 cspi shares the functions with i.mx21 one */
889 .intctrl = mx21_intctrl,
890 .config = mx21_config,
891 .trigger = mx21_trigger,
892 .rx_available = mx21_rx_available,
893 .reset = mx21_reset,
894 .fifo_size = 8,
895 .has_dmamode = false,
896 .dynamic_burst = false,
897 .has_slavemode = false,
898 .devtype = IMX27_CSPI,
899 };
900
901 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
902 .intctrl = mx31_intctrl,
903 .config = mx31_config,
904 .trigger = mx31_trigger,
905 .rx_available = mx31_rx_available,
906 .reset = mx31_reset,
907 .fifo_size = 8,
908 .has_dmamode = false,
909 .dynamic_burst = false,
910 .has_slavemode = false,
911 .devtype = IMX31_CSPI,
912 };
913
914 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
915 /* i.mx35 and later cspi shares the functions with i.mx31 one */
916 .intctrl = mx31_intctrl,
917 .config = mx31_config,
918 .trigger = mx31_trigger,
919 .rx_available = mx31_rx_available,
920 .reset = mx31_reset,
921 .fifo_size = 8,
922 .has_dmamode = true,
923 .dynamic_burst = false,
924 .has_slavemode = false,
925 .devtype = IMX35_CSPI,
926 };
927
928 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
929 .intctrl = mx51_ecspi_intctrl,
930 .config = mx51_ecspi_config,
931 .trigger = mx51_ecspi_trigger,
932 .rx_available = mx51_ecspi_rx_available,
933 .reset = mx51_ecspi_reset,
934 .fifo_size = 64,
935 .has_dmamode = true,
936 .dynamic_burst = true,
937 .has_slavemode = true,
938 .disable = mx51_ecspi_disable,
939 .devtype = IMX51_ECSPI,
940 };
941
942 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
943 .intctrl = mx51_ecspi_intctrl,
944 .config = mx51_ecspi_config,
945 .trigger = mx51_ecspi_trigger,
946 .rx_available = mx51_ecspi_rx_available,
947 .reset = mx51_ecspi_reset,
948 .fifo_size = 64,
949 .has_dmamode = true,
950 .has_slavemode = true,
951 .disable = mx51_ecspi_disable,
952 .devtype = IMX53_ECSPI,
953 };
954
955 static const struct platform_device_id spi_imx_devtype[] = {
956 {
957 .name = "imx1-cspi",
958 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
959 }, {
960 .name = "imx21-cspi",
961 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
962 }, {
963 .name = "imx27-cspi",
964 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
965 }, {
966 .name = "imx31-cspi",
967 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
968 }, {
969 .name = "imx35-cspi",
970 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
971 }, {
972 .name = "imx51-ecspi",
973 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
974 }, {
975 .name = "imx53-ecspi",
976 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
977 }, {
978 /* sentinel */
979 }
980 };
981
982 static const struct of_device_id spi_imx_dt_ids[] = {
983 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
984 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
985 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
986 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
987 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
988 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
989 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
990 { /* sentinel */ }
991 };
992 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
993
994 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
995 {
996 int active = is_active != BITBANG_CS_INACTIVE;
997 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
998
999 if (spi->mode & SPI_NO_CS)
1000 return;
1001
1002 if (!gpio_is_valid(spi->cs_gpio))
1003 return;
1004
1005 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1006 }
1007
1008 static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1009 {
1010 u32 ctrl;
1011
1012 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1013 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1014 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1015 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1016 }
1017
1018 static void spi_imx_push(struct spi_imx_data *spi_imx)
1019 {
1020 unsigned int burst_len, fifo_words;
1021
1022 if (spi_imx->dynamic_burst)
1023 fifo_words = 4;
1024 else
1025 fifo_words = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1026 /*
1027 * Reload the FIFO when the remaining bytes to be transferred in the
1028 * current burst is 0. This only applies when bits_per_word is a
1029 * multiple of 8.
1030 */
1031 if (!spi_imx->remainder) {
1032 if (spi_imx->dynamic_burst) {
1033
1034 /* We need to deal unaligned data first */
1035 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1036
1037 if (!burst_len)
1038 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1039
1040 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1041
1042 spi_imx->remainder = burst_len;
1043 } else {
1044 spi_imx->remainder = fifo_words;
1045 }
1046 }
1047
1048 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1049 if (!spi_imx->count)
1050 break;
1051 if (spi_imx->dynamic_burst &&
1052 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder,
1053 fifo_words))
1054 break;
1055 spi_imx->tx(spi_imx);
1056 spi_imx->txfifo++;
1057 }
1058
1059 if (!spi_imx->slave_mode)
1060 spi_imx->devtype_data->trigger(spi_imx);
1061 }
1062
1063 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1064 {
1065 struct spi_imx_data *spi_imx = dev_id;
1066
1067 while (spi_imx->txfifo &&
1068 spi_imx->devtype_data->rx_available(spi_imx)) {
1069 spi_imx->rx(spi_imx);
1070 spi_imx->txfifo--;
1071 }
1072
1073 if (spi_imx->count) {
1074 spi_imx_push(spi_imx);
1075 return IRQ_HANDLED;
1076 }
1077
1078 if (spi_imx->txfifo) {
1079 /* No data left to push, but still waiting for rx data,
1080 * enable receive data available interrupt.
1081 */
1082 spi_imx->devtype_data->intctrl(
1083 spi_imx, MXC_INT_RR);
1084 return IRQ_HANDLED;
1085 }
1086
1087 spi_imx->devtype_data->intctrl(spi_imx, 0);
1088 complete(&spi_imx->xfer_done);
1089
1090 return IRQ_HANDLED;
1091 }
1092
1093 static int spi_imx_dma_configure(struct spi_master *master)
1094 {
1095 int ret;
1096 enum dma_slave_buswidth buswidth;
1097 struct dma_slave_config rx = {}, tx = {};
1098 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1099
1100 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1101 case 4:
1102 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1103 break;
1104 case 2:
1105 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1106 break;
1107 case 1:
1108 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1109 break;
1110 default:
1111 return -EINVAL;
1112 }
1113
1114 tx.direction = DMA_MEM_TO_DEV;
1115 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1116 tx.dst_addr_width = buswidth;
1117 tx.dst_maxburst = spi_imx->wml;
1118 ret = dmaengine_slave_config(master->dma_tx, &tx);
1119 if (ret) {
1120 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1121 return ret;
1122 }
1123
1124 rx.direction = DMA_DEV_TO_MEM;
1125 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1126 rx.src_addr_width = buswidth;
1127 rx.src_maxburst = spi_imx->wml;
1128 ret = dmaengine_slave_config(master->dma_rx, &rx);
1129 if (ret) {
1130 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1131 return ret;
1132 }
1133
1134 return 0;
1135 }
1136
1137 static int spi_imx_setupxfer(struct spi_device *spi,
1138 struct spi_transfer *t)
1139 {
1140 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1141 int ret;
1142
1143 if (!t)
1144 return 0;
1145
1146 spi_imx->bits_per_word = t->bits_per_word;
1147 spi_imx->speed_hz = t->speed_hz;
1148
1149 /*
1150 * Initialize the functions for transfer. To transfer non byte-aligned
1151 * words, we have to use multiple word-size bursts, we can't use
1152 * dynamic_burst in that case.
1153 */
1154 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode &&
1155 (spi_imx->bits_per_word == 8 ||
1156 spi_imx->bits_per_word == 16 ||
1157 spi_imx->bits_per_word == 32)) {
1158
1159 spi_imx->rx = spi_imx_buf_rx_swap;
1160 spi_imx->tx = spi_imx_buf_tx_swap;
1161 spi_imx->dynamic_burst = 1;
1162
1163 } else {
1164 if (spi_imx->bits_per_word <= 8) {
1165 spi_imx->rx = spi_imx_buf_rx_u8;
1166 spi_imx->tx = spi_imx_buf_tx_u8;
1167 } else if (spi_imx->bits_per_word <= 16) {
1168 spi_imx->rx = spi_imx_buf_rx_u16;
1169 spi_imx->tx = spi_imx_buf_tx_u16;
1170 } else {
1171 spi_imx->rx = spi_imx_buf_rx_u32;
1172 spi_imx->tx = spi_imx_buf_tx_u32;
1173 }
1174 spi_imx->dynamic_burst = 0;
1175 }
1176
1177 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1178 spi_imx->usedma = 1;
1179 else
1180 spi_imx->usedma = 0;
1181
1182 if (spi_imx->usedma) {
1183 ret = spi_imx_dma_configure(spi->master);
1184 if (ret)
1185 return ret;
1186 }
1187
1188 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1189 spi_imx->rx = mx53_ecspi_rx_slave;
1190 spi_imx->tx = mx53_ecspi_tx_slave;
1191 spi_imx->slave_burst = t->len;
1192 }
1193
1194 spi_imx->devtype_data->config(spi);
1195
1196 return 0;
1197 }
1198
1199 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1200 {
1201 struct spi_master *master = spi_imx->bitbang.master;
1202
1203 if (master->dma_rx) {
1204 dma_release_channel(master->dma_rx);
1205 master->dma_rx = NULL;
1206 }
1207
1208 if (master->dma_tx) {
1209 dma_release_channel(master->dma_tx);
1210 master->dma_tx = NULL;
1211 }
1212 }
1213
1214 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1215 struct spi_master *master)
1216 {
1217 int ret;
1218
1219 /* use pio mode for i.mx6dl chip TKT238285 */
1220 if (of_machine_is_compatible("fsl,imx6dl"))
1221 return 0;
1222
1223 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1224
1225 /* Prepare for TX DMA: */
1226 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1227 if (IS_ERR(master->dma_tx)) {
1228 ret = PTR_ERR(master->dma_tx);
1229 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1230 master->dma_tx = NULL;
1231 goto err;
1232 }
1233
1234 /* Prepare for RX : */
1235 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1236 if (IS_ERR(master->dma_rx)) {
1237 ret = PTR_ERR(master->dma_rx);
1238 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1239 master->dma_rx = NULL;
1240 goto err;
1241 }
1242
1243 init_completion(&spi_imx->dma_rx_completion);
1244 init_completion(&spi_imx->dma_tx_completion);
1245 master->can_dma = spi_imx_can_dma;
1246 master->max_dma_len = MAX_SDMA_BD_BYTES;
1247 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1248 SPI_MASTER_MUST_TX;
1249
1250 return 0;
1251 err:
1252 spi_imx_sdma_exit(spi_imx);
1253 return ret;
1254 }
1255
1256 static void spi_imx_dma_rx_callback(void *cookie)
1257 {
1258 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1259
1260 complete(&spi_imx->dma_rx_completion);
1261 }
1262
1263 static void spi_imx_dma_tx_callback(void *cookie)
1264 {
1265 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1266
1267 complete(&spi_imx->dma_tx_completion);
1268 }
1269
1270 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1271 {
1272 unsigned long timeout = 0;
1273
1274 /* Time with actual data transfer and CS change delay related to HW */
1275 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1276
1277 /* Add extra second for scheduler related activities */
1278 timeout += 1;
1279
1280 /* Double calculated timeout */
1281 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1282 }
1283
1284 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1285 struct spi_transfer *transfer)
1286 {
1287 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1288 unsigned long transfer_timeout;
1289 unsigned long timeout;
1290 struct spi_master *master = spi_imx->bitbang.master;
1291 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1292
1293 /*
1294 * The TX DMA setup starts the transfer, so make sure RX is configured
1295 * before TX.
1296 */
1297 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1298 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1299 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1300 if (!desc_rx)
1301 return -EINVAL;
1302
1303 desc_rx->callback = spi_imx_dma_rx_callback;
1304 desc_rx->callback_param = (void *)spi_imx;
1305 dmaengine_submit(desc_rx);
1306 reinit_completion(&spi_imx->dma_rx_completion);
1307 dma_async_issue_pending(master->dma_rx);
1308
1309 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1310 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1311 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1312 if (!desc_tx) {
1313 dmaengine_terminate_all(master->dma_tx);
1314 return -EINVAL;
1315 }
1316
1317 desc_tx->callback = spi_imx_dma_tx_callback;
1318 desc_tx->callback_param = (void *)spi_imx;
1319 dmaengine_submit(desc_tx);
1320 reinit_completion(&spi_imx->dma_tx_completion);
1321 dma_async_issue_pending(master->dma_tx);
1322
1323 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1324
1325 /* Wait SDMA to finish the data transfer.*/
1326 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1327 transfer_timeout);
1328 if (!timeout) {
1329 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1330 dmaengine_terminate_all(master->dma_tx);
1331 dmaengine_terminate_all(master->dma_rx);
1332 return -ETIMEDOUT;
1333 }
1334
1335 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1336 transfer_timeout);
1337 if (!timeout) {
1338 dev_err(&master->dev, "I/O Error in DMA RX\n");
1339 spi_imx->devtype_data->reset(spi_imx);
1340 dmaengine_terminate_all(master->dma_rx);
1341 return -ETIMEDOUT;
1342 }
1343
1344 return transfer->len;
1345 }
1346
1347 static int spi_imx_pio_transfer(struct spi_device *spi,
1348 struct spi_transfer *transfer)
1349 {
1350 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1351 unsigned long transfer_timeout;
1352 unsigned long timeout;
1353
1354 spi_imx->tx_buf = transfer->tx_buf;
1355 spi_imx->rx_buf = transfer->rx_buf;
1356 spi_imx->count = transfer->len;
1357 spi_imx->txfifo = 0;
1358 spi_imx->remainder = 0;
1359
1360 reinit_completion(&spi_imx->xfer_done);
1361
1362 spi_imx_push(spi_imx);
1363
1364 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1365
1366 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1367
1368 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1369 transfer_timeout);
1370 if (!timeout) {
1371 dev_err(&spi->dev, "I/O Error in PIO\n");
1372 spi_imx->devtype_data->reset(spi_imx);
1373 return -ETIMEDOUT;
1374 }
1375
1376 return transfer->len;
1377 }
1378
1379 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1380 struct spi_transfer *transfer)
1381 {
1382 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1383 int ret = transfer->len;
1384
1385 if (is_imx53_ecspi(spi_imx) &&
1386 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1387 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1388 MX53_MAX_TRANSFER_BYTES);
1389 return -EMSGSIZE;
1390 }
1391
1392 spi_imx->tx_buf = transfer->tx_buf;
1393 spi_imx->rx_buf = transfer->rx_buf;
1394 spi_imx->count = transfer->len;
1395 spi_imx->txfifo = 0;
1396 spi_imx->remainder = 0;
1397
1398 reinit_completion(&spi_imx->xfer_done);
1399 spi_imx->slave_aborted = false;
1400
1401 spi_imx_push(spi_imx);
1402
1403 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1404
1405 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1406 spi_imx->slave_aborted) {
1407 dev_dbg(&spi->dev, "interrupted\n");
1408 ret = -EINTR;
1409 }
1410
1411 /* ecspi has a HW issue when works in Slave mode,
1412 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1413 * ECSPI_TXDATA keeps shift out the last word data,
1414 * so we have to disable ECSPI when in slave mode after the
1415 * transfer completes
1416 */
1417 if (spi_imx->devtype_data->disable)
1418 spi_imx->devtype_data->disable(spi_imx);
1419
1420 return ret;
1421 }
1422
1423 static int spi_imx_transfer(struct spi_device *spi,
1424 struct spi_transfer *transfer)
1425 {
1426 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1427
1428 /* flush rxfifo before transfer */
1429 while (spi_imx->devtype_data->rx_available(spi_imx))
1430 spi_imx->rx(spi_imx);
1431
1432 if (spi_imx->slave_mode)
1433 return spi_imx_pio_transfer_slave(spi, transfer);
1434
1435 if (spi_imx->usedma)
1436 return spi_imx_dma_transfer(spi_imx, transfer);
1437 else
1438 return spi_imx_pio_transfer(spi, transfer);
1439 }
1440
1441 static int spi_imx_setup(struct spi_device *spi)
1442 {
1443 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1444 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1445
1446 if (spi->mode & SPI_NO_CS)
1447 return 0;
1448
1449 if (gpio_is_valid(spi->cs_gpio))
1450 gpio_direction_output(spi->cs_gpio,
1451 spi->mode & SPI_CS_HIGH ? 0 : 1);
1452
1453 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1454
1455 return 0;
1456 }
1457
1458 static void spi_imx_cleanup(struct spi_device *spi)
1459 {
1460 }
1461
1462 static int
1463 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1464 {
1465 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1466 int ret;
1467
1468 ret = clk_enable(spi_imx->clk_per);
1469 if (ret)
1470 return ret;
1471
1472 ret = clk_enable(spi_imx->clk_ipg);
1473 if (ret) {
1474 clk_disable(spi_imx->clk_per);
1475 return ret;
1476 }
1477
1478 return 0;
1479 }
1480
1481 static int
1482 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1483 {
1484 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1485
1486 clk_disable(spi_imx->clk_ipg);
1487 clk_disable(spi_imx->clk_per);
1488 return 0;
1489 }
1490
1491 static int spi_imx_slave_abort(struct spi_master *master)
1492 {
1493 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1494
1495 spi_imx->slave_aborted = true;
1496 complete(&spi_imx->xfer_done);
1497
1498 return 0;
1499 }
1500
1501 static int spi_imx_probe(struct platform_device *pdev)
1502 {
1503 struct device_node *np = pdev->dev.of_node;
1504 const struct of_device_id *of_id =
1505 of_match_device(spi_imx_dt_ids, &pdev->dev);
1506 struct spi_imx_master *mxc_platform_info =
1507 dev_get_platdata(&pdev->dev);
1508 struct spi_master *master;
1509 struct spi_imx_data *spi_imx;
1510 struct resource *res;
1511 int i, ret, irq, spi_drctl;
1512 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1513 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1514 bool slave_mode;
1515
1516 if (!np && !mxc_platform_info) {
1517 dev_err(&pdev->dev, "can't get the platform data\n");
1518 return -EINVAL;
1519 }
1520
1521 slave_mode = devtype_data->has_slavemode &&
1522 of_property_read_bool(np, "spi-slave");
1523 if (slave_mode)
1524 master = spi_alloc_slave(&pdev->dev,
1525 sizeof(struct spi_imx_data));
1526 else
1527 master = spi_alloc_master(&pdev->dev,
1528 sizeof(struct spi_imx_data));
1529 if (!master)
1530 return -ENOMEM;
1531
1532 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1533 if ((ret < 0) || (spi_drctl >= 0x3)) {
1534 /* '11' is reserved */
1535 spi_drctl = 0;
1536 }
1537
1538 platform_set_drvdata(pdev, master);
1539
1540 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1541 master->bus_num = np ? -1 : pdev->id;
1542
1543 spi_imx = spi_master_get_devdata(master);
1544 spi_imx->bitbang.master = master;
1545 spi_imx->dev = &pdev->dev;
1546 spi_imx->slave_mode = slave_mode;
1547
1548 spi_imx->devtype_data = devtype_data;
1549
1550 /* Get number of chip selects, either platform data or OF */
1551 if (mxc_platform_info) {
1552 master->num_chipselect = mxc_platform_info->num_chipselect;
1553 if (mxc_platform_info->chipselect) {
1554 master->cs_gpios = devm_kcalloc(&master->dev,
1555 master->num_chipselect, sizeof(int),
1556 GFP_KERNEL);
1557 if (!master->cs_gpios)
1558 return -ENOMEM;
1559
1560 for (i = 0; i < master->num_chipselect; i++)
1561 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1562 }
1563 } else {
1564 u32 num_cs;
1565
1566 if (!of_property_read_u32(np, "num-cs", &num_cs))
1567 master->num_chipselect = num_cs;
1568 /* If not preset, default value of 1 is used */
1569 }
1570
1571 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1572 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1573 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1574 spi_imx->bitbang.master->setup = spi_imx_setup;
1575 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1576 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1577 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1578 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1579 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1580 | SPI_NO_CS;
1581 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1582 is_imx53_ecspi(spi_imx))
1583 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1584
1585 spi_imx->spi_drctl = spi_drctl;
1586
1587 init_completion(&spi_imx->xfer_done);
1588
1589 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1590 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1591 if (IS_ERR(spi_imx->base)) {
1592 ret = PTR_ERR(spi_imx->base);
1593 goto out_master_put;
1594 }
1595 spi_imx->base_phys = res->start;
1596
1597 irq = platform_get_irq(pdev, 0);
1598 if (irq < 0) {
1599 ret = irq;
1600 goto out_master_put;
1601 }
1602
1603 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1604 dev_name(&pdev->dev), spi_imx);
1605 if (ret) {
1606 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1607 goto out_master_put;
1608 }
1609
1610 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1611 if (IS_ERR(spi_imx->clk_ipg)) {
1612 ret = PTR_ERR(spi_imx->clk_ipg);
1613 goto out_master_put;
1614 }
1615
1616 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1617 if (IS_ERR(spi_imx->clk_per)) {
1618 ret = PTR_ERR(spi_imx->clk_per);
1619 goto out_master_put;
1620 }
1621
1622 ret = clk_prepare_enable(spi_imx->clk_per);
1623 if (ret)
1624 goto out_master_put;
1625
1626 ret = clk_prepare_enable(spi_imx->clk_ipg);
1627 if (ret)
1628 goto out_put_per;
1629
1630 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1631 /*
1632 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1633 * if validated on other chips.
1634 */
1635 if (spi_imx->devtype_data->has_dmamode) {
1636 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1637 if (ret == -EPROBE_DEFER)
1638 goto out_clk_put;
1639
1640 if (ret < 0)
1641 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1642 ret);
1643 }
1644
1645 spi_imx->devtype_data->reset(spi_imx);
1646
1647 spi_imx->devtype_data->intctrl(spi_imx, 0);
1648
1649 master->dev.of_node = pdev->dev.of_node;
1650 ret = spi_bitbang_start(&spi_imx->bitbang);
1651 if (ret) {
1652 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1653 goto out_clk_put;
1654 }
1655
1656 /* Request GPIO CS lines, if any */
1657 if (!spi_imx->slave_mode && master->cs_gpios) {
1658 for (i = 0; i < master->num_chipselect; i++) {
1659 if (!gpio_is_valid(master->cs_gpios[i]))
1660 continue;
1661
1662 ret = devm_gpio_request(&pdev->dev,
1663 master->cs_gpios[i],
1664 DRIVER_NAME);
1665 if (ret) {
1666 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1667 master->cs_gpios[i]);
1668 goto out_spi_bitbang;
1669 }
1670 }
1671 }
1672
1673 dev_info(&pdev->dev, "probed\n");
1674
1675 clk_disable(spi_imx->clk_ipg);
1676 clk_disable(spi_imx->clk_per);
1677 return ret;
1678
1679 out_spi_bitbang:
1680 spi_bitbang_stop(&spi_imx->bitbang);
1681 out_clk_put:
1682 clk_disable_unprepare(spi_imx->clk_ipg);
1683 out_put_per:
1684 clk_disable_unprepare(spi_imx->clk_per);
1685 out_master_put:
1686 spi_master_put(master);
1687
1688 return ret;
1689 }
1690
1691 static int spi_imx_remove(struct platform_device *pdev)
1692 {
1693 struct spi_master *master = platform_get_drvdata(pdev);
1694 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1695 int ret;
1696
1697 spi_bitbang_stop(&spi_imx->bitbang);
1698
1699 ret = clk_enable(spi_imx->clk_per);
1700 if (ret)
1701 return ret;
1702
1703 ret = clk_enable(spi_imx->clk_ipg);
1704 if (ret) {
1705 clk_disable(spi_imx->clk_per);
1706 return ret;
1707 }
1708
1709 writel(0, spi_imx->base + MXC_CSPICTRL);
1710 clk_disable_unprepare(spi_imx->clk_ipg);
1711 clk_disable_unprepare(spi_imx->clk_per);
1712 spi_imx_sdma_exit(spi_imx);
1713 spi_master_put(master);
1714
1715 return 0;
1716 }
1717
1718 static struct platform_driver spi_imx_driver = {
1719 .driver = {
1720 .name = DRIVER_NAME,
1721 .of_match_table = spi_imx_dt_ids,
1722 },
1723 .id_table = spi_imx_devtype,
1724 .probe = spi_imx_probe,
1725 .remove = spi_imx_remove,
1726 };
1727 module_platform_driver(spi_imx_driver);
1728
1729 MODULE_DESCRIPTION("SPI Controller driver");
1730 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1731 MODULE_LICENSE("GPL");
1732 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support