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staging: rtl8188eu: rename HalSetBrateCfg() - style
[linux/fpc-iii.git] / drivers / spi / spi-omap2-mcspi.c
blob508c61c669e7d701525af13309430d7a4d1e9ce8
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrj�l� <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/err.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/slab.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/gcd.h>
36
37 #include <linux/spi/spi.h>
38 #include <linux/gpio.h>
39
40 #include <linux/platform_data/spi-omap2-mcspi.h>
41
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
43 #define OMAP2_MCSPI_MAX_DIVIDER 4096
44 #define OMAP2_MCSPI_MAX_FIFODEPTH 64
45 #define OMAP2_MCSPI_MAX_FIFOWCNT 0xFFFF
46 #define SPI_AUTOSUSPEND_TIMEOUT 2000
47
48 #define OMAP2_MCSPI_REVISION 0x00
49 #define OMAP2_MCSPI_SYSSTATUS 0x14
50 #define OMAP2_MCSPI_IRQSTATUS 0x18
51 #define OMAP2_MCSPI_IRQENABLE 0x1c
52 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
53 #define OMAP2_MCSPI_SYST 0x24
54 #define OMAP2_MCSPI_MODULCTRL 0x28
55 #define OMAP2_MCSPI_XFERLEVEL 0x7c
56
57 /* per-channel banks, 0x14 bytes each, first is: */
58 #define OMAP2_MCSPI_CHCONF0 0x2c
59 #define OMAP2_MCSPI_CHSTAT0 0x30
60 #define OMAP2_MCSPI_CHCTRL0 0x34
61 #define OMAP2_MCSPI_TX0 0x38
62 #define OMAP2_MCSPI_RX0 0x3c
63
64 /* per-register bitmasks: */
65 #define OMAP2_MCSPI_IRQSTATUS_EOW BIT(17)
66
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE BIT(0)
68 #define OMAP2_MCSPI_MODULCTRL_MS BIT(2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST BIT(3)
70
71 #define OMAP2_MCSPI_CHCONF_PHA BIT(0)
72 #define OMAP2_MCSPI_CHCONF_POL BIT(1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL BIT(6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY BIT(12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY BIT(13)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW BIT(14)
80 #define OMAP2_MCSPI_CHCONF_DMAR BIT(15)
81 #define OMAP2_MCSPI_CHCONF_DPE0 BIT(16)
82 #define OMAP2_MCSPI_CHCONF_DPE1 BIT(17)
83 #define OMAP2_MCSPI_CHCONF_IS BIT(18)
84 #define OMAP2_MCSPI_CHCONF_TURBO BIT(19)
85 #define OMAP2_MCSPI_CHCONF_FORCE BIT(20)
86 #define OMAP2_MCSPI_CHCONF_FFET BIT(27)
87 #define OMAP2_MCSPI_CHCONF_FFER BIT(28)
88 #define OMAP2_MCSPI_CHCONF_CLKG BIT(29)
89
90 #define OMAP2_MCSPI_CHSTAT_RXS BIT(0)
91 #define OMAP2_MCSPI_CHSTAT_TXS BIT(1)
92 #define OMAP2_MCSPI_CHSTAT_EOT BIT(2)
93 #define OMAP2_MCSPI_CHSTAT_TXFFE BIT(3)
94
95 #define OMAP2_MCSPI_CHCTRL_EN BIT(0)
96 #define OMAP2_MCSPI_CHCTRL_EXTCLK_MASK (0xff << 8)
97
98 #define OMAP2_MCSPI_WAKEUPENABLE_WKEN BIT(0)
99
100 /* We have 2 DMA channels per CS, one for RX and one for TX */
101 struct omap2_mcspi_dma {
102 struct dma_chan *dma_tx;
103 struct dma_chan *dma_rx;
104
105 struct completion dma_tx_completion;
106 struct completion dma_rx_completion;
107
108 char dma_rx_ch_name[14];
109 char dma_tx_ch_name[14];
110 };
111
112 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
113 * cache operations; better heuristics consider wordsize and bitrate.
114 */
115 #define DMA_MIN_BYTES 160
116
117
118 /*
119 * Used for context save and restore, structure members to be updated whenever
120 * corresponding registers are modified.
121 */
122 struct omap2_mcspi_regs {
123 u32 modulctrl;
124 u32 wakeupenable;
125 struct list_head cs;
126 };
127
128 struct omap2_mcspi {
129 struct spi_master *master;
130 /* Virtual base address of the controller */
131 void __iomem *base;
132 unsigned long phys;
133 /* SPI1 has 4 channels, while SPI2 has 2 */
134 struct omap2_mcspi_dma *dma_channels;
135 struct device *dev;
136 struct omap2_mcspi_regs ctx;
137 int fifo_depth;
138 unsigned int pin_dir:1;
139 };
140
141 struct omap2_mcspi_cs {
142 void __iomem *base;
143 unsigned long phys;
144 int word_len;
145 u16 mode;
146 struct list_head node;
147 /* Context save and restore shadow register */
148 u32 chconf0, chctrl0;
149 };
150
151 static inline void mcspi_write_reg(struct spi_master *master,
152 int idx, u32 val)
153 {
154 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
155
156 writel_relaxed(val, mcspi->base + idx);
157 }
158
159 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
160 {
161 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
162
163 return readl_relaxed(mcspi->base + idx);
164 }
165
166 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
167 int idx, u32 val)
168 {
169 struct omap2_mcspi_cs *cs = spi->controller_state;
170
171 writel_relaxed(val, cs->base + idx);
172 }
173
174 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
175 {
176 struct omap2_mcspi_cs *cs = spi->controller_state;
177
178 return readl_relaxed(cs->base + idx);
179 }
180
181 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
182 {
183 struct omap2_mcspi_cs *cs = spi->controller_state;
184
185 return cs->chconf0;
186 }
187
188 static inline void mcspi_write_chconf0(const struct spi_device *spi, u32 val)
189 {
190 struct omap2_mcspi_cs *cs = spi->controller_state;
191
192 cs->chconf0 = val;
193 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
194 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
195 }
196
197 static inline int mcspi_bytes_per_word(int word_len)
198 {
199 if (word_len <= 8)
200 return 1;
201 else if (word_len <= 16)
202 return 2;
203 else /* word_len <= 32 */
204 return 4;
205 }
206
207 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
208 int is_read, int enable)
209 {
210 u32 l, rw;
211
212 l = mcspi_cached_chconf0(spi);
213
214 if (is_read) /* 1 is read, 0 write */
215 rw = OMAP2_MCSPI_CHCONF_DMAR;
216 else
217 rw = OMAP2_MCSPI_CHCONF_DMAW;
218
219 if (enable)
220 l |= rw;
221 else
222 l &= ~rw;
223
224 mcspi_write_chconf0(spi, l);
225 }
226
227 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
228 {
229 struct omap2_mcspi_cs *cs = spi->controller_state;
230 u32 l;
231
232 l = cs->chctrl0;
233 if (enable)
234 l |= OMAP2_MCSPI_CHCTRL_EN;
235 else
236 l &= ~OMAP2_MCSPI_CHCTRL_EN;
237 cs->chctrl0 = l;
238 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
239 /* Flash post-writes */
240 mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCTRL0);
241 }
242
243 static void omap2_mcspi_set_cs(struct spi_device *spi, bool enable)
244 {
245 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
246 u32 l;
247
248 /* The controller handles the inverted chip selects
249 * using the OMAP2_MCSPI_CHCONF_EPOL bit so revert
250 * the inversion from the core spi_set_cs function.
251 */
252 if (spi->mode & SPI_CS_HIGH)
253 enable = !enable;
254
255 if (spi->controller_state) {
256 int err = pm_runtime_get_sync(mcspi->dev);
257 if (err < 0) {
258 pm_runtime_put_noidle(mcspi->dev);
259 dev_err(mcspi->dev, "failed to get sync: %d\n", err);
260 return;
261 }
262
263 l = mcspi_cached_chconf0(spi);
264
265 if (enable)
266 l &= ~OMAP2_MCSPI_CHCONF_FORCE;
267 else
268 l |= OMAP2_MCSPI_CHCONF_FORCE;
269
270 mcspi_write_chconf0(spi, l);
271
272 pm_runtime_mark_last_busy(mcspi->dev);
273 pm_runtime_put_autosuspend(mcspi->dev);
274 }
275 }
276
277 static void omap2_mcspi_set_master_mode(struct spi_master *master)
278 {
279 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
280 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
281 u32 l;
282
283 /*
284 * Setup when switching from (reset default) slave mode
285 * to single-channel master mode
286 */
287 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
288 l &= ~(OMAP2_MCSPI_MODULCTRL_STEST | OMAP2_MCSPI_MODULCTRL_MS);
289 l |= OMAP2_MCSPI_MODULCTRL_SINGLE;
290 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
291
292 ctx->modulctrl = l;
293 }
294
295 static void omap2_mcspi_set_fifo(const struct spi_device *spi,
296 struct spi_transfer *t, int enable)
297 {
298 struct spi_master *master = spi->master;
299 struct omap2_mcspi_cs *cs = spi->controller_state;
300 struct omap2_mcspi *mcspi;
301 unsigned int wcnt;
302 int max_fifo_depth, fifo_depth, bytes_per_word;
303 u32 chconf, xferlevel;
304
305 mcspi = spi_master_get_devdata(master);
306
307 chconf = mcspi_cached_chconf0(spi);
308 if (enable) {
309 bytes_per_word = mcspi_bytes_per_word(cs->word_len);
310 if (t->len % bytes_per_word != 0)
311 goto disable_fifo;
312
313 if (t->rx_buf != NULL && t->tx_buf != NULL)
314 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH / 2;
315 else
316 max_fifo_depth = OMAP2_MCSPI_MAX_FIFODEPTH;
317
318 fifo_depth = gcd(t->len, max_fifo_depth);
319 if (fifo_depth < 2 || fifo_depth % bytes_per_word != 0)
320 goto disable_fifo;
321
322 wcnt = t->len / bytes_per_word;
323 if (wcnt > OMAP2_MCSPI_MAX_FIFOWCNT)
324 goto disable_fifo;
325
326 xferlevel = wcnt << 16;
327 if (t->rx_buf != NULL) {
328 chconf |= OMAP2_MCSPI_CHCONF_FFER;
329 xferlevel |= (fifo_depth - 1) << 8;
330 }
331 if (t->tx_buf != NULL) {
332 chconf |= OMAP2_MCSPI_CHCONF_FFET;
333 xferlevel |= fifo_depth - 1;
334 }
335
336 mcspi_write_reg(master, OMAP2_MCSPI_XFERLEVEL, xferlevel);
337 mcspi_write_chconf0(spi, chconf);
338 mcspi->fifo_depth = fifo_depth;
339
340 return;
341 }
342
343 disable_fifo:
344 if (t->rx_buf != NULL)
345 chconf &= ~OMAP2_MCSPI_CHCONF_FFER;
346
347 if (t->tx_buf != NULL)
348 chconf &= ~OMAP2_MCSPI_CHCONF_FFET;
349
350 mcspi_write_chconf0(spi, chconf);
351 mcspi->fifo_depth = 0;
352 }
353
354 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
355 {
356 unsigned long timeout;
357
358 timeout = jiffies + msecs_to_jiffies(1000);
359 while (!(readl_relaxed(reg) & bit)) {
360 if (time_after(jiffies, timeout)) {
361 if (!(readl_relaxed(reg) & bit))
362 return -ETIMEDOUT;
363 else
364 return 0;
365 }
366 cpu_relax();
367 }
368 return 0;
369 }
370
371 static void omap2_mcspi_rx_callback(void *data)
372 {
373 struct spi_device *spi = data;
374 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
375 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
376
377 /* We must disable the DMA RX request */
378 omap2_mcspi_set_dma_req(spi, 1, 0);
379
380 complete(&mcspi_dma->dma_rx_completion);
381 }
382
383 static void omap2_mcspi_tx_callback(void *data)
384 {
385 struct spi_device *spi = data;
386 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
387 struct omap2_mcspi_dma *mcspi_dma = &mcspi->dma_channels[spi->chip_select];
388
389 /* We must disable the DMA TX request */
390 omap2_mcspi_set_dma_req(spi, 0, 0);
391
392 complete(&mcspi_dma->dma_tx_completion);
393 }
394
395 static void omap2_mcspi_tx_dma(struct spi_device *spi,
396 struct spi_transfer *xfer,
397 struct dma_slave_config cfg)
398 {
399 struct omap2_mcspi *mcspi;
400 struct omap2_mcspi_dma *mcspi_dma;
401
402 mcspi = spi_master_get_devdata(spi->master);
403 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
404
405 if (mcspi_dma->dma_tx) {
406 struct dma_async_tx_descriptor *tx;
407
408 dmaengine_slave_config(mcspi_dma->dma_tx, &cfg);
409
410 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_tx, xfer->tx_sg.sgl,
411 xfer->tx_sg.nents,
412 DMA_MEM_TO_DEV,
413 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
414 if (tx) {
415 tx->callback = omap2_mcspi_tx_callback;
416 tx->callback_param = spi;
417 dmaengine_submit(tx);
418 } else {
419 /* FIXME: fall back to PIO? */
420 }
421 }
422 dma_async_issue_pending(mcspi_dma->dma_tx);
423 omap2_mcspi_set_dma_req(spi, 0, 1);
424
425 }
426
427 static unsigned
428 omap2_mcspi_rx_dma(struct spi_device *spi, struct spi_transfer *xfer,
429 struct dma_slave_config cfg,
430 unsigned es)
431 {
432 struct omap2_mcspi *mcspi;
433 struct omap2_mcspi_dma *mcspi_dma;
434 unsigned int count, transfer_reduction = 0;
435 struct scatterlist *sg_out[2];
436 int nb_sizes = 0, out_mapped_nents[2], ret, x;
437 size_t sizes[2];
438 u32 l;
439 int elements = 0;
440 int word_len, element_count;
441 struct omap2_mcspi_cs *cs = spi->controller_state;
442 void __iomem *chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
443
444 mcspi = spi_master_get_devdata(spi->master);
445 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
446 count = xfer->len;
447
448 /*
449 * In the "End-of-Transfer Procedure" section for DMA RX in OMAP35x TRM
450 * it mentions reducing DMA transfer length by one element in master
451 * normal mode.
452 */
453 if (mcspi->fifo_depth == 0)
454 transfer_reduction = es;
455
456 word_len = cs->word_len;
457 l = mcspi_cached_chconf0(spi);
458
459 if (word_len <= 8)
460 element_count = count;
461 else if (word_len <= 16)
462 element_count = count >> 1;
463 else /* word_len <= 32 */
464 element_count = count >> 2;
465
466 if (mcspi_dma->dma_rx) {
467 struct dma_async_tx_descriptor *tx;
468
469 dmaengine_slave_config(mcspi_dma->dma_rx, &cfg);
470
471 /*
472 * Reduce DMA transfer length by one more if McSPI is
473 * configured in turbo mode.
474 */
475 if ((l & OMAP2_MCSPI_CHCONF_TURBO) && mcspi->fifo_depth == 0)
476 transfer_reduction += es;
477
478 if (transfer_reduction) {
479 /* Split sgl into two. The second sgl won't be used. */
480 sizes[0] = count - transfer_reduction;
481 sizes[1] = transfer_reduction;
482 nb_sizes = 2;
483 } else {
484 /*
485 * Don't bother splitting the sgl. This essentially
486 * clones the original sgl.
487 */
488 sizes[0] = count;
489 nb_sizes = 1;
490 }
491
492 ret = sg_split(xfer->rx_sg.sgl, xfer->rx_sg.nents,
493 0, nb_sizes,
494 sizes,
495 sg_out, out_mapped_nents,
496 GFP_KERNEL);
497
498 if (ret < 0) {
499 dev_err(&spi->dev, "sg_split failed\n");
500 return 0;
501 }
502
503 tx = dmaengine_prep_slave_sg(mcspi_dma->dma_rx,
504 sg_out[0],
505 out_mapped_nents[0],
506 DMA_DEV_TO_MEM,
507 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
508 if (tx) {
509 tx->callback = omap2_mcspi_rx_callback;
510 tx->callback_param = spi;
511 dmaengine_submit(tx);
512 } else {
513 /* FIXME: fall back to PIO? */
514 }
515 }
516
517 dma_async_issue_pending(mcspi_dma->dma_rx);
518 omap2_mcspi_set_dma_req(spi, 1, 1);
519
520 wait_for_completion(&mcspi_dma->dma_rx_completion);
521
522 for (x = 0; x < nb_sizes; x++)
523 kfree(sg_out[x]);
524
525 if (mcspi->fifo_depth > 0)
526 return count;
527
528 /*
529 * Due to the DMA transfer length reduction the missing bytes must
530 * be read manually to receive all of the expected data.
531 */
532 omap2_mcspi_set_enable(spi, 0);
533
534 elements = element_count - 1;
535
536 if (l & OMAP2_MCSPI_CHCONF_TURBO) {
537 elements--;
538
539 if (!mcspi_wait_for_reg_bit(chstat_reg,
540 OMAP2_MCSPI_CHSTAT_RXS)) {
541 u32 w;
542
543 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
544 if (word_len <= 8)
545 ((u8 *)xfer->rx_buf)[elements++] = w;
546 else if (word_len <= 16)
547 ((u16 *)xfer->rx_buf)[elements++] = w;
548 else /* word_len <= 32 */
549 ((u32 *)xfer->rx_buf)[elements++] = w;
550 } else {
551 int bytes_per_word = mcspi_bytes_per_word(word_len);
552 dev_err(&spi->dev, "DMA RX penultimate word empty\n");
553 count -= (bytes_per_word << 1);
554 omap2_mcspi_set_enable(spi, 1);
555 return count;
556 }
557 }
558 if (!mcspi_wait_for_reg_bit(chstat_reg, OMAP2_MCSPI_CHSTAT_RXS)) {
559 u32 w;
560
561 w = mcspi_read_cs_reg(spi, OMAP2_MCSPI_RX0);
562 if (word_len <= 8)
563 ((u8 *)xfer->rx_buf)[elements] = w;
564 else if (word_len <= 16)
565 ((u16 *)xfer->rx_buf)[elements] = w;
566 else /* word_len <= 32 */
567 ((u32 *)xfer->rx_buf)[elements] = w;
568 } else {
569 dev_err(&spi->dev, "DMA RX last word empty\n");
570 count -= mcspi_bytes_per_word(word_len);
571 }
572 omap2_mcspi_set_enable(spi, 1);
573 return count;
574 }
575
576 static unsigned
577 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
578 {
579 struct omap2_mcspi *mcspi;
580 struct omap2_mcspi_cs *cs = spi->controller_state;
581 struct omap2_mcspi_dma *mcspi_dma;
582 unsigned int count;
583 u8 *rx;
584 const u8 *tx;
585 struct dma_slave_config cfg;
586 enum dma_slave_buswidth width;
587 unsigned es;
588 u32 burst;
589 void __iomem *chstat_reg;
590 void __iomem *irqstat_reg;
591 int wait_res;
592
593 mcspi = spi_master_get_devdata(spi->master);
594 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
595
596 if (cs->word_len <= 8) {
597 width = DMA_SLAVE_BUSWIDTH_1_BYTE;
598 es = 1;
599 } else if (cs->word_len <= 16) {
600 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
601 es = 2;
602 } else {
603 width = DMA_SLAVE_BUSWIDTH_4_BYTES;
604 es = 4;
605 }
606
607 count = xfer->len;
608 burst = 1;
609
610 if (mcspi->fifo_depth > 0) {
611 if (count > mcspi->fifo_depth)
612 burst = mcspi->fifo_depth / es;
613 else
614 burst = count / es;
615 }
616
617 memset(&cfg, 0, sizeof(cfg));
618 cfg.src_addr = cs->phys + OMAP2_MCSPI_RX0;
619 cfg.dst_addr = cs->phys + OMAP2_MCSPI_TX0;
620 cfg.src_addr_width = width;
621 cfg.dst_addr_width = width;
622 cfg.src_maxburst = burst;
623 cfg.dst_maxburst = burst;
624
625 rx = xfer->rx_buf;
626 tx = xfer->tx_buf;
627
628 if (tx != NULL)
629 omap2_mcspi_tx_dma(spi, xfer, cfg);
630
631 if (rx != NULL)
632 count = omap2_mcspi_rx_dma(spi, xfer, cfg, es);
633
634 if (tx != NULL) {
635 wait_for_completion(&mcspi_dma->dma_tx_completion);
636
637 if (mcspi->fifo_depth > 0) {
638 irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
639
640 if (mcspi_wait_for_reg_bit(irqstat_reg,
641 OMAP2_MCSPI_IRQSTATUS_EOW) < 0)
642 dev_err(&spi->dev, "EOW timed out\n");
643
644 mcspi_write_reg(mcspi->master, OMAP2_MCSPI_IRQSTATUS,
645 OMAP2_MCSPI_IRQSTATUS_EOW);
646 }
647
648 /* for TX_ONLY mode, be sure all words have shifted out */
649 if (rx == NULL) {
650 chstat_reg = cs->base + OMAP2_MCSPI_CHSTAT0;
651 if (mcspi->fifo_depth > 0) {
652 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
653 OMAP2_MCSPI_CHSTAT_TXFFE);
654 if (wait_res < 0)
655 dev_err(&spi->dev, "TXFFE timed out\n");
656 } else {
657 wait_res = mcspi_wait_for_reg_bit(chstat_reg,
658 OMAP2_MCSPI_CHSTAT_TXS);
659 if (wait_res < 0)
660 dev_err(&spi->dev, "TXS timed out\n");
661 }
662 if (wait_res >= 0 &&
663 (mcspi_wait_for_reg_bit(chstat_reg,
664 OMAP2_MCSPI_CHSTAT_EOT) < 0))
665 dev_err(&spi->dev, "EOT timed out\n");
666 }
667 }
668 return count;
669 }
670
671 static unsigned
672 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
673 {
674 struct omap2_mcspi_cs *cs = spi->controller_state;
675 unsigned int count, c;
676 u32 l;
677 void __iomem *base = cs->base;
678 void __iomem *tx_reg;
679 void __iomem *rx_reg;
680 void __iomem *chstat_reg;
681 int word_len;
682
683 count = xfer->len;
684 c = count;
685 word_len = cs->word_len;
686
687 l = mcspi_cached_chconf0(spi);
688
689 /* We store the pre-calculated register addresses on stack to speed
690 * up the transfer loop. */
691 tx_reg = base + OMAP2_MCSPI_TX0;
692 rx_reg = base + OMAP2_MCSPI_RX0;
693 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
694
695 if (c < (word_len>>3))
696 return 0;
697
698 if (word_len <= 8) {
699 u8 *rx;
700 const u8 *tx;
701
702 rx = xfer->rx_buf;
703 tx = xfer->tx_buf;
704
705 do {
706 c -= 1;
707 if (tx != NULL) {
708 if (mcspi_wait_for_reg_bit(chstat_reg,
709 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
710 dev_err(&spi->dev, "TXS timed out\n");
711 goto out;
712 }
713 dev_vdbg(&spi->dev, "write-%d %02x\n",
714 word_len, *tx);
715 writel_relaxed(*tx++, tx_reg);
716 }
717 if (rx != NULL) {
718 if (mcspi_wait_for_reg_bit(chstat_reg,
719 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
720 dev_err(&spi->dev, "RXS timed out\n");
721 goto out;
722 }
723
724 if (c == 1 && tx == NULL &&
725 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
726 omap2_mcspi_set_enable(spi, 0);
727 *rx++ = readl_relaxed(rx_reg);
728 dev_vdbg(&spi->dev, "read-%d %02x\n",
729 word_len, *(rx - 1));
730 if (mcspi_wait_for_reg_bit(chstat_reg,
731 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
732 dev_err(&spi->dev,
733 "RXS timed out\n");
734 goto out;
735 }
736 c = 0;
737 } else if (c == 0 && tx == NULL) {
738 omap2_mcspi_set_enable(spi, 0);
739 }
740
741 *rx++ = readl_relaxed(rx_reg);
742 dev_vdbg(&spi->dev, "read-%d %02x\n",
743 word_len, *(rx - 1));
744 }
745 } while (c);
746 } else if (word_len <= 16) {
747 u16 *rx;
748 const u16 *tx;
749
750 rx = xfer->rx_buf;
751 tx = xfer->tx_buf;
752 do {
753 c -= 2;
754 if (tx != NULL) {
755 if (mcspi_wait_for_reg_bit(chstat_reg,
756 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
757 dev_err(&spi->dev, "TXS timed out\n");
758 goto out;
759 }
760 dev_vdbg(&spi->dev, "write-%d %04x\n",
761 word_len, *tx);
762 writel_relaxed(*tx++, tx_reg);
763 }
764 if (rx != NULL) {
765 if (mcspi_wait_for_reg_bit(chstat_reg,
766 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
767 dev_err(&spi->dev, "RXS timed out\n");
768 goto out;
769 }
770
771 if (c == 2 && tx == NULL &&
772 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
773 omap2_mcspi_set_enable(spi, 0);
774 *rx++ = readl_relaxed(rx_reg);
775 dev_vdbg(&spi->dev, "read-%d %04x\n",
776 word_len, *(rx - 1));
777 if (mcspi_wait_for_reg_bit(chstat_reg,
778 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
779 dev_err(&spi->dev,
780 "RXS timed out\n");
781 goto out;
782 }
783 c = 0;
784 } else if (c == 0 && tx == NULL) {
785 omap2_mcspi_set_enable(spi, 0);
786 }
787
788 *rx++ = readl_relaxed(rx_reg);
789 dev_vdbg(&spi->dev, "read-%d %04x\n",
790 word_len, *(rx - 1));
791 }
792 } while (c >= 2);
793 } else if (word_len <= 32) {
794 u32 *rx;
795 const u32 *tx;
796
797 rx = xfer->rx_buf;
798 tx = xfer->tx_buf;
799 do {
800 c -= 4;
801 if (tx != NULL) {
802 if (mcspi_wait_for_reg_bit(chstat_reg,
803 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
804 dev_err(&spi->dev, "TXS timed out\n");
805 goto out;
806 }
807 dev_vdbg(&spi->dev, "write-%d %08x\n",
808 word_len, *tx);
809 writel_relaxed(*tx++, tx_reg);
810 }
811 if (rx != NULL) {
812 if (mcspi_wait_for_reg_bit(chstat_reg,
813 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
814 dev_err(&spi->dev, "RXS timed out\n");
815 goto out;
816 }
817
818 if (c == 4 && tx == NULL &&
819 (l & OMAP2_MCSPI_CHCONF_TURBO)) {
820 omap2_mcspi_set_enable(spi, 0);
821 *rx++ = readl_relaxed(rx_reg);
822 dev_vdbg(&spi->dev, "read-%d %08x\n",
823 word_len, *(rx - 1));
824 if (mcspi_wait_for_reg_bit(chstat_reg,
825 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
826 dev_err(&spi->dev,
827 "RXS timed out\n");
828 goto out;
829 }
830 c = 0;
831 } else if (c == 0 && tx == NULL) {
832 omap2_mcspi_set_enable(spi, 0);
833 }
834
835 *rx++ = readl_relaxed(rx_reg);
836 dev_vdbg(&spi->dev, "read-%d %08x\n",
837 word_len, *(rx - 1));
838 }
839 } while (c >= 4);
840 }
841
842 /* for TX_ONLY mode, be sure all words have shifted out */
843 if (xfer->rx_buf == NULL) {
844 if (mcspi_wait_for_reg_bit(chstat_reg,
845 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
846 dev_err(&spi->dev, "TXS timed out\n");
847 } else if (mcspi_wait_for_reg_bit(chstat_reg,
848 OMAP2_MCSPI_CHSTAT_EOT) < 0)
849 dev_err(&spi->dev, "EOT timed out\n");
850
851 /* disable chan to purge rx datas received in TX_ONLY transfer,
852 * otherwise these rx datas will affect the direct following
853 * RX_ONLY transfer.
854 */
855 omap2_mcspi_set_enable(spi, 0);
856 }
857 out:
858 omap2_mcspi_set_enable(spi, 1);
859 return count - c;
860 }
861
862 static u32 omap2_mcspi_calc_divisor(u32 speed_hz)
863 {
864 u32 div;
865
866 for (div = 0; div < 15; div++)
867 if (speed_hz >= (OMAP2_MCSPI_MAX_FREQ >> div))
868 return div;
869
870 return 15;
871 }
872
873 /* called only when no transfer is active to this device */
874 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
875 struct spi_transfer *t)
876 {
877 struct omap2_mcspi_cs *cs = spi->controller_state;
878 struct omap2_mcspi *mcspi;
879 u32 l = 0, clkd = 0, div, extclk = 0, clkg = 0;
880 u8 word_len = spi->bits_per_word;
881 u32 speed_hz = spi->max_speed_hz;
882
883 mcspi = spi_master_get_devdata(spi->master);
884
885 if (t != NULL && t->bits_per_word)
886 word_len = t->bits_per_word;
887
888 cs->word_len = word_len;
889
890 if (t && t->speed_hz)
891 speed_hz = t->speed_hz;
892
893 speed_hz = min_t(u32, speed_hz, OMAP2_MCSPI_MAX_FREQ);
894 if (speed_hz < (OMAP2_MCSPI_MAX_FREQ / OMAP2_MCSPI_MAX_DIVIDER)) {
895 clkd = omap2_mcspi_calc_divisor(speed_hz);
896 speed_hz = OMAP2_MCSPI_MAX_FREQ >> clkd;
897 clkg = 0;
898 } else {
899 div = (OMAP2_MCSPI_MAX_FREQ + speed_hz - 1) / speed_hz;
900 speed_hz = OMAP2_MCSPI_MAX_FREQ / div;
901 clkd = (div - 1) & 0xf;
902 extclk = (div - 1) >> 4;
903 clkg = OMAP2_MCSPI_CHCONF_CLKG;
904 }
905
906 l = mcspi_cached_chconf0(spi);
907
908 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
909 * REVISIT: this controller could support SPI_3WIRE mode.
910 */
911 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
912 l &= ~OMAP2_MCSPI_CHCONF_IS;
913 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
914 l |= OMAP2_MCSPI_CHCONF_DPE0;
915 } else {
916 l |= OMAP2_MCSPI_CHCONF_IS;
917 l |= OMAP2_MCSPI_CHCONF_DPE1;
918 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
919 }
920
921 /* wordlength */
922 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
923 l |= (word_len - 1) << 7;
924
925 /* set chipselect polarity; manage with FORCE */
926 if (!(spi->mode & SPI_CS_HIGH))
927 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
928 else
929 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
930
931 /* set clock divisor */
932 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
933 l |= clkd << 2;
934
935 /* set clock granularity */
936 l &= ~OMAP2_MCSPI_CHCONF_CLKG;
937 l |= clkg;
938 if (clkg) {
939 cs->chctrl0 &= ~OMAP2_MCSPI_CHCTRL_EXTCLK_MASK;
940 cs->chctrl0 |= extclk << 8;
941 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, cs->chctrl0);
942 }
943
944 /* set SPI mode 0..3 */
945 if (spi->mode & SPI_CPOL)
946 l |= OMAP2_MCSPI_CHCONF_POL;
947 else
948 l &= ~OMAP2_MCSPI_CHCONF_POL;
949 if (spi->mode & SPI_CPHA)
950 l |= OMAP2_MCSPI_CHCONF_PHA;
951 else
952 l &= ~OMAP2_MCSPI_CHCONF_PHA;
953
954 mcspi_write_chconf0(spi, l);
955
956 cs->mode = spi->mode;
957
958 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
959 speed_hz,
960 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
961 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
962
963 return 0;
964 }
965
966 /*
967 * Note that we currently allow DMA only if we get a channel
968 * for both rx and tx. Otherwise we'll do PIO for both rx and tx.
969 */
970 static int omap2_mcspi_request_dma(struct spi_device *spi)
971 {
972 struct spi_master *master = spi->master;
973 struct omap2_mcspi *mcspi;
974 struct omap2_mcspi_dma *mcspi_dma;
975 int ret = 0;
976
977 mcspi = spi_master_get_devdata(master);
978 mcspi_dma = mcspi->dma_channels + spi->chip_select;
979
980 init_completion(&mcspi_dma->dma_rx_completion);
981 init_completion(&mcspi_dma->dma_tx_completion);
982
983 mcspi_dma->dma_rx = dma_request_chan(&master->dev,
984 mcspi_dma->dma_rx_ch_name);
985 if (IS_ERR(mcspi_dma->dma_rx)) {
986 ret = PTR_ERR(mcspi_dma->dma_rx);
987 mcspi_dma->dma_rx = NULL;
988 goto no_dma;
989 }
990
991 mcspi_dma->dma_tx = dma_request_chan(&master->dev,
992 mcspi_dma->dma_tx_ch_name);
993 if (IS_ERR(mcspi_dma->dma_tx)) {
994 ret = PTR_ERR(mcspi_dma->dma_tx);
995 mcspi_dma->dma_tx = NULL;
996 dma_release_channel(mcspi_dma->dma_rx);
997 mcspi_dma->dma_rx = NULL;
998 }
999
1000 no_dma:
1001 return ret;
1002 }
1003
1004 static int omap2_mcspi_setup(struct spi_device *spi)
1005 {
1006 int ret;
1007 struct omap2_mcspi *mcspi = spi_master_get_devdata(spi->master);
1008 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1009 struct omap2_mcspi_dma *mcspi_dma;
1010 struct omap2_mcspi_cs *cs = spi->controller_state;
1011
1012 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1013
1014 if (!cs) {
1015 cs = kzalloc(sizeof *cs, GFP_KERNEL);
1016 if (!cs)
1017 return -ENOMEM;
1018 cs->base = mcspi->base + spi->chip_select * 0x14;
1019 cs->phys = mcspi->phys + spi->chip_select * 0x14;
1020 cs->mode = 0;
1021 cs->chconf0 = 0;
1022 cs->chctrl0 = 0;
1023 spi->controller_state = cs;
1024 /* Link this to context save list */
1025 list_add_tail(&cs->node, &ctx->cs);
1026
1027 if (gpio_is_valid(spi->cs_gpio)) {
1028 ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
1029 if (ret) {
1030 dev_err(&spi->dev, "failed to request gpio\n");
1031 return ret;
1032 }
1033 gpio_direction_output(spi->cs_gpio,
1034 !(spi->mode & SPI_CS_HIGH));
1035 }
1036 }
1037
1038 if (!mcspi_dma->dma_rx || !mcspi_dma->dma_tx) {
1039 ret = omap2_mcspi_request_dma(spi);
1040 if (ret)
1041 dev_warn(&spi->dev, "not using DMA for McSPI (%d)\n",
1042 ret);
1043 }
1044
1045 ret = pm_runtime_get_sync(mcspi->dev);
1046 if (ret < 0) {
1047 pm_runtime_put_noidle(mcspi->dev);
1048
1049 return ret;
1050 }
1051
1052 ret = omap2_mcspi_setup_transfer(spi, NULL);
1053 pm_runtime_mark_last_busy(mcspi->dev);
1054 pm_runtime_put_autosuspend(mcspi->dev);
1055
1056 return ret;
1057 }
1058
1059 static void omap2_mcspi_cleanup(struct spi_device *spi)
1060 {
1061 struct omap2_mcspi *mcspi;
1062 struct omap2_mcspi_dma *mcspi_dma;
1063 struct omap2_mcspi_cs *cs;
1064
1065 mcspi = spi_master_get_devdata(spi->master);
1066
1067 if (spi->controller_state) {
1068 /* Unlink controller state from context save list */
1069 cs = spi->controller_state;
1070 list_del(&cs->node);
1071
1072 kfree(cs);
1073 }
1074
1075 if (spi->chip_select < spi->master->num_chipselect) {
1076 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
1077
1078 if (mcspi_dma->dma_rx) {
1079 dma_release_channel(mcspi_dma->dma_rx);
1080 mcspi_dma->dma_rx = NULL;
1081 }
1082 if (mcspi_dma->dma_tx) {
1083 dma_release_channel(mcspi_dma->dma_tx);
1084 mcspi_dma->dma_tx = NULL;
1085 }
1086 }
1087
1088 if (gpio_is_valid(spi->cs_gpio))
1089 gpio_free(spi->cs_gpio);
1090 }
1091
1092 static int omap2_mcspi_transfer_one(struct spi_master *master,
1093 struct spi_device *spi,
1094 struct spi_transfer *t)
1095 {
1096
1097 /* We only enable one channel at a time -- the one whose message is
1098 * -- although this controller would gladly
1099 * arbitrate among multiple channels. This corresponds to "single
1100 * channel" master mode. As a side effect, we need to manage the
1101 * chipselect with the FORCE bit ... CS != channel enable.
1102 */
1103
1104 struct omap2_mcspi *mcspi;
1105 struct omap2_mcspi_dma *mcspi_dma;
1106 struct omap2_mcspi_cs *cs;
1107 struct omap2_mcspi_device_config *cd;
1108 int par_override = 0;
1109 int status = 0;
1110 u32 chconf;
1111
1112 mcspi = spi_master_get_devdata(master);
1113 mcspi_dma = mcspi->dma_channels + spi->chip_select;
1114 cs = spi->controller_state;
1115 cd = spi->controller_data;
1116
1117 /*
1118 * The slave driver could have changed spi->mode in which case
1119 * it will be different from cs->mode (the current hardware setup).
1120 * If so, set par_override (even though its not a parity issue) so
1121 * omap2_mcspi_setup_transfer will be called to configure the hardware
1122 * with the correct mode on the first iteration of the loop below.
1123 */
1124 if (spi->mode != cs->mode)
1125 par_override = 1;
1126
1127 omap2_mcspi_set_enable(spi, 0);
1128
1129 if (gpio_is_valid(spi->cs_gpio))
1130 omap2_mcspi_set_cs(spi, spi->mode & SPI_CS_HIGH);
1131
1132 if (par_override ||
1133 (t->speed_hz != spi->max_speed_hz) ||
1134 (t->bits_per_word != spi->bits_per_word)) {
1135 par_override = 1;
1136 status = omap2_mcspi_setup_transfer(spi, t);
1137 if (status < 0)
1138 goto out;
1139 if (t->speed_hz == spi->max_speed_hz &&
1140 t->bits_per_word == spi->bits_per_word)
1141 par_override = 0;
1142 }
1143 if (cd && cd->cs_per_word) {
1144 chconf = mcspi->ctx.modulctrl;
1145 chconf &= ~OMAP2_MCSPI_MODULCTRL_SINGLE;
1146 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1147 mcspi->ctx.modulctrl =
1148 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1149 }
1150
1151 chconf = mcspi_cached_chconf0(spi);
1152 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
1153 chconf &= ~OMAP2_MCSPI_CHCONF_TURBO;
1154
1155 if (t->tx_buf == NULL)
1156 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
1157 else if (t->rx_buf == NULL)
1158 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
1159
1160 if (cd && cd->turbo_mode && t->tx_buf == NULL) {
1161 /* Turbo mode is for more than one word */
1162 if (t->len > ((cs->word_len + 7) >> 3))
1163 chconf |= OMAP2_MCSPI_CHCONF_TURBO;
1164 }
1165
1166 mcspi_write_chconf0(spi, chconf);
1167
1168 if (t->len) {
1169 unsigned count;
1170
1171 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1172 master->cur_msg_mapped &&
1173 master->can_dma(master, spi, t))
1174 omap2_mcspi_set_fifo(spi, t, 1);
1175
1176 omap2_mcspi_set_enable(spi, 1);
1177
1178 /* RX_ONLY mode needs dummy data in TX reg */
1179 if (t->tx_buf == NULL)
1180 writel_relaxed(0, cs->base
1181 + OMAP2_MCSPI_TX0);
1182
1183 if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
1184 master->cur_msg_mapped &&
1185 master->can_dma(master, spi, t))
1186 count = omap2_mcspi_txrx_dma(spi, t);
1187 else
1188 count = omap2_mcspi_txrx_pio(spi, t);
1189
1190 if (count != t->len) {
1191 status = -EIO;
1192 goto out;
1193 }
1194 }
1195
1196 omap2_mcspi_set_enable(spi, 0);
1197
1198 if (mcspi->fifo_depth > 0)
1199 omap2_mcspi_set_fifo(spi, t, 0);
1200
1201 out:
1202 /* Restore defaults if they were overriden */
1203 if (par_override) {
1204 par_override = 0;
1205 status = omap2_mcspi_setup_transfer(spi, NULL);
1206 }
1207
1208 if (cd && cd->cs_per_word) {
1209 chconf = mcspi->ctx.modulctrl;
1210 chconf |= OMAP2_MCSPI_MODULCTRL_SINGLE;
1211 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, chconf);
1212 mcspi->ctx.modulctrl =
1213 mcspi_read_cs_reg(spi, OMAP2_MCSPI_MODULCTRL);
1214 }
1215
1216 omap2_mcspi_set_enable(spi, 0);
1217
1218 if (gpio_is_valid(spi->cs_gpio))
1219 omap2_mcspi_set_cs(spi, !(spi->mode & SPI_CS_HIGH));
1220
1221 if (mcspi->fifo_depth > 0 && t)
1222 omap2_mcspi_set_fifo(spi, t, 0);
1223
1224 return status;
1225 }
1226
1227 static int omap2_mcspi_prepare_message(struct spi_master *master,
1228 struct spi_message *msg)
1229 {
1230 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1231 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1232 struct omap2_mcspi_cs *cs;
1233
1234 /* Only a single channel can have the FORCE bit enabled
1235 * in its chconf0 register.
1236 * Scan all channels and disable them except the current one.
1237 * A FORCE can remain from a last transfer having cs_change enabled
1238 */
1239 list_for_each_entry(cs, &ctx->cs, node) {
1240 if (msg->spi->controller_state == cs)
1241 continue;
1242
1243 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE)) {
1244 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1245 writel_relaxed(cs->chconf0,
1246 cs->base + OMAP2_MCSPI_CHCONF0);
1247 readl_relaxed(cs->base + OMAP2_MCSPI_CHCONF0);
1248 }
1249 }
1250
1251 return 0;
1252 }
1253
1254 static bool omap2_mcspi_can_dma(struct spi_master *master,
1255 struct spi_device *spi,
1256 struct spi_transfer *xfer)
1257 {
1258 return (xfer->len >= DMA_MIN_BYTES);
1259 }
1260
1261 static int omap2_mcspi_master_setup(struct omap2_mcspi *mcspi)
1262 {
1263 struct spi_master *master = mcspi->master;
1264 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1265 int ret = 0;
1266
1267 ret = pm_runtime_get_sync(mcspi->dev);
1268 if (ret < 0) {
1269 pm_runtime_put_noidle(mcspi->dev);
1270
1271 return ret;
1272 }
1273
1274 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE,
1275 OMAP2_MCSPI_WAKEUPENABLE_WKEN);
1276 ctx->wakeupenable = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
1277
1278 omap2_mcspi_set_master_mode(master);
1279 pm_runtime_mark_last_busy(mcspi->dev);
1280 pm_runtime_put_autosuspend(mcspi->dev);
1281 return 0;
1282 }
1283
1284 /*
1285 * When SPI wake up from off-mode, CS is in activate state. If it was in
1286 * inactive state when driver was suspend, then force it to inactive state at
1287 * wake up.
1288 */
1289 static int omap_mcspi_runtime_resume(struct device *dev)
1290 {
1291 struct spi_master *master = dev_get_drvdata(dev);
1292 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1293 struct omap2_mcspi_regs *ctx = &mcspi->ctx;
1294 struct omap2_mcspi_cs *cs;
1295
1296 /* McSPI: context restore */
1297 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, ctx->modulctrl);
1298 mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
1299
1300 list_for_each_entry(cs, &ctx->cs, node) {
1301 /*
1302 * We need to toggle CS state for OMAP take this
1303 * change in account.
1304 */
1305 if ((cs->chconf0 & OMAP2_MCSPI_CHCONF_FORCE) == 0) {
1306 cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
1307 writel_relaxed(cs->chconf0,
1308 cs->base + OMAP2_MCSPI_CHCONF0);
1309 cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
1310 writel_relaxed(cs->chconf0,
1311 cs->base + OMAP2_MCSPI_CHCONF0);
1312 } else {
1313 writel_relaxed(cs->chconf0,
1314 cs->base + OMAP2_MCSPI_CHCONF0);
1315 }
1316 }
1317
1318 return 0;
1319 }
1320
1321 static struct omap2_mcspi_platform_config omap2_pdata = {
1322 .regs_offset = 0,
1323 };
1324
1325 static struct omap2_mcspi_platform_config omap4_pdata = {
1326 .regs_offset = OMAP4_MCSPI_REG_OFFSET,
1327 };
1328
1329 static const struct of_device_id omap_mcspi_of_match[] = {
1330 {
1331 .compatible = "ti,omap2-mcspi",
1332 .data = &omap2_pdata,
1333 },
1334 {
1335 .compatible = "ti,omap4-mcspi",
1336 .data = &omap4_pdata,
1337 },
1338 { },
1339 };
1340 MODULE_DEVICE_TABLE(of, omap_mcspi_of_match);
1341
1342 static int omap2_mcspi_probe(struct platform_device *pdev)
1343 {
1344 struct spi_master *master;
1345 const struct omap2_mcspi_platform_config *pdata;
1346 struct omap2_mcspi *mcspi;
1347 struct resource *r;
1348 int status = 0, i;
1349 u32 regs_offset = 0;
1350 struct device_node *node = pdev->dev.of_node;
1351 const struct of_device_id *match;
1352
1353 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
1354 if (master == NULL) {
1355 dev_dbg(&pdev->dev, "master allocation failed\n");
1356 return -ENOMEM;
1357 }
1358
1359 /* the spi->mode bits understood by this driver: */
1360 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1361 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1362 master->setup = omap2_mcspi_setup;
1363 master->auto_runtime_pm = true;
1364 master->prepare_message = omap2_mcspi_prepare_message;
1365 master->can_dma = omap2_mcspi_can_dma;
1366 master->transfer_one = omap2_mcspi_transfer_one;
1367 master->set_cs = omap2_mcspi_set_cs;
1368 master->cleanup = omap2_mcspi_cleanup;
1369 master->dev.of_node = node;
1370 master->max_speed_hz = OMAP2_MCSPI_MAX_FREQ;
1371 master->min_speed_hz = OMAP2_MCSPI_MAX_FREQ >> 15;
1372
1373 platform_set_drvdata(pdev, master);
1374
1375 mcspi = spi_master_get_devdata(master);
1376 mcspi->master = master;
1377
1378 match = of_match_device(omap_mcspi_of_match, &pdev->dev);
1379 if (match) {
1380 u32 num_cs = 1; /* default number of chipselect */
1381 pdata = match->data;
1382
1383 of_property_read_u32(node, "ti,spi-num-cs", &num_cs);
1384 master->num_chipselect = num_cs;
1385 if (of_get_property(node, "ti,pindir-d0-out-d1-in", NULL))
1386 mcspi->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
1387 } else {
1388 pdata = dev_get_platdata(&pdev->dev);
1389 master->num_chipselect = pdata->num_cs;
1390 mcspi->pin_dir = pdata->pin_dir;
1391 }
1392 regs_offset = pdata->regs_offset;
1393
1394 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1395 mcspi->base = devm_ioremap_resource(&pdev->dev, r);
1396 if (IS_ERR(mcspi->base)) {
1397 status = PTR_ERR(mcspi->base);
1398 goto free_master;
1399 }
1400 mcspi->phys = r->start + regs_offset;
1401 mcspi->base += regs_offset;
1402
1403 mcspi->dev = &pdev->dev;
1404
1405 INIT_LIST_HEAD(&mcspi->ctx.cs);
1406
1407 mcspi->dma_channels = devm_kcalloc(&pdev->dev, master->num_chipselect,
1408 sizeof(struct omap2_mcspi_dma),
1409 GFP_KERNEL);
1410 if (mcspi->dma_channels == NULL) {
1411 status = -ENOMEM;
1412 goto free_master;
1413 }
1414
1415 for (i = 0; i < master->num_chipselect; i++) {
1416 sprintf(mcspi->dma_channels[i].dma_rx_ch_name, "rx%d", i);
1417 sprintf(mcspi->dma_channels[i].dma_tx_ch_name, "tx%d", i);
1418 }
1419
1420 pm_runtime_use_autosuspend(&pdev->dev);
1421 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1422 pm_runtime_enable(&pdev->dev);
1423
1424 status = omap2_mcspi_master_setup(mcspi);
1425 if (status < 0)
1426 goto disable_pm;
1427
1428 status = devm_spi_register_master(&pdev->dev, master);
1429 if (status < 0)
1430 goto disable_pm;
1431
1432 return status;
1433
1434 disable_pm:
1435 pm_runtime_dont_use_autosuspend(&pdev->dev);
1436 pm_runtime_put_sync(&pdev->dev);
1437 pm_runtime_disable(&pdev->dev);
1438 free_master:
1439 spi_master_put(master);
1440 return status;
1441 }
1442
1443 static int omap2_mcspi_remove(struct platform_device *pdev)
1444 {
1445 struct spi_master *master = platform_get_drvdata(pdev);
1446 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1447
1448 pm_runtime_dont_use_autosuspend(mcspi->dev);
1449 pm_runtime_put_sync(mcspi->dev);
1450 pm_runtime_disable(&pdev->dev);
1451
1452 return 0;
1453 }
1454
1455 /* work with hotplug and coldplug */
1456 MODULE_ALIAS("platform:omap2_mcspi");
1457
1458 #ifdef CONFIG_SUSPEND
1459 static int omap2_mcspi_suspend_noirq(struct device *dev)
1460 {
1461 return pinctrl_pm_select_sleep_state(dev);
1462 }
1463
1464 static int omap2_mcspi_resume_noirq(struct device *dev)
1465 {
1466 struct spi_master *master = dev_get_drvdata(dev);
1467 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
1468 int error;
1469
1470 error = pinctrl_pm_select_default_state(dev);
1471 if (error)
1472 dev_warn(mcspi->dev, "%s: failed to set pins: %i\n",
1473 __func__, error);
1474
1475 return 0;
1476 }
1477
1478 #else
1479 #define omap2_mcspi_suspend_noirq NULL
1480 #define omap2_mcspi_resume_noirq NULL
1481 #endif
1482
1483 static const struct dev_pm_ops omap2_mcspi_pm_ops = {
1484 .suspend_noirq = omap2_mcspi_suspend_noirq,
1485 .resume_noirq = omap2_mcspi_resume_noirq,
1486 .runtime_resume = omap_mcspi_runtime_resume,
1487 };
1488
1489 static struct platform_driver omap2_mcspi_driver = {
1490 .driver = {
1491 .name = "omap2_mcspi",
1492 .pm = &omap2_mcspi_pm_ops,
1493 .of_match_table = omap_mcspi_of_match,
1494 },
1495 .probe = omap2_mcspi_probe,
1496 .remove = omap2_mcspi_remove,
1497 };
1498
1499 module_platform_driver(omap2_mcspi_driver);
1500 MODULE_LICENSE("GPL");
Linux with added FPC-III support