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dm writecache: fix incorrect flush sequence when doing SSD mode commit
[linux/fpc-iii.git] / arch / arm / mach-davinci / devices-da8xx.c
blob2d69e704f7f6b656bfc55b12da7d5a95f623e386
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DA8XX/OMAP L1XX platform device data
4 *
5 * Copyright (c) 2007-2009, MontaVista Software, Inc. <source@mvista.com>
6 * Derived from code that was:
7 * Copyright (C) 2006 Komal Shah <komal_shah802003@yahoo.com>
8 */
9 #include <linux/ahci_platform.h>
10 #include <linux/clk-provider.h>
11 #include <linux/clk.h>
12 #include <linux/clkdev.h>
13 #include <linux/dma-contiguous.h>
14 #include <linux/dmaengine.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/platform_device.h>
18 #include <linux/reboot.h>
19 #include <linux/serial_8250.h>
20
21 #include <mach/common.h>
22 #include <mach/cputype.h>
23 #include <mach/da8xx.h>
24 #include <mach/time.h>
25
26 #include "asp.h"
27 #include "cpuidle.h"
28 #include "irqs.h"
29 #include "sram.h"
30
31 #define DA8XX_TPCC_BASE 0x01c00000
32 #define DA8XX_TPTC0_BASE 0x01c08000
33 #define DA8XX_TPTC1_BASE 0x01c08400
34 #define DA8XX_WDOG_BASE 0x01c21000 /* DA8XX_TIMER64P1_BASE */
35 #define DA8XX_I2C0_BASE 0x01c22000
36 #define DA8XX_RTC_BASE 0x01c23000
37 #define DA8XX_PRUSS_MEM_BASE 0x01c30000
38 #define DA8XX_MMCSD0_BASE 0x01c40000
39 #define DA8XX_SPI0_BASE 0x01c41000
40 #define DA830_SPI1_BASE 0x01e12000
41 #define DA8XX_LCD_CNTRL_BASE 0x01e13000
42 #define DA850_SATA_BASE 0x01e18000
43 #define DA850_MMCSD1_BASE 0x01e1b000
44 #define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
45 #define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
46 #define DA8XX_EMAC_CPGMAC_BASE 0x01e23000
47 #define DA8XX_EMAC_MDIO_BASE 0x01e24000
48 #define DA8XX_I2C1_BASE 0x01e28000
49 #define DA850_TPCC1_BASE 0x01e30000
50 #define DA850_TPTC2_BASE 0x01e38000
51 #define DA850_SPI1_BASE 0x01f0e000
52 #define DA8XX_DDR2_CTL_BASE 0xb0000000
53
54 #define DA8XX_EMAC_CTRL_REG_OFFSET 0x3000
55 #define DA8XX_EMAC_MOD_REG_OFFSET 0x2000
56 #define DA8XX_EMAC_RAM_OFFSET 0x0000
57 #define DA8XX_EMAC_CTRL_RAM_SIZE SZ_8K
58
59 void __iomem *da8xx_syscfg0_base;
60 void __iomem *da8xx_syscfg1_base;
61
62 static struct plat_serial8250_port da8xx_serial0_pdata[] = {
63 {
64 .mapbase = DA8XX_UART0_BASE,
65 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT0),
66 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
67 UPF_IOREMAP,
68 .iotype = UPIO_MEM,
69 .regshift = 2,
70 },
71 {
72 .flags = 0,
73 }
74 };
75 static struct plat_serial8250_port da8xx_serial1_pdata[] = {
76 {
77 .mapbase = DA8XX_UART1_BASE,
78 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT1),
79 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
80 UPF_IOREMAP,
81 .iotype = UPIO_MEM,
82 .regshift = 2,
83 },
84 {
85 .flags = 0,
86 }
87 };
88 static struct plat_serial8250_port da8xx_serial2_pdata[] = {
89 {
90 .mapbase = DA8XX_UART2_BASE,
91 .irq = DAVINCI_INTC_IRQ(IRQ_DA8XX_UARTINT2),
92 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
93 UPF_IOREMAP,
94 .iotype = UPIO_MEM,
95 .regshift = 2,
96 },
97 {
98 .flags = 0,
99 }
100 };
101
102 struct platform_device da8xx_serial_device[] = {
103 {
104 .name = "serial8250",
105 .id = PLAT8250_DEV_PLATFORM,
106 .dev = {
107 .platform_data = da8xx_serial0_pdata,
108 }
109 },
110 {
111 .name = "serial8250",
112 .id = PLAT8250_DEV_PLATFORM1,
113 .dev = {
114 .platform_data = da8xx_serial1_pdata,
115 }
116 },
117 {
118 .name = "serial8250",
119 .id = PLAT8250_DEV_PLATFORM2,
120 .dev = {
121 .platform_data = da8xx_serial2_pdata,
122 }
123 },
124 {
125 }
126 };
127
128 static s8 da8xx_queue_priority_mapping[][2] = {
129 /* {event queue no, Priority} */
130 {0, 3},
131 {1, 7},
132 {-1, -1}
133 };
134
135 static s8 da850_queue_priority_mapping[][2] = {
136 /* {event queue no, Priority} */
137 {0, 3},
138 {-1, -1}
139 };
140
141 static struct edma_soc_info da8xx_edma0_pdata = {
142 .queue_priority_mapping = da8xx_queue_priority_mapping,
143 .default_queue = EVENTQ_1,
144 };
145
146 static struct edma_soc_info da850_edma1_pdata = {
147 .queue_priority_mapping = da850_queue_priority_mapping,
148 .default_queue = EVENTQ_0,
149 };
150
151 static struct resource da8xx_edma0_resources[] = {
152 {
153 .name = "edma3_cc",
154 .start = DA8XX_TPCC_BASE,
155 .end = DA8XX_TPCC_BASE + SZ_32K - 1,
156 .flags = IORESOURCE_MEM,
157 },
158 {
159 .name = "edma3_tc0",
160 .start = DA8XX_TPTC0_BASE,
161 .end = DA8XX_TPTC0_BASE + SZ_1K - 1,
162 .flags = IORESOURCE_MEM,
163 },
164 {
165 .name = "edma3_tc1",
166 .start = DA8XX_TPTC1_BASE,
167 .end = DA8XX_TPTC1_BASE + SZ_1K - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 {
171 .name = "edma3_ccint",
172 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCINT0),
173 .flags = IORESOURCE_IRQ,
174 },
175 {
176 .name = "edma3_ccerrint",
177 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CCERRINT),
178 .flags = IORESOURCE_IRQ,
179 },
180 };
181
182 static struct resource da850_edma1_resources[] = {
183 {
184 .name = "edma3_cc",
185 .start = DA850_TPCC1_BASE,
186 .end = DA850_TPCC1_BASE + SZ_32K - 1,
187 .flags = IORESOURCE_MEM,
188 },
189 {
190 .name = "edma3_tc0",
191 .start = DA850_TPTC2_BASE,
192 .end = DA850_TPTC2_BASE + SZ_1K - 1,
193 .flags = IORESOURCE_MEM,
194 },
195 {
196 .name = "edma3_ccint",
197 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCINT1),
198 .flags = IORESOURCE_IRQ,
199 },
200 {
201 .name = "edma3_ccerrint",
202 .start = DAVINCI_INTC_IRQ(IRQ_DA850_CCERRINT1),
203 .flags = IORESOURCE_IRQ,
204 },
205 };
206
207 static const struct platform_device_info da8xx_edma0_device __initconst = {
208 .name = "edma",
209 .id = 0,
210 .dma_mask = DMA_BIT_MASK(32),
211 .res = da8xx_edma0_resources,
212 .num_res = ARRAY_SIZE(da8xx_edma0_resources),
213 .data = &da8xx_edma0_pdata,
214 .size_data = sizeof(da8xx_edma0_pdata),
215 };
216
217 static const struct platform_device_info da850_edma1_device __initconst = {
218 .name = "edma",
219 .id = 1,
220 .dma_mask = DMA_BIT_MASK(32),
221 .res = da850_edma1_resources,
222 .num_res = ARRAY_SIZE(da850_edma1_resources),
223 .data = &da850_edma1_pdata,
224 .size_data = sizeof(da850_edma1_pdata),
225 };
226
227 static const struct dma_slave_map da830_edma_map[] = {
228 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
229 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
230 { "davinci-mcasp.1", "rx", EDMA_FILTER_PARAM(0, 2) },
231 { "davinci-mcasp.1", "tx", EDMA_FILTER_PARAM(0, 3) },
232 { "davinci-mcasp.2", "rx", EDMA_FILTER_PARAM(0, 4) },
233 { "davinci-mcasp.2", "tx", EDMA_FILTER_PARAM(0, 5) },
234 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
235 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
236 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
237 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
238 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
239 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
240 };
241
242 int __init da830_register_edma(struct edma_rsv_info *rsv)
243 {
244 struct platform_device *edma_pdev;
245
246 da8xx_edma0_pdata.rsv = rsv;
247
248 da8xx_edma0_pdata.slave_map = da830_edma_map;
249 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da830_edma_map);
250
251 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
252 return PTR_ERR_OR_ZERO(edma_pdev);
253 }
254
255 static const struct dma_slave_map da850_edma0_map[] = {
256 { "davinci-mcasp.0", "rx", EDMA_FILTER_PARAM(0, 0) },
257 { "davinci-mcasp.0", "tx", EDMA_FILTER_PARAM(0, 1) },
258 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 2) },
259 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 3) },
260 { "davinci-mcbsp.1", "rx", EDMA_FILTER_PARAM(0, 4) },
261 { "davinci-mcbsp.1", "tx", EDMA_FILTER_PARAM(0, 5) },
262 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 14) },
263 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 15) },
264 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 16) },
265 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 17) },
266 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 18) },
267 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 19) },
268 };
269
270 static const struct dma_slave_map da850_edma1_map[] = {
271 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(1, 28) },
272 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(1, 29) },
273 };
274
275 int __init da850_register_edma(struct edma_rsv_info *rsv[2])
276 {
277 struct platform_device *edma_pdev;
278
279 if (rsv) {
280 da8xx_edma0_pdata.rsv = rsv[0];
281 da850_edma1_pdata.rsv = rsv[1];
282 }
283
284 da8xx_edma0_pdata.slave_map = da850_edma0_map;
285 da8xx_edma0_pdata.slavecnt = ARRAY_SIZE(da850_edma0_map);
286
287 edma_pdev = platform_device_register_full(&da8xx_edma0_device);
288 if (IS_ERR(edma_pdev)) {
289 pr_warn("%s: Failed to register eDMA0\n", __func__);
290 return PTR_ERR(edma_pdev);
291 }
292
293 da850_edma1_pdata.slave_map = da850_edma1_map;
294 da850_edma1_pdata.slavecnt = ARRAY_SIZE(da850_edma1_map);
295
296 edma_pdev = platform_device_register_full(&da850_edma1_device);
297 return PTR_ERR_OR_ZERO(edma_pdev);
298 }
299
300 static struct resource da8xx_i2c_resources0[] = {
301 {
302 .start = DA8XX_I2C0_BASE,
303 .end = DA8XX_I2C0_BASE + SZ_4K - 1,
304 .flags = IORESOURCE_MEM,
305 },
306 {
307 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
308 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT0),
309 .flags = IORESOURCE_IRQ,
310 },
311 };
312
313 static struct platform_device da8xx_i2c_device0 = {
314 .name = "i2c_davinci",
315 .id = 1,
316 .num_resources = ARRAY_SIZE(da8xx_i2c_resources0),
317 .resource = da8xx_i2c_resources0,
318 };
319
320 static struct resource da8xx_i2c_resources1[] = {
321 {
322 .start = DA8XX_I2C1_BASE,
323 .end = DA8XX_I2C1_BASE + SZ_4K - 1,
324 .flags = IORESOURCE_MEM,
325 },
326 {
327 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
328 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_I2CINT1),
329 .flags = IORESOURCE_IRQ,
330 },
331 };
332
333 static struct platform_device da8xx_i2c_device1 = {
334 .name = "i2c_davinci",
335 .id = 2,
336 .num_resources = ARRAY_SIZE(da8xx_i2c_resources1),
337 .resource = da8xx_i2c_resources1,
338 };
339
340 int __init da8xx_register_i2c(int instance,
341 struct davinci_i2c_platform_data *pdata)
342 {
343 struct platform_device *pdev;
344
345 if (instance == 0)
346 pdev = &da8xx_i2c_device0;
347 else if (instance == 1)
348 pdev = &da8xx_i2c_device1;
349 else
350 return -EINVAL;
351
352 pdev->dev.platform_data = pdata;
353 return platform_device_register(pdev);
354 }
355
356 static struct resource da8xx_watchdog_resources[] = {
357 {
358 .start = DA8XX_WDOG_BASE,
359 .end = DA8XX_WDOG_BASE + SZ_4K - 1,
360 .flags = IORESOURCE_MEM,
361 },
362 };
363
364 static struct platform_device da8xx_wdt_device = {
365 .name = "davinci-wdt",
366 .id = -1,
367 .num_resources = ARRAY_SIZE(da8xx_watchdog_resources),
368 .resource = da8xx_watchdog_resources,
369 };
370
371 int __init da8xx_register_watchdog(void)
372 {
373 return platform_device_register(&da8xx_wdt_device);
374 }
375
376 static struct resource da8xx_emac_resources[] = {
377 {
378 .start = DA8XX_EMAC_CPPI_PORT_BASE,
379 .end = DA8XX_EMAC_CPPI_PORT_BASE + SZ_16K - 1,
380 .flags = IORESOURCE_MEM,
381 },
382 {
383 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
384 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_THRESH_PULSE),
385 .flags = IORESOURCE_IRQ,
386 },
387 {
388 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
389 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_RX_PULSE),
390 .flags = IORESOURCE_IRQ,
391 },
392 {
393 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
394 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_TX_PULSE),
395 .flags = IORESOURCE_IRQ,
396 },
397 {
398 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
399 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_C0_MISC_PULSE),
400 .flags = IORESOURCE_IRQ,
401 },
402 };
403
404 struct emac_platform_data da8xx_emac_pdata = {
405 .ctrl_reg_offset = DA8XX_EMAC_CTRL_REG_OFFSET,
406 .ctrl_mod_reg_offset = DA8XX_EMAC_MOD_REG_OFFSET,
407 .ctrl_ram_offset = DA8XX_EMAC_RAM_OFFSET,
408 .ctrl_ram_size = DA8XX_EMAC_CTRL_RAM_SIZE,
409 .version = EMAC_VERSION_2,
410 };
411
412 static struct platform_device da8xx_emac_device = {
413 .name = "davinci_emac",
414 .id = 1,
415 .dev = {
416 .platform_data = &da8xx_emac_pdata,
417 },
418 .num_resources = ARRAY_SIZE(da8xx_emac_resources),
419 .resource = da8xx_emac_resources,
420 };
421
422 static struct resource da8xx_mdio_resources[] = {
423 {
424 .start = DA8XX_EMAC_MDIO_BASE,
425 .end = DA8XX_EMAC_MDIO_BASE + SZ_4K - 1,
426 .flags = IORESOURCE_MEM,
427 },
428 };
429
430 static struct platform_device da8xx_mdio_device = {
431 .name = "davinci_mdio",
432 .id = 0,
433 .num_resources = ARRAY_SIZE(da8xx_mdio_resources),
434 .resource = da8xx_mdio_resources,
435 };
436
437 int __init da8xx_register_emac(void)
438 {
439 int ret;
440
441 ret = platform_device_register(&da8xx_mdio_device);
442 if (ret < 0)
443 return ret;
444
445 return platform_device_register(&da8xx_emac_device);
446 }
447
448 static struct resource da830_mcasp1_resources[] = {
449 {
450 .name = "mpu",
451 .start = DAVINCI_DA830_MCASP1_REG_BASE,
452 .end = DAVINCI_DA830_MCASP1_REG_BASE + (SZ_1K * 12) - 1,
453 .flags = IORESOURCE_MEM,
454 },
455 /* TX event */
456 {
457 .name = "tx",
458 .start = DAVINCI_DA830_DMA_MCASP1_AXEVT,
459 .end = DAVINCI_DA830_DMA_MCASP1_AXEVT,
460 .flags = IORESOURCE_DMA,
461 },
462 /* RX event */
463 {
464 .name = "rx",
465 .start = DAVINCI_DA830_DMA_MCASP1_AREVT,
466 .end = DAVINCI_DA830_DMA_MCASP1_AREVT,
467 .flags = IORESOURCE_DMA,
468 },
469 {
470 .name = "common",
471 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
472 .flags = IORESOURCE_IRQ,
473 },
474 };
475
476 static struct platform_device da830_mcasp1_device = {
477 .name = "davinci-mcasp",
478 .id = 1,
479 .num_resources = ARRAY_SIZE(da830_mcasp1_resources),
480 .resource = da830_mcasp1_resources,
481 };
482
483 static struct resource da830_mcasp2_resources[] = {
484 {
485 .name = "mpu",
486 .start = DAVINCI_DA830_MCASP2_REG_BASE,
487 .end = DAVINCI_DA830_MCASP2_REG_BASE + (SZ_1K * 12) - 1,
488 .flags = IORESOURCE_MEM,
489 },
490 /* TX event */
491 {
492 .name = "tx",
493 .start = DAVINCI_DA830_DMA_MCASP2_AXEVT,
494 .end = DAVINCI_DA830_DMA_MCASP2_AXEVT,
495 .flags = IORESOURCE_DMA,
496 },
497 /* RX event */
498 {
499 .name = "rx",
500 .start = DAVINCI_DA830_DMA_MCASP2_AREVT,
501 .end = DAVINCI_DA830_DMA_MCASP2_AREVT,
502 .flags = IORESOURCE_DMA,
503 },
504 {
505 .name = "common",
506 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
507 .flags = IORESOURCE_IRQ,
508 },
509 };
510
511 static struct platform_device da830_mcasp2_device = {
512 .name = "davinci-mcasp",
513 .id = 2,
514 .num_resources = ARRAY_SIZE(da830_mcasp2_resources),
515 .resource = da830_mcasp2_resources,
516 };
517
518 static struct resource da850_mcasp_resources[] = {
519 {
520 .name = "mpu",
521 .start = DAVINCI_DA8XX_MCASP0_REG_BASE,
522 .end = DAVINCI_DA8XX_MCASP0_REG_BASE + (SZ_1K * 12) - 1,
523 .flags = IORESOURCE_MEM,
524 },
525 /* TX event */
526 {
527 .name = "tx",
528 .start = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
529 .end = DAVINCI_DA8XX_DMA_MCASP0_AXEVT,
530 .flags = IORESOURCE_DMA,
531 },
532 /* RX event */
533 {
534 .name = "rx",
535 .start = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
536 .end = DAVINCI_DA8XX_DMA_MCASP0_AREVT,
537 .flags = IORESOURCE_DMA,
538 },
539 {
540 .name = "common",
541 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MCASPINT),
542 .flags = IORESOURCE_IRQ,
543 },
544 };
545
546 static struct platform_device da850_mcasp_device = {
547 .name = "davinci-mcasp",
548 .id = 0,
549 .num_resources = ARRAY_SIZE(da850_mcasp_resources),
550 .resource = da850_mcasp_resources,
551 };
552
553 void __init da8xx_register_mcasp(int id, struct snd_platform_data *pdata)
554 {
555 struct platform_device *pdev;
556
557 switch (id) {
558 case 0:
559 /* Valid for DA830/OMAP-L137 or DA850/OMAP-L138 */
560 pdev = &da850_mcasp_device;
561 break;
562 case 1:
563 /* Valid for DA830/OMAP-L137 only */
564 if (!cpu_is_davinci_da830())
565 return;
566 pdev = &da830_mcasp1_device;
567 break;
568 case 2:
569 /* Valid for DA830/OMAP-L137 only */
570 if (!cpu_is_davinci_da830())
571 return;
572 pdev = &da830_mcasp2_device;
573 break;
574 default:
575 return;
576 }
577
578 pdev->dev.platform_data = pdata;
579 platform_device_register(pdev);
580 }
581
582 static struct resource da8xx_pruss_resources[] = {
583 {
584 .start = DA8XX_PRUSS_MEM_BASE,
585 .end = DA8XX_PRUSS_MEM_BASE + 0xFFFF,
586 .flags = IORESOURCE_MEM,
587 },
588 {
589 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
590 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT0),
591 .flags = IORESOURCE_IRQ,
592 },
593 {
594 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
595 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT1),
596 .flags = IORESOURCE_IRQ,
597 },
598 {
599 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
600 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT2),
601 .flags = IORESOURCE_IRQ,
602 },
603 {
604 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
605 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT3),
606 .flags = IORESOURCE_IRQ,
607 },
608 {
609 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
610 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT4),
611 .flags = IORESOURCE_IRQ,
612 },
613 {
614 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
615 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT5),
616 .flags = IORESOURCE_IRQ,
617 },
618 {
619 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
620 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT6),
621 .flags = IORESOURCE_IRQ,
622 },
623 {
624 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
625 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_EVTOUT7),
626 .flags = IORESOURCE_IRQ,
627 },
628 };
629
630 static struct uio_pruss_pdata da8xx_uio_pruss_pdata = {
631 .pintc_base = 0x4000,
632 };
633
634 static struct platform_device da8xx_uio_pruss_dev = {
635 .name = "pruss_uio",
636 .id = -1,
637 .num_resources = ARRAY_SIZE(da8xx_pruss_resources),
638 .resource = da8xx_pruss_resources,
639 .dev = {
640 .coherent_dma_mask = DMA_BIT_MASK(32),
641 .platform_data = &da8xx_uio_pruss_pdata,
642 }
643 };
644
645 int __init da8xx_register_uio_pruss(void)
646 {
647 da8xx_uio_pruss_pdata.sram_pool = sram_get_gen_pool();
648 return platform_device_register(&da8xx_uio_pruss_dev);
649 }
650
651 static struct lcd_ctrl_config lcd_cfg = {
652 .panel_shade = COLOR_ACTIVE,
653 .bpp = 16,
654 };
655
656 struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata = {
657 .manu_name = "sharp",
658 .controller_data = &lcd_cfg,
659 .type = "Sharp_LCD035Q3DG01",
660 };
661
662 struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata = {
663 .manu_name = "sharp",
664 .controller_data = &lcd_cfg,
665 .type = "Sharp_LK043T1DG01",
666 };
667
668 static struct resource da8xx_lcdc_resources[] = {
669 [0] = { /* registers */
670 .start = DA8XX_LCD_CNTRL_BASE,
671 .end = DA8XX_LCD_CNTRL_BASE + SZ_4K - 1,
672 .flags = IORESOURCE_MEM,
673 },
674 [1] = { /* interrupt */
675 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
676 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_LCDINT),
677 .flags = IORESOURCE_IRQ,
678 },
679 };
680
681 static struct platform_device da8xx_lcdc_device = {
682 .name = "da8xx_lcdc",
683 .id = 0,
684 .num_resources = ARRAY_SIZE(da8xx_lcdc_resources),
685 .resource = da8xx_lcdc_resources,
686 .dev = {
687 .coherent_dma_mask = DMA_BIT_MASK(32),
688 }
689 };
690
691 int __init da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata)
692 {
693 da8xx_lcdc_device.dev.platform_data = pdata;
694 return platform_device_register(&da8xx_lcdc_device);
695 }
696
697 static struct resource da8xx_gpio_resources[] = {
698 { /* registers */
699 .start = DA8XX_GPIO_BASE,
700 .end = DA8XX_GPIO_BASE + SZ_4K - 1,
701 .flags = IORESOURCE_MEM,
702 },
703 { /* interrupt */
704 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
705 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO0),
706 .flags = IORESOURCE_IRQ,
707 },
708 {
709 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
710 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO1),
711 .flags = IORESOURCE_IRQ,
712 },
713 {
714 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
715 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO2),
716 .flags = IORESOURCE_IRQ,
717 },
718 {
719 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
720 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO3),
721 .flags = IORESOURCE_IRQ,
722 },
723 {
724 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
725 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO4),
726 .flags = IORESOURCE_IRQ,
727 },
728 {
729 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
730 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO5),
731 .flags = IORESOURCE_IRQ,
732 },
733 {
734 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
735 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO6),
736 .flags = IORESOURCE_IRQ,
737 },
738 {
739 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
740 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO7),
741 .flags = IORESOURCE_IRQ,
742 },
743 {
744 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
745 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_GPIO8),
746 .flags = IORESOURCE_IRQ,
747 },
748 };
749
750 static struct platform_device da8xx_gpio_device = {
751 .name = "davinci_gpio",
752 .id = -1,
753 .num_resources = ARRAY_SIZE(da8xx_gpio_resources),
754 .resource = da8xx_gpio_resources,
755 };
756
757 int __init da8xx_register_gpio(void *pdata)
758 {
759 da8xx_gpio_device.dev.platform_data = pdata;
760 return platform_device_register(&da8xx_gpio_device);
761 }
762
763 static struct resource da8xx_mmcsd0_resources[] = {
764 { /* registers */
765 .start = DA8XX_MMCSD0_BASE,
766 .end = DA8XX_MMCSD0_BASE + SZ_4K - 1,
767 .flags = IORESOURCE_MEM,
768 },
769 { /* interrupt */
770 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
771 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_MMCSDINT0),
772 .flags = IORESOURCE_IRQ,
773 },
774 };
775
776 static struct platform_device da8xx_mmcsd0_device = {
777 .name = "da830-mmc",
778 .id = 0,
779 .num_resources = ARRAY_SIZE(da8xx_mmcsd0_resources),
780 .resource = da8xx_mmcsd0_resources,
781 };
782
783 int __init da8xx_register_mmcsd0(struct davinci_mmc_config *config)
784 {
785 da8xx_mmcsd0_device.dev.platform_data = config;
786 return platform_device_register(&da8xx_mmcsd0_device);
787 }
788
789 #ifdef CONFIG_ARCH_DAVINCI_DA850
790 static struct resource da850_mmcsd1_resources[] = {
791 { /* registers */
792 .start = DA850_MMCSD1_BASE,
793 .end = DA850_MMCSD1_BASE + SZ_4K - 1,
794 .flags = IORESOURCE_MEM,
795 },
796 { /* interrupt */
797 .start = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
798 .end = DAVINCI_INTC_IRQ(IRQ_DA850_MMCSDINT0_1),
799 .flags = IORESOURCE_IRQ,
800 },
801 };
802
803 static struct platform_device da850_mmcsd1_device = {
804 .name = "da830-mmc",
805 .id = 1,
806 .num_resources = ARRAY_SIZE(da850_mmcsd1_resources),
807 .resource = da850_mmcsd1_resources,
808 };
809
810 int __init da850_register_mmcsd1(struct davinci_mmc_config *config)
811 {
812 da850_mmcsd1_device.dev.platform_data = config;
813 return platform_device_register(&da850_mmcsd1_device);
814 }
815 #endif
816
817 static struct resource da8xx_rproc_resources[] = {
818 { /* DSP boot address */
819 .name = "host1cfg",
820 .start = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG,
821 .end = DA8XX_SYSCFG0_BASE + DA8XX_HOST1CFG_REG + 3,
822 .flags = IORESOURCE_MEM,
823 },
824 { /* DSP interrupt registers */
825 .name = "chipsig",
826 .start = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG,
827 .end = DA8XX_SYSCFG0_BASE + DA8XX_CHIPSIG_REG + 7,
828 .flags = IORESOURCE_MEM,
829 },
830 { /* DSP L2 RAM */
831 .name = "l2sram",
832 .start = DA8XX_DSP_L2_RAM_BASE,
833 .end = DA8XX_DSP_L2_RAM_BASE + SZ_256K - 1,
834 .flags = IORESOURCE_MEM,
835 },
836 { /* DSP L1P RAM */
837 .name = "l1pram",
838 .start = DA8XX_DSP_L1P_RAM_BASE,
839 .end = DA8XX_DSP_L1P_RAM_BASE + SZ_32K - 1,
840 .flags = IORESOURCE_MEM,
841 },
842 { /* DSP L1D RAM */
843 .name = "l1dram",
844 .start = DA8XX_DSP_L1D_RAM_BASE,
845 .end = DA8XX_DSP_L1D_RAM_BASE + SZ_32K - 1,
846 .flags = IORESOURCE_MEM,
847 },
848 { /* dsp irq */
849 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
850 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_CHIPINT0),
851 .flags = IORESOURCE_IRQ,
852 },
853 };
854
855 static struct platform_device da8xx_dsp = {
856 .name = "davinci-rproc",
857 .dev = {
858 .coherent_dma_mask = DMA_BIT_MASK(32),
859 },
860 .num_resources = ARRAY_SIZE(da8xx_rproc_resources),
861 .resource = da8xx_rproc_resources,
862 };
863
864 static bool rproc_mem_inited __initdata;
865
866 #if IS_ENABLED(CONFIG_DA8XX_REMOTEPROC)
867
868 static phys_addr_t rproc_base __initdata;
869 static unsigned long rproc_size __initdata;
870
871 static int __init early_rproc_mem(char *p)
872 {
873 char *endp;
874
875 if (p == NULL)
876 return 0;
877
878 rproc_size = memparse(p, &endp);
879 if (*endp == '@')
880 rproc_base = memparse(endp + 1, NULL);
881
882 return 0;
883 }
884 early_param("rproc_mem", early_rproc_mem);
885
886 void __init da8xx_rproc_reserve_cma(void)
887 {
888 int ret;
889
890 if (!rproc_base || !rproc_size) {
891 pr_err("%s: 'rproc_mem=nn@address' badly specified\n"
892 " 'nn' and 'address' must both be non-zero\n",
893 __func__);
894
895 return;
896 }
897
898 pr_info("%s: reserving 0x%lx @ 0x%lx...\n",
899 __func__, rproc_size, (unsigned long)rproc_base);
900
901 ret = dma_declare_contiguous(&da8xx_dsp.dev, rproc_size, rproc_base, 0);
902 if (ret)
903 pr_err("%s: dma_declare_contiguous failed %d\n", __func__, ret);
904 else
905 rproc_mem_inited = true;
906 }
907
908 #else
909
910 void __init da8xx_rproc_reserve_cma(void)
911 {
912 }
913
914 #endif
915
916 int __init da8xx_register_rproc(void)
917 {
918 int ret;
919
920 if (!rproc_mem_inited) {
921 pr_warn("%s: memory not reserved for DSP, not registering DSP device\n",
922 __func__);
923 return -ENOMEM;
924 }
925
926 ret = platform_device_register(&da8xx_dsp);
927 if (ret)
928 pr_err("%s: can't register DSP device: %d\n", __func__, ret);
929
930 return ret;
931 };
932
933 static struct resource da8xx_rtc_resources[] = {
934 {
935 .start = DA8XX_RTC_BASE,
936 .end = DA8XX_RTC_BASE + SZ_4K - 1,
937 .flags = IORESOURCE_MEM,
938 },
939 { /* timer irq */
940 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
941 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
942 .flags = IORESOURCE_IRQ,
943 },
944 { /* alarm irq */
945 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
946 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_RTC),
947 .flags = IORESOURCE_IRQ,
948 },
949 };
950
951 static struct platform_device da8xx_rtc_device = {
952 .name = "da830-rtc",
953 .id = -1,
954 .num_resources = ARRAY_SIZE(da8xx_rtc_resources),
955 .resource = da8xx_rtc_resources,
956 };
957
958 int da8xx_register_rtc(void)
959 {
960 return platform_device_register(&da8xx_rtc_device);
961 }
962
963 static void __iomem *da8xx_ddr2_ctlr_base;
964 void __iomem * __init da8xx_get_mem_ctlr(void)
965 {
966 if (da8xx_ddr2_ctlr_base)
967 return da8xx_ddr2_ctlr_base;
968
969 da8xx_ddr2_ctlr_base = ioremap(DA8XX_DDR2_CTL_BASE, SZ_32K);
970 if (!da8xx_ddr2_ctlr_base)
971 pr_warn("%s: Unable to map DDR2 controller", __func__);
972
973 return da8xx_ddr2_ctlr_base;
974 }
975
976 static struct resource da8xx_cpuidle_resources[] = {
977 {
978 .start = DA8XX_DDR2_CTL_BASE,
979 .end = DA8XX_DDR2_CTL_BASE + SZ_32K - 1,
980 .flags = IORESOURCE_MEM,
981 },
982 };
983
984 /* DA8XX devices support DDR2 power down */
985 static struct davinci_cpuidle_config da8xx_cpuidle_pdata = {
986 .ddr2_pdown = 1,
987 };
988
989
990 static struct platform_device da8xx_cpuidle_device = {
991 .name = "cpuidle-davinci",
992 .num_resources = ARRAY_SIZE(da8xx_cpuidle_resources),
993 .resource = da8xx_cpuidle_resources,
994 .dev = {
995 .platform_data = &da8xx_cpuidle_pdata,
996 },
997 };
998
999 int __init da8xx_register_cpuidle(void)
1000 {
1001 da8xx_cpuidle_pdata.ddr2_ctlr_base = da8xx_get_mem_ctlr();
1002
1003 return platform_device_register(&da8xx_cpuidle_device);
1004 }
1005
1006 static struct resource da8xx_spi0_resources[] = {
1007 [0] = {
1008 .start = DA8XX_SPI0_BASE,
1009 .end = DA8XX_SPI0_BASE + SZ_4K - 1,
1010 .flags = IORESOURCE_MEM,
1011 },
1012 [1] = {
1013 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1014 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT0),
1015 .flags = IORESOURCE_IRQ,
1016 },
1017 };
1018
1019 static struct resource da8xx_spi1_resources[] = {
1020 [0] = {
1021 .start = DA830_SPI1_BASE,
1022 .end = DA830_SPI1_BASE + SZ_4K - 1,
1023 .flags = IORESOURCE_MEM,
1024 },
1025 [1] = {
1026 .start = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1027 .end = DAVINCI_INTC_IRQ(IRQ_DA8XX_SPINT1),
1028 .flags = IORESOURCE_IRQ,
1029 },
1030 };
1031
1032 static struct davinci_spi_platform_data da8xx_spi_pdata[] = {
1033 [0] = {
1034 .version = SPI_VERSION_2,
1035 .intr_line = 1,
1036 .dma_event_q = EVENTQ_0,
1037 .prescaler_limit = 2,
1038 },
1039 [1] = {
1040 .version = SPI_VERSION_2,
1041 .intr_line = 1,
1042 .dma_event_q = EVENTQ_0,
1043 .prescaler_limit = 2,
1044 },
1045 };
1046
1047 static struct platform_device da8xx_spi_device[] = {
1048 [0] = {
1049 .name = "spi_davinci",
1050 .id = 0,
1051 .num_resources = ARRAY_SIZE(da8xx_spi0_resources),
1052 .resource = da8xx_spi0_resources,
1053 .dev = {
1054 .platform_data = &da8xx_spi_pdata[0],
1055 },
1056 },
1057 [1] = {
1058 .name = "spi_davinci",
1059 .id = 1,
1060 .num_resources = ARRAY_SIZE(da8xx_spi1_resources),
1061 .resource = da8xx_spi1_resources,
1062 .dev = {
1063 .platform_data = &da8xx_spi_pdata[1],
1064 },
1065 },
1066 };
1067
1068 int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
1069 {
1070 if (instance < 0 || instance > 1)
1071 return -EINVAL;
1072
1073 da8xx_spi_pdata[instance].num_chipselect = num_chipselect;
1074
1075 if (instance == 1 && cpu_is_davinci_da850()) {
1076 da8xx_spi1_resources[0].start = DA850_SPI1_BASE;
1077 da8xx_spi1_resources[0].end = DA850_SPI1_BASE + SZ_4K - 1;
1078 }
1079
1080 return platform_device_register(&da8xx_spi_device[instance]);
1081 }
1082
1083 #ifdef CONFIG_ARCH_DAVINCI_DA850
1084 int __init da850_register_sata_refclk(int rate)
1085 {
1086 struct clk *clk;
1087
1088 clk = clk_register_fixed_rate(NULL, "sata_refclk", NULL, 0, rate);
1089 if (IS_ERR(clk))
1090 return PTR_ERR(clk);
1091
1092 return clk_register_clkdev(clk, "refclk", "ahci_da850");
1093 }
1094
1095 static struct resource da850_sata_resources[] = {
1096 {
1097 .start = DA850_SATA_BASE,
1098 .end = DA850_SATA_BASE + 0x1fff,
1099 .flags = IORESOURCE_MEM,
1100 },
1101 {
1102 .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
1103 .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
1104 .flags = IORESOURCE_MEM,
1105 },
1106 {
1107 .start = DAVINCI_INTC_IRQ(IRQ_DA850_SATAINT),
1108 .flags = IORESOURCE_IRQ,
1109 },
1110 };
1111
1112 static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
1113
1114 static struct platform_device da850_sata_device = {
1115 .name = "ahci_da850",
1116 .id = -1,
1117 .dev = {
1118 .dma_mask = &da850_sata_dmamask,
1119 .coherent_dma_mask = DMA_BIT_MASK(32),
1120 },
1121 .num_resources = ARRAY_SIZE(da850_sata_resources),
1122 .resource = da850_sata_resources,
1123 };
1124
1125 int __init da850_register_sata(unsigned long refclkpn)
1126 {
1127 int ret;
1128
1129 ret = da850_register_sata_refclk(refclkpn);
1130 if (ret)
1131 return ret;
1132
1133 return platform_device_register(&da850_sata_device);
1134 }
1135 #endif
1136
1137 static struct regmap *da8xx_cfgchip;
1138
1139 static const struct regmap_config da8xx_cfgchip_config __initconst = {
1140 .name = "cfgchip",
1141 .reg_bits = 32,
1142 .val_bits = 32,
1143 .reg_stride = 4,
1144 .max_register = DA8XX_CFGCHIP4_REG - DA8XX_CFGCHIP0_REG,
1145 };
1146
1147 /**
1148 * da8xx_get_cfgchip - Lazy gets CFGCHIP as regmap
1149 *
1150 * This is for use on non-DT boards only. For DT boards, use
1151 * syscon_regmap_lookup_by_compatible("ti,da830-cfgchip")
1152 *
1153 * Returns: Pointer to the CFGCHIP regmap or negative error code.
1154 */
1155 struct regmap * __init da8xx_get_cfgchip(void)
1156 {
1157 if (IS_ERR_OR_NULL(da8xx_cfgchip))
1158 da8xx_cfgchip = regmap_init_mmio(NULL,
1159 DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG),
1160 &da8xx_cfgchip_config);
1161
1162 return da8xx_cfgchip;
1163 }
Linux with added FPC-III support