arch/arm/mach-ixp4xx/goramo_mlr.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Goramo MultiLink router platform code
   4  * Copyright (C) 2006-2009 Krzysztof Halasa <khc@pm.waw.pl>
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/gpio.h>
   9 #include <linux/hdlc.h>
  10 #include <linux/io.h>
  11 #include <linux/irq.h>
  12 #include <linux/kernel.h>
  13 #include <linux/pci.h>
  14 #include <linux/serial_8250.h>
  15 #include <asm/mach-types.h>
  16 #include <asm/mach/arch.h>
  17 #include <asm/mach/flash.h>
  18 #include <asm/mach/pci.h>
  19 #include <asm/system_info.h>
  20
  21 #include "irqs.h"
  22
  23 #define SLOT_ETHA               0x0B    /* IDSEL = AD21 */
  24 #define SLOT_ETHB               0x0C    /* IDSEL = AD20 */
  25 #define SLOT_MPCI               0x0D    /* IDSEL = AD19 */
  26 #define SLOT_NEC                0x0E    /* IDSEL = AD18 */
  27
  28 /* GPIO lines */
  29 #define GPIO_SCL                0
  30 #define GPIO_SDA                1
  31 #define GPIO_STR                2
  32 #define GPIO_IRQ_NEC            3
  33 #define GPIO_IRQ_ETHA           4
  34 #define GPIO_IRQ_ETHB           5
  35 #define GPIO_HSS0_DCD_N         6
  36 #define GPIO_HSS1_DCD_N         7
  37 #define GPIO_UART0_DCD          8
  38 #define GPIO_UART1_DCD          9
  39 #define GPIO_HSS0_CTS_N         10
  40 #define GPIO_HSS1_CTS_N         11
  41 #define GPIO_IRQ_MPCI           12
  42 #define GPIO_HSS1_RTS_N         13
  43 #define GPIO_HSS0_RTS_N         14
  44 /* GPIO15 is not connected */
  45
  46 /* Control outputs from 74HC4094 */
  47 #define CONTROL_HSS0_CLK_INT    0
  48 #define CONTROL_HSS1_CLK_INT    1
  49 #define CONTROL_HSS0_DTR_N      2
  50 #define CONTROL_HSS1_DTR_N      3
  51 #define CONTROL_EXT             4
  52 #define CONTROL_AUTO_RESET      5
  53 #define CONTROL_PCI_RESET_N     6
  54 #define CONTROL_EEPROM_WC_N     7
  55
  56 /* offsets from start of flash ROM = 0x50000000 */
  57 #define CFG_ETH0_ADDRESS        0x40 /* 6 bytes */
  58 #define CFG_ETH1_ADDRESS        0x46 /* 6 bytes */
  59 #define CFG_REV                 0x4C /* u32 */
  60 #define CFG_SDRAM_SIZE          0x50 /* u32 */
  61 #define CFG_SDRAM_CONF          0x54 /* u32 */
  62 #define CFG_SDRAM_MODE          0x58 /* u32 */
  63 #define CFG_SDRAM_REFRESH       0x5C /* u32 */
  64
  65 #define CFG_HW_BITS             0x60 /* u32 */
  66 #define  CFG_HW_USB_PORTS       0x00000007 /* 0 = no NEC chip, 1-5 = ports # */
  67 #define  CFG_HW_HAS_PCI_SLOT    0x00000008
  68 #define  CFG_HW_HAS_ETH0        0x00000010
  69 #define  CFG_HW_HAS_ETH1        0x00000020
  70 #define  CFG_HW_HAS_HSS0        0x00000040
  71 #define  CFG_HW_HAS_HSS1        0x00000080
  72 #define  CFG_HW_HAS_UART0       0x00000100
  73 #define  CFG_HW_HAS_UART1       0x00000200
  74 #define  CFG_HW_HAS_EEPROM      0x00000400
  75
  76 #define FLASH_CMD_READ_ARRAY    0xFF
  77 #define FLASH_CMD_READ_ID       0x90
  78 #define FLASH_SER_OFF           0x102 /* 0x81 in 16-bit mode */
  79
  80 static u32 hw_bits = 0xFFFFFFFD;    /* assume all hardware present */;
  81 static u8 control_value;
  82
  83 /*
  84  * FIXME: this is reimplementing I2C bit-bangining. Move this
  85  * over to using driver/i2c/busses/i2c-gpio.c like all other boards
  86  * and register proper I2C device(s) on the bus for this. (See
  87  * other IXP4xx boards for examples.)
  88  */
  89 static void set_scl(u8 value)
  90 {
  91         gpio_set_value(GPIO_SCL, !!value);
  92         udelay(3);
  93 }
  94
  95 static void set_sda(u8 value)
  96 {
  97         gpio_set_value(GPIO_SDA, !!value);
  98         udelay(3);
  99 }
 100
 101 static void set_str(u8 value)
 102 {
 103         gpio_set_value(GPIO_STR, !!value);
 104         udelay(3);
 105 }
 106
 107 static inline void set_control(int line, int value)
 108 {
 109         if (value)
 110                 control_value |=  (1 << line);
 111         else
 112                 control_value &= ~(1 << line);
 113 }
 114
 115
 116 static void output_control(void)
 117 {
 118         int i;
 119
 120         gpio_direction_output(GPIO_SCL, 1);
 121         gpio_direction_output(GPIO_SDA, 1);
 122
 123         for (i = 0; i < 8; i++) {
 124                 set_scl(0);
 125                 set_sda(control_value & (0x80 >> i)); /* MSB first */
 126                 set_scl(1);     /* active edge */
 127         }
 128
 129         set_str(1);
 130         set_str(0);
 131
 132         set_scl(0);
 133         set_sda(1);             /* Be ready for START */
 134         set_scl(1);
 135 }
 136
 137
 138 static void (*set_carrier_cb_tab[2])(void *pdev, int carrier);
 139
 140 static int hss_set_clock(int port, unsigned int clock_type)
 141 {
 142         int ctrl_int = port ? CONTROL_HSS1_CLK_INT : CONTROL_HSS0_CLK_INT;
 143
 144         switch (clock_type) {
 145         case CLOCK_DEFAULT:
 146         case CLOCK_EXT:
 147                 set_control(ctrl_int, 0);
 148                 output_control();
 149                 return CLOCK_EXT;
 150
 151         case CLOCK_INT:
 152                 set_control(ctrl_int, 1);
 153                 output_control();
 154                 return CLOCK_INT;
 155
 156         default:
 157                 return -EINVAL;
 158         }
 159 }
 160
 161 static irqreturn_t hss_dcd_irq(int irq, void *pdev)
 162 {
 163         int port = (irq == IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N));
 164         int i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
 165         set_carrier_cb_tab[port](pdev, !i);
 166         return IRQ_HANDLED;
 167 }
 168
 169
 170 static int hss_open(int port, void *pdev,
 171                     void (*set_carrier_cb)(void *pdev, int carrier))
 172 {
 173         int i, irq;
 174
 175         if (!port)
 176                 irq = IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N);
 177         else
 178                 irq = IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N);
 179
 180         i = gpio_get_value(port ? GPIO_HSS1_DCD_N : GPIO_HSS0_DCD_N);
 181         set_carrier_cb(pdev, !i);
 182
 183         set_carrier_cb_tab[!!port] = set_carrier_cb;
 184
 185         if ((i = request_irq(irq, hss_dcd_irq, 0, "IXP4xx HSS", pdev)) != 0) {
 186                 printk(KERN_ERR "ixp4xx_hss: failed to request IRQ%i (%i)\n",
 187                        irq, i);
 188                 return i;
 189         }
 190
 191         set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 0);
 192         output_control();
 193         gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 0);
 194         return 0;
 195 }
 196
 197 static void hss_close(int port, void *pdev)
 198 {
 199         free_irq(port ? IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N) :
 200                  IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), pdev);
 201         set_carrier_cb_tab[!!port] = NULL; /* catch bugs */
 202
 203         set_control(port ? CONTROL_HSS1_DTR_N : CONTROL_HSS0_DTR_N, 1);
 204         output_control();
 205         gpio_set_value(port ? GPIO_HSS1_RTS_N : GPIO_HSS0_RTS_N, 1);
 206 }
 207
 208
 209 /* Flash memory */
 210 static struct flash_platform_data flash_data = {
 211         .map_name       = "cfi_probe",
 212         .width          = 2,
 213 };
 214
 215 static struct resource flash_resource = {
 216         .flags          = IORESOURCE_MEM,
 217 };
 218
 219 static struct platform_device device_flash = {
 220         .name           = "IXP4XX-Flash",
 221         .id             = 0,
 222         .dev            = { .platform_data = &flash_data },
 223         .num_resources  = 1,
 224         .resource       = &flash_resource,
 225 };
 226
 227 /* IXP425 2 UART ports */
 228 static struct resource uart_resources[] = {
 229         {
 230                 .start          = IXP4XX_UART1_BASE_PHYS,
 231                 .end            = IXP4XX_UART1_BASE_PHYS + 0x0fff,
 232                 .flags          = IORESOURCE_MEM,
 233         },
 234         {
 235                 .start          = IXP4XX_UART2_BASE_PHYS,
 236                 .end            = IXP4XX_UART2_BASE_PHYS + 0x0fff,
 237                 .flags          = IORESOURCE_MEM,
 238         }
 239 };
 240
 241 static struct plat_serial8250_port uart_data[] = {
 242         {
 243                 .mapbase        = IXP4XX_UART1_BASE_PHYS,
 244                 .membase        = (char __iomem *)IXP4XX_UART1_BASE_VIRT +
 245                         REG_OFFSET,
 246                 .irq            = IRQ_IXP4XX_UART1,
 247                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 248                 .iotype         = UPIO_MEM,
 249                 .regshift       = 2,
 250                 .uartclk        = IXP4XX_UART_XTAL,
 251         },
 252         {
 253                 .mapbase        = IXP4XX_UART2_BASE_PHYS,
 254                 .membase        = (char __iomem *)IXP4XX_UART2_BASE_VIRT +
 255                         REG_OFFSET,
 256                 .irq            = IRQ_IXP4XX_UART2,
 257                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
 258                 .iotype         = UPIO_MEM,
 259                 .regshift       = 2,
 260                 .uartclk        = IXP4XX_UART_XTAL,
 261         },
 262         { },
 263 };
 264
 265 static struct platform_device device_uarts = {
 266         .name                   = "serial8250",
 267         .id                     = PLAT8250_DEV_PLATFORM,
 268         .dev.platform_data      = uart_data,
 269         .num_resources          = 2,
 270         .resource               = uart_resources,
 271 };
 272
 273
 274 /* Built-in 10/100 Ethernet MAC interfaces */
 275 static struct eth_plat_info eth_plat[] = {
 276         {
 277                 .phy            = 0,
 278                 .rxq            = 3,
 279                 .txreadyq       = 32,
 280         }, {
 281                 .phy            = 1,
 282                 .rxq            = 4,
 283                 .txreadyq       = 33,
 284         }
 285 };
 286
 287 static struct platform_device device_eth_tab[] = {
 288         {
 289                 .name                   = "ixp4xx_eth",
 290                 .id                     = IXP4XX_ETH_NPEB,
 291                 .dev.platform_data      = eth_plat,
 292         }, {
 293                 .name                   = "ixp4xx_eth",
 294                 .id                     = IXP4XX_ETH_NPEC,
 295                 .dev.platform_data      = eth_plat + 1,
 296         }
 297 };
 298
 299
 300 /* IXP425 2 synchronous serial ports */
 301 static struct hss_plat_info hss_plat[] = {
 302         {
 303                 .set_clock      = hss_set_clock,
 304                 .open           = hss_open,
 305                 .close          = hss_close,
 306                 .txreadyq       = 34,
 307         }, {
 308                 .set_clock      = hss_set_clock,
 309                 .open           = hss_open,
 310                 .close          = hss_close,
 311                 .txreadyq       = 35,
 312         }
 313 };
 314
 315 static struct platform_device device_hss_tab[] = {
 316         {
 317                 .name                   = "ixp4xx_hss",
 318                 .id                     = 0,
 319                 .dev.platform_data      = hss_plat,
 320         }, {
 321                 .name                   = "ixp4xx_hss",
 322                 .id                     = 1,
 323                 .dev.platform_data      = hss_plat + 1,
 324         }
 325 };
 326
 327
 328 static struct platform_device *device_tab[7] __initdata = {
 329         &device_flash,          /* index 0 */
 330 };
 331
 332 static inline u8 __init flash_readb(u8 __iomem *flash, u32 addr)
 333 {
 334 #ifdef __ARMEB__
 335         return __raw_readb(flash + addr);
 336 #else
 337         return __raw_readb(flash + (addr ^ 3));
 338 #endif
 339 }
 340
 341 static inline u16 __init flash_readw(u8 __iomem *flash, u32 addr)
 342 {
 343 #ifdef __ARMEB__
 344         return __raw_readw(flash + addr);
 345 #else
 346         return __raw_readw(flash + (addr ^ 2));
 347 #endif
 348 }
 349
 350 static void __init gmlr_init(void)
 351 {
 352         u8 __iomem *flash;
 353         int i, devices = 1; /* flash */
 354
 355         ixp4xx_sys_init();
 356
 357         if ((flash = ioremap(IXP4XX_EXP_BUS_BASE_PHYS, 0x80)) == NULL)
 358                 printk(KERN_ERR "goramo-mlr: unable to access system"
 359                        " configuration data\n");
 360         else {
 361                 system_rev = __raw_readl(flash + CFG_REV);
 362                 hw_bits = __raw_readl(flash + CFG_HW_BITS);
 363
 364                 for (i = 0; i < ETH_ALEN; i++) {
 365                         eth_plat[0].hwaddr[i] =
 366                                 flash_readb(flash, CFG_ETH0_ADDRESS + i);
 367                         eth_plat[1].hwaddr[i] =
 368                                 flash_readb(flash, CFG_ETH1_ADDRESS + i);
 369                 }
 370
 371                 __raw_writew(FLASH_CMD_READ_ID, flash);
 372                 system_serial_high = flash_readw(flash, FLASH_SER_OFF);
 373                 system_serial_high <<= 16;
 374                 system_serial_high |= flash_readw(flash, FLASH_SER_OFF + 2);
 375                 system_serial_low = flash_readw(flash, FLASH_SER_OFF + 4);
 376                 system_serial_low <<= 16;
 377                 system_serial_low |= flash_readw(flash, FLASH_SER_OFF + 6);
 378                 __raw_writew(FLASH_CMD_READ_ARRAY, flash);
 379
 380                 iounmap(flash);
 381         }
 382
 383         switch (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1)) {
 384         case CFG_HW_HAS_UART0:
 385                 memset(&uart_data[1], 0, sizeof(uart_data[1]));
 386                 device_uarts.num_resources = 1;
 387                 break;
 388
 389         case CFG_HW_HAS_UART1:
 390                 device_uarts.dev.platform_data = &uart_data[1];
 391                 device_uarts.resource = &uart_resources[1];
 392                 device_uarts.num_resources = 1;
 393                 break;
 394         }
 395         if (hw_bits & (CFG_HW_HAS_UART0 | CFG_HW_HAS_UART1))
 396                 device_tab[devices++] = &device_uarts; /* max index 1 */
 397
 398         if (hw_bits & CFG_HW_HAS_ETH0)
 399                 device_tab[devices++] = &device_eth_tab[0]; /* max index 2 */
 400         if (hw_bits & CFG_HW_HAS_ETH1)
 401                 device_tab[devices++] = &device_eth_tab[1]; /* max index 3 */
 402
 403         if (hw_bits & CFG_HW_HAS_HSS0)
 404                 device_tab[devices++] = &device_hss_tab[0]; /* max index 4 */
 405         if (hw_bits & CFG_HW_HAS_HSS1)
 406                 device_tab[devices++] = &device_hss_tab[1]; /* max index 5 */
 407
 408         gpio_request(GPIO_SCL, "SCL/clock");
 409         gpio_request(GPIO_SDA, "SDA/data");
 410         gpio_request(GPIO_STR, "strobe");
 411         gpio_request(GPIO_HSS0_RTS_N, "HSS0 RTS");
 412         gpio_request(GPIO_HSS1_RTS_N, "HSS1 RTS");
 413         gpio_request(GPIO_HSS0_DCD_N, "HSS0 DCD");
 414         gpio_request(GPIO_HSS1_DCD_N, "HSS1 DCD");
 415
 416         gpio_direction_output(GPIO_SCL, 1);
 417         gpio_direction_output(GPIO_SDA, 1);
 418         gpio_direction_output(GPIO_STR, 0);
 419         gpio_direction_output(GPIO_HSS0_RTS_N, 1);
 420         gpio_direction_output(GPIO_HSS1_RTS_N, 1);
 421         gpio_direction_input(GPIO_HSS0_DCD_N);
 422         gpio_direction_input(GPIO_HSS1_DCD_N);
 423         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
 424         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
 425
 426         set_control(CONTROL_HSS0_DTR_N, 1);
 427         set_control(CONTROL_HSS1_DTR_N, 1);
 428         set_control(CONTROL_EEPROM_WC_N, 1);
 429         set_control(CONTROL_PCI_RESET_N, 1);
 430         output_control();
 431
 432         msleep(1);            /* Wait for PCI devices to initialize */
 433
 434         flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
 435         flash_resource.end = IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
 436
 437         platform_add_devices(device_tab, devices);
 438 }
 439
 440
 441 #ifdef CONFIG_PCI
 442 static void __init gmlr_pci_preinit(void)
 443 {
 444         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
 445         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
 446         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
 447         irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
 448         ixp4xx_pci_preinit();
 449 }
 450
 451 static void __init gmlr_pci_postinit(void)
 452 {
 453         if ((hw_bits & CFG_HW_USB_PORTS) >= 2 &&
 454             (hw_bits & CFG_HW_USB_PORTS) < 5) {
 455                 /* need to adjust number of USB ports on NEC chip */
 456                 u32 value, addr = BIT(32 - SLOT_NEC) | 0xE0;
 457                 if (!ixp4xx_pci_read(addr, NP_CMD_CONFIGREAD, &value)) {
 458                         value &= ~7;
 459                         value |= (hw_bits & CFG_HW_USB_PORTS);
 460                         ixp4xx_pci_write(addr, NP_CMD_CONFIGWRITE, value);
 461                 }
 462         }
 463 }
 464
 465 static int __init gmlr_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 466 {
 467         switch(slot) {
 468         case SLOT_ETHA: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA);
 469         case SLOT_ETHB: return IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB);
 470         case SLOT_NEC:  return IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC);
 471         default:        return IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI);
 472         }
 473 }
 474
 475 static struct hw_pci gmlr_hw_pci __initdata = {
 476         .nr_controllers = 1,
 477         .ops            = &ixp4xx_ops,
 478         .preinit        = gmlr_pci_preinit,
 479         .postinit       = gmlr_pci_postinit,
 480         .setup          = ixp4xx_setup,
 481         .map_irq        = gmlr_map_irq,
 482 };
 483
 484 static int __init gmlr_pci_init(void)
 485 {
 486         if (machine_is_goramo_mlr() &&
 487             (hw_bits & (CFG_HW_USB_PORTS | CFG_HW_HAS_PCI_SLOT)))
 488                 pci_common_init(&gmlr_hw_pci);
 489         return 0;
 490 }
 491
 492 subsys_initcall(gmlr_pci_init);
 493 #endif /* CONFIG_PCI */
 494
 495
 496 MACHINE_START(GORAMO_MLR, "MultiLink")
 497         /* Maintainer: Krzysztof Halasa */
 498         .map_io         = ixp4xx_map_io,
 499         .init_early     = ixp4xx_init_early,
 500         .init_irq       = ixp4xx_init_irq,
 501         .init_time      = ixp4xx_timer_init,
 502         .atag_offset    = 0x100,
 503         .init_machine   = gmlr_init,
 504 #if defined(CONFIG_PCI)
 505         .dma_zone_size  = SZ_64M,
 506 #endif
 507         .restart        = ixp4xx_restart,
 508 MACHINE_END