dm writecache: fix incorrect flush sequence when doing SSD mode commit
[linux/fpc-iii.git] / arch / arm / mach-rpc / include / mach / memory.h
bloba586eb31b18df7b920cf06f9b094ea4bc3c99b60
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * arch/arm/mach-rpc/include/mach/memory.h
5 * Copyright (C) 1996,1997,1998 Russell King.
7 * Changelog:
8 * 20-Oct-1996 RMK Created
9 * 31-Dec-1997 RMK Fixed definitions to reduce warnings
10 * 11-Jan-1998 RMK Uninlined to reduce hits on cache
11 * 08-Feb-1998 RMK Added __virt_to_bus and __bus_to_virt
12 * 21-Mar-1999 RMK Renamed to memory.h
13 * RMK Added TASK_SIZE and PAGE_OFFSET
15 #ifndef __ASM_ARCH_MEMORY_H
16 #define __ASM_ARCH_MEMORY_H
19 * Cache flushing area - ROM
21 #define FLUSH_BASE_PHYS 0x00000000
22 #define FLUSH_BASE 0xdf000000
25 * Sparsemem support. Each section is a maximum of 64MB. The sections
26 * are offset by 128MB and can cover 128MB, so that gives us a maximum
27 * of 29 physmem bits.
29 #define MAX_PHYSMEM_BITS 29
30 #define SECTION_SIZE_BITS 26
32 #endif