arch/powerpc/sysdev/fsl_rio.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Freescale MPC85xx/MPC86xx RapidIO support
   4  *
   5  * Copyright 2009 Sysgo AG
   6  * Thomas Moll <thomas.moll@sysgo.com>
   7  * - fixed maintenance access routines, check for aligned access
   8  *
   9  * Copyright 2009 Integrated Device Technology, Inc.
  10  * Alex Bounine <alexandre.bounine@idt.com>
  11  * - Added Port-Write message handling
  12  * - Added Machine Check exception handling
  13  *
  14  * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
  15  * Zhang Wei <wei.zhang@freescale.com>
  16  *
  17  * Copyright 2005 MontaVista Software, Inc.
  18  * Matt Porter <mporter@kernel.crashing.org>
  19  */
  20
  21 #include <linux/init.h>
  22 #include <linux/extable.h>
  23 #include <linux/types.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/device.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_irq.h>
  29 #include <linux/of_platform.h>
  30 #include <linux/delay.h>
  31 #include <linux/slab.h>
  32
  33 #include <linux/io.h>
  34 #include <linux/uaccess.h>
  35 #include <asm/machdep.h>
  36
  37 #include "fsl_rio.h"
  38
  39 #undef DEBUG_PW /* Port-Write debugging */
  40
  41 #define RIO_PORT1_EDCSR         0x0640
  42 #define RIO_PORT2_EDCSR         0x0680
  43 #define RIO_PORT1_IECSR         0x10130
  44 #define RIO_PORT2_IECSR         0x101B0
  45
  46 #define RIO_GCCSR               0x13c
  47 #define RIO_ESCSR               0x158
  48 #define ESCSR_CLEAR             0x07120204
  49 #define RIO_PORT2_ESCSR         0x178
  50 #define RIO_CCSR                0x15c
  51 #define RIO_LTLEDCSR_IER        0x80000000
  52 #define RIO_LTLEDCSR_PRT        0x01000000
  53 #define IECSR_CLEAR             0x80000000
  54 #define RIO_ISR_AACR            0x10120
  55 #define RIO_ISR_AACR_AA         0x1     /* Accept All ID */
  56
  57 #define RIWTAR_TRAD_VAL_SHIFT   12
  58 #define RIWTAR_TRAD_MASK        0x00FFFFFF
  59 #define RIWBAR_BADD_VAL_SHIFT   12
  60 #define RIWBAR_BADD_MASK        0x003FFFFF
  61 #define RIWAR_ENABLE            0x80000000
  62 #define RIWAR_TGINT_LOCAL       0x00F00000
  63 #define RIWAR_RDTYP_NO_SNOOP    0x00040000
  64 #define RIWAR_RDTYP_SNOOP       0x00050000
  65 #define RIWAR_WRTYP_NO_SNOOP    0x00004000
  66 #define RIWAR_WRTYP_SNOOP       0x00005000
  67 #define RIWAR_WRTYP_ALLOC       0x00006000
  68 #define RIWAR_SIZE_MASK         0x0000003F
  69
  70 static DEFINE_SPINLOCK(fsl_rio_config_lock);
  71
  72 #define __fsl_read_rio_config(x, addr, err, op)         \
  73         __asm__ __volatile__(                           \
  74                 "1:     "op" %1,0(%2)\n"                \
  75                 "       eieio\n"                        \
  76                 "2:\n"                                  \
  77                 ".section .fixup,\"ax\"\n"              \
  78                 "3:     li %1,-1\n"                     \
  79                 "       li %0,%3\n"                     \
  80                 "       b 2b\n"                         \
  81                 ".previous\n"                           \
  82                 EX_TABLE(1b, 3b)                        \
  83                 : "=r" (err), "=r" (x)                  \
  84                 : "b" (addr), "i" (-EFAULT), "0" (err))
  85
  86 void __iomem *rio_regs_win;
  87 void __iomem *rmu_regs_win;
  88 resource_size_t rio_law_start;
  89
  90 struct fsl_rio_dbell *dbell;
  91 struct fsl_rio_pw *pw;
  92
  93 #ifdef CONFIG_E500
  94 int fsl_rio_mcheck_exception(struct pt_regs *regs)
  95 {
  96         const struct exception_table_entry *entry;
  97         unsigned long reason;
  98
  99         if (!rio_regs_win)
 100                 return 0;
 101
 102         reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
 103         if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
 104                 /* Check if we are prepared to handle this fault */
 105                 entry = search_exception_tables(regs->nip);
 106                 if (entry) {
 107                         pr_debug("RIO: %s - MC Exception handled\n",
 108                                  __func__);
 109                         out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
 110                                  0);
 111                         regs->msr |= MSR_RI;
 112                         regs->nip = extable_fixup(entry);
 113                         return 1;
 114                 }
 115         }
 116
 117         return 0;
 118 }
 119 EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
 120 #endif
 121
 122 /**
 123  * fsl_local_config_read - Generate a MPC85xx local config space read
 124  * @mport: RapidIO master port info
 125  * @index: ID of RapdiIO interface
 126  * @offset: Offset into configuration space
 127  * @len: Length (in bytes) of the maintenance transaction
 128  * @data: Value to be read into
 129  *
 130  * Generates a MPC85xx local configuration space read. Returns %0 on
 131  * success or %-EINVAL on failure.
 132  */
 133 static int fsl_local_config_read(struct rio_mport *mport,
 134                                 int index, u32 offset, int len, u32 *data)
 135 {
 136         struct rio_priv *priv = mport->priv;
 137         pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
 138                  offset);
 139         *data = in_be32(priv->regs_win + offset);
 140
 141         return 0;
 142 }
 143
 144 /**
 145  * fsl_local_config_write - Generate a MPC85xx local config space write
 146  * @mport: RapidIO master port info
 147  * @index: ID of RapdiIO interface
 148  * @offset: Offset into configuration space
 149  * @len: Length (in bytes) of the maintenance transaction
 150  * @data: Value to be written
 151  *
 152  * Generates a MPC85xx local configuration space write. Returns %0 on
 153  * success or %-EINVAL on failure.
 154  */
 155 static int fsl_local_config_write(struct rio_mport *mport,
 156                                 int index, u32 offset, int len, u32 data)
 157 {
 158         struct rio_priv *priv = mport->priv;
 159         pr_debug
 160                 ("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
 161                 index, offset, data);
 162         out_be32(priv->regs_win + offset, data);
 163
 164         return 0;
 165 }
 166
 167 /**
 168  * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
 169  * @mport: RapidIO master port info
 170  * @index: ID of RapdiIO interface
 171  * @destid: Destination ID of transaction
 172  * @hopcount: Number of hops to target device
 173  * @offset: Offset into configuration space
 174  * @len: Length (in bytes) of the maintenance transaction
 175  * @val: Location to be read into
 176  *
 177  * Generates a MPC85xx read maintenance transaction. Returns %0 on
 178  * success or %-EINVAL on failure.
 179  */
 180 static int
 181 fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
 182                         u8 hopcount, u32 offset, int len, u32 *val)
 183 {
 184         struct rio_priv *priv = mport->priv;
 185         unsigned long flags;
 186         u8 *data;
 187         u32 rval, err = 0;
 188
 189         pr_debug
 190                 ("fsl_rio_config_read:"
 191                 " index %d destid %d hopcount %d offset %8.8x len %d\n",
 192                 index, destid, hopcount, offset, len);
 193
 194         /* 16MB maintenance window possible */
 195         /* allow only aligned access to maintenance registers */
 196         if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
 197                 return -EINVAL;
 198
 199         spin_lock_irqsave(&fsl_rio_config_lock, flags);
 200
 201         out_be32(&priv->maint_atmu_regs->rowtar,
 202                  (destid << 22) | (hopcount << 12) | (offset >> 12));
 203         out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
 204
 205         data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
 206         switch (len) {
 207         case 1:
 208                 __fsl_read_rio_config(rval, data, err, "lbz");
 209                 break;
 210         case 2:
 211                 __fsl_read_rio_config(rval, data, err, "lhz");
 212                 break;
 213         case 4:
 214                 __fsl_read_rio_config(rval, data, err, "lwz");
 215                 break;
 216         default:
 217                 spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
 218                 return -EINVAL;
 219         }
 220
 221         if (err) {
 222                 pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
 223                          err, destid, hopcount, offset);
 224         }
 225
 226         spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
 227         *val = rval;
 228
 229         return err;
 230 }
 231
 232 /**
 233  * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
 234  * @mport: RapidIO master port info
 235  * @index: ID of RapdiIO interface
 236  * @destid: Destination ID of transaction
 237  * @hopcount: Number of hops to target device
 238  * @offset: Offset into configuration space
 239  * @len: Length (in bytes) of the maintenance transaction
 240  * @val: Value to be written
 241  *
 242  * Generates an MPC85xx write maintenance transaction. Returns %0 on
 243  * success or %-EINVAL on failure.
 244  */
 245 static int
 246 fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
 247                         u8 hopcount, u32 offset, int len, u32 val)
 248 {
 249         struct rio_priv *priv = mport->priv;
 250         unsigned long flags;
 251         u8 *data;
 252         int ret = 0;
 253
 254         pr_debug
 255                 ("fsl_rio_config_write:"
 256                 " index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
 257                 index, destid, hopcount, offset, len, val);
 258
 259         /* 16MB maintenance windows possible */
 260         /* allow only aligned access to maintenance registers */
 261         if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
 262                 return -EINVAL;
 263
 264         spin_lock_irqsave(&fsl_rio_config_lock, flags);
 265
 266         out_be32(&priv->maint_atmu_regs->rowtar,
 267                  (destid << 22) | (hopcount << 12) | (offset >> 12));
 268         out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
 269
 270         data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
 271         switch (len) {
 272         case 1:
 273                 out_8((u8 *) data, val);
 274                 break;
 275         case 2:
 276                 out_be16((u16 *) data, val);
 277                 break;
 278         case 4:
 279                 out_be32((u32 *) data, val);
 280                 break;
 281         default:
 282                 ret = -EINVAL;
 283         }
 284         spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
 285
 286         return ret;
 287 }
 288
 289 static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
 290 {
 291         int i;
 292
 293         /* close inbound windows */
 294         for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
 295                 out_be32(&priv->inb_atmu_regs[i].riwar, 0);
 296 }
 297
 298 int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
 299         u64 rstart, u64 size, u32 flags)
 300 {
 301         struct rio_priv *priv = mport->priv;
 302         u32 base_size;
 303         unsigned int base_size_log;
 304         u64 win_start, win_end;
 305         u32 riwar;
 306         int i;
 307
 308         if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
 309                 return -EINVAL;
 310
 311         base_size_log = ilog2(size);
 312         base_size = 1 << base_size_log;
 313
 314         /* check if addresses are aligned with the window size */
 315         if (lstart & (base_size - 1))
 316                 return -EINVAL;
 317         if (rstart & (base_size - 1))
 318                 return -EINVAL;
 319
 320         /* check for conflicting ranges */
 321         for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
 322                 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
 323                 if ((riwar & RIWAR_ENABLE) == 0)
 324                         continue;
 325                 win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
 326                         << RIWBAR_BADD_VAL_SHIFT;
 327                 win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
 328                 if (rstart < win_end && (rstart + size) > win_start)
 329                         return -EINVAL;
 330         }
 331
 332         /* find unused atmu */
 333         for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
 334                 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
 335                 if ((riwar & RIWAR_ENABLE) == 0)
 336                         break;
 337         }
 338         if (i >= RIO_INB_ATMU_COUNT)
 339                 return -ENOMEM;
 340
 341         out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
 342         out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
 343         out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
 344                 RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
 345
 346         return 0;
 347 }
 348
 349 void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
 350 {
 351         u32 win_start_shift, base_start_shift;
 352         struct rio_priv *priv = mport->priv;
 353         u32 riwar, riwtar;
 354         int i;
 355
 356         /* skip default window */
 357         base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
 358         for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
 359                 riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
 360                 if ((riwar & RIWAR_ENABLE) == 0)
 361                         continue;
 362
 363                 riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
 364                 win_start_shift = riwtar & RIWTAR_TRAD_MASK;
 365                 if (win_start_shift == base_start_shift) {
 366                         out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
 367                         return;
 368                 }
 369         }
 370 }
 371
 372 void fsl_rio_port_error_handler(int offset)
 373 {
 374         /*XXX: Error recovery is not implemented, we just clear errors */
 375         out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
 376
 377         if (offset == 0) {
 378                 out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
 379                 out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
 380                 out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
 381         } else {
 382                 out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
 383                 out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
 384                 out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
 385         }
 386 }
 387 static inline void fsl_rio_info(struct device *dev, u32 ccsr)
 388 {
 389         const char *str;
 390         if (ccsr & 1) {
 391                 /* Serial phy */
 392                 switch (ccsr >> 30) {
 393                 case 0:
 394                         str = "1";
 395                         break;
 396                 case 1:
 397                         str = "4";
 398                         break;
 399                 default:
 400                         str = "Unknown";
 401                         break;
 402                 }
 403                 dev_info(dev, "Hardware port width: %s\n", str);
 404
 405                 switch ((ccsr >> 27) & 7) {
 406                 case 0:
 407                         str = "Single-lane 0";
 408                         break;
 409                 case 1:
 410                         str = "Single-lane 2";
 411                         break;
 412                 case 2:
 413                         str = "Four-lane";
 414                         break;
 415                 default:
 416                         str = "Unknown";
 417                         break;
 418                 }
 419                 dev_info(dev, "Training connection status: %s\n", str);
 420         } else {
 421                 /* Parallel phy */
 422                 if (!(ccsr & 0x80000000))
 423                         dev_info(dev, "Output port operating in 8-bit mode\n");
 424                 if (!(ccsr & 0x08000000))
 425                         dev_info(dev, "Input port operating in 8-bit mode\n");
 426         }
 427 }
 428
 429 /**
 430  * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
 431  * @dev: platform_device pointer
 432  *
 433  * Initializes MPC85xx RapidIO hardware interface, configures
 434  * master port with system-specific info, and registers the
 435  * master port with the RapidIO subsystem.
 436  */
 437 int fsl_rio_setup(struct platform_device *dev)
 438 {
 439         struct rio_ops *ops;
 440         struct rio_mport *port;
 441         struct rio_priv *priv;
 442         int rc = 0;
 443         const u32 *dt_range, *cell, *port_index;
 444         u32 active_ports = 0;
 445         struct resource regs, rmu_regs;
 446         struct device_node *np, *rmu_node;
 447         int rlen;
 448         u32 ccsr;
 449         u64 range_start, range_size;
 450         int paw, aw, sw;
 451         u32 i;
 452         static int tmp;
 453         struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
 454
 455         if (!dev->dev.of_node) {
 456                 dev_err(&dev->dev, "Device OF-Node is NULL");
 457                 return -ENODEV;
 458         }
 459
 460         rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
 461         if (rc) {
 462                 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
 463                                 dev->dev.of_node);
 464                 return -EFAULT;
 465         }
 466         dev_info(&dev->dev, "Of-device full name %pOF\n",
 467                         dev->dev.of_node);
 468         dev_info(&dev->dev, "Regs: %pR\n", &regs);
 469
 470         rio_regs_win = ioremap(regs.start, resource_size(&regs));
 471         if (!rio_regs_win) {
 472                 dev_err(&dev->dev, "Unable to map rio register window\n");
 473                 rc = -ENOMEM;
 474                 goto err_rio_regs;
 475         }
 476
 477         ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
 478         if (!ops) {
 479                 rc = -ENOMEM;
 480                 goto err_ops;
 481         }
 482         ops->lcread = fsl_local_config_read;
 483         ops->lcwrite = fsl_local_config_write;
 484         ops->cread = fsl_rio_config_read;
 485         ops->cwrite = fsl_rio_config_write;
 486         ops->dsend = fsl_rio_doorbell_send;
 487         ops->pwenable = fsl_rio_pw_enable;
 488         ops->open_outb_mbox = fsl_open_outb_mbox;
 489         ops->open_inb_mbox = fsl_open_inb_mbox;
 490         ops->close_outb_mbox = fsl_close_outb_mbox;
 491         ops->close_inb_mbox = fsl_close_inb_mbox;
 492         ops->add_outb_message = fsl_add_outb_message;
 493         ops->add_inb_buffer = fsl_add_inb_buffer;
 494         ops->get_inb_message = fsl_get_inb_message;
 495         ops->map_inb = fsl_map_inb_mem;
 496         ops->unmap_inb = fsl_unmap_inb_mem;
 497
 498         rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
 499         if (!rmu_node) {
 500                 dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
 501                 rc = -ENOENT;
 502                 goto err_rmu;
 503         }
 504         rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
 505         if (rc) {
 506                 dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
 507                                 rmu_node);
 508                 goto err_rmu;
 509         }
 510         rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
 511         if (!rmu_regs_win) {
 512                 dev_err(&dev->dev, "Unable to map rmu register window\n");
 513                 rc = -ENOMEM;
 514                 goto err_rmu;
 515         }
 516         for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
 517                 rmu_np[tmp] = np;
 518                 tmp++;
 519         }
 520
 521         /*set up doobell node*/
 522         np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
 523         if (!np) {
 524                 dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
 525                 rc = -ENODEV;
 526                 goto err_dbell;
 527         }
 528         dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
 529         if (!(dbell)) {
 530                 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
 531                 rc = -ENOMEM;
 532                 goto err_dbell;
 533         }
 534         dbell->dev = &dev->dev;
 535         dbell->bellirq = irq_of_parse_and_map(np, 1);
 536         dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
 537
 538         aw = of_n_addr_cells(np);
 539         dt_range = of_get_property(np, "reg", &rlen);
 540         if (!dt_range) {
 541                 pr_err("%pOF: unable to find 'reg' property\n",
 542                         np);
 543                 rc = -ENOMEM;
 544                 goto err_pw;
 545         }
 546         range_start = of_read_number(dt_range, aw);
 547         dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
 548                                 (u32)range_start);
 549
 550         /*set up port write node*/
 551         np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
 552         if (!np) {
 553                 dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
 554                 rc = -ENODEV;
 555                 goto err_pw;
 556         }
 557         pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
 558         if (!(pw)) {
 559                 dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
 560                 rc = -ENOMEM;
 561                 goto err_pw;
 562         }
 563         pw->dev = &dev->dev;
 564         pw->pwirq = irq_of_parse_and_map(np, 0);
 565         dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
 566         aw = of_n_addr_cells(np);
 567         dt_range = of_get_property(np, "reg", &rlen);
 568         if (!dt_range) {
 569                 pr_err("%pOF: unable to find 'reg' property\n",
 570                         np);
 571                 rc = -ENOMEM;
 572                 goto err;
 573         }
 574         range_start = of_read_number(dt_range, aw);
 575         pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
 576
 577         /*set up ports node*/
 578         for_each_child_of_node(dev->dev.of_node, np) {
 579                 port_index = of_get_property(np, "cell-index", NULL);
 580                 if (!port_index) {
 581                         dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
 582                                         np);
 583                         continue;
 584                 }
 585
 586                 dt_range = of_get_property(np, "ranges", &rlen);
 587                 if (!dt_range) {
 588                         dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
 589                                         np);
 590                         continue;
 591                 }
 592
 593                 /* Get node address wide */
 594                 cell = of_get_property(np, "#address-cells", NULL);
 595                 if (cell)
 596                         aw = *cell;
 597                 else
 598                         aw = of_n_addr_cells(np);
 599                 /* Get node size wide */
 600                 cell = of_get_property(np, "#size-cells", NULL);
 601                 if (cell)
 602                         sw = *cell;
 603                 else
 604                         sw = of_n_size_cells(np);
 605                 /* Get parent address wide wide */
 606                 paw = of_n_addr_cells(np);
 607                 range_start = of_read_number(dt_range + aw, paw);
 608                 range_size = of_read_number(dt_range + aw + paw, sw);
 609
 610                 dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n",
 611                                 np, range_start, range_size);
 612
 613                 port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
 614                 if (!port)
 615                         continue;
 616
 617                 rc = rio_mport_initialize(port);
 618                 if (rc) {
 619                         kfree(port);
 620                         continue;
 621                 }
 622
 623                 i = *port_index - 1;
 624                 port->index = (unsigned char)i;
 625
 626                 priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
 627                 if (!priv) {
 628                         dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
 629                         kfree(port);
 630                         continue;
 631                 }
 632
 633                 INIT_LIST_HEAD(&port->dbells);
 634                 port->iores.start = range_start;
 635                 port->iores.end = port->iores.start + range_size - 1;
 636                 port->iores.flags = IORESOURCE_MEM;
 637                 port->iores.name = "rio_io_win";
 638
 639                 if (request_resource(&iomem_resource, &port->iores) < 0) {
 640                         dev_err(&dev->dev, "RIO: Error requesting master port region"
 641                                 " 0x%016llx-0x%016llx\n",
 642                                 (u64)port->iores.start, (u64)port->iores.end);
 643                                 kfree(priv);
 644                                 kfree(port);
 645                                 continue;
 646                 }
 647                 sprintf(port->name, "RIO mport %d", i);
 648
 649                 priv->dev = &dev->dev;
 650                 port->dev.parent = &dev->dev;
 651                 port->ops = ops;
 652                 port->priv = priv;
 653                 port->phys_efptr = 0x100;
 654                 port->phys_rmap = 1;
 655                 priv->regs_win = rio_regs_win;
 656
 657                 ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
 658
 659                 /* Checking the port training status */
 660                 if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
 661                         dev_err(&dev->dev, "Port %d is not ready. "
 662                         "Try to restart connection...\n", i);
 663                         /* Disable ports */
 664                         out_be32(priv->regs_win
 665                                 + RIO_CCSR + i*0x20, 0);
 666                         /* Set 1x lane */
 667                         setbits32(priv->regs_win
 668                                 + RIO_CCSR + i*0x20, 0x02000000);
 669                         /* Enable ports */
 670                         setbits32(priv->regs_win
 671                                 + RIO_CCSR + i*0x20, 0x00600000);
 672                         msleep(100);
 673                         if (in_be32((priv->regs_win
 674                                         + RIO_ESCSR + i*0x20)) & 1) {
 675                                 dev_err(&dev->dev,
 676                                         "Port %d restart failed.\n", i);
 677                                 release_resource(&port->iores);
 678                                 kfree(priv);
 679                                 kfree(port);
 680                                 continue;
 681                         }
 682                         dev_info(&dev->dev, "Port %d restart success!\n", i);
 683                 }
 684                 fsl_rio_info(&dev->dev, ccsr);
 685
 686                 port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
 687                                         & RIO_PEF_CTLS) >> 4;
 688                 dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
 689                                 port->sys_size ? 65536 : 256);
 690
 691                 if (port->host_deviceid >= 0)
 692                         out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
 693                                 RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
 694                 else
 695                         out_be32(priv->regs_win + RIO_GCCSR,
 696                                 RIO_PORT_GEN_MASTER);
 697
 698                 priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
 699                         + ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
 700                         RIO_ATMU_REGS_PORT2_OFFSET));
 701
 702                 priv->maint_atmu_regs = priv->atmu_regs + 1;
 703                 priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
 704                         (priv->regs_win +
 705                         ((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
 706                         RIO_INB_ATMU_REGS_PORT2_OFFSET));
 707
 708                 /* Set to receive packets with any dest ID */
 709                 out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
 710                          RIO_ISR_AACR_AA);
 711
 712                 /* Configure maintenance transaction window */
 713                 out_be32(&priv->maint_atmu_regs->rowbar,
 714                         port->iores.start >> 12);
 715                 out_be32(&priv->maint_atmu_regs->rowar,
 716                          0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
 717
 718                 priv->maint_win = ioremap(port->iores.start,
 719                                 RIO_MAINT_WIN_SIZE);
 720
 721                 rio_law_start = range_start;
 722
 723                 fsl_rio_setup_rmu(port, rmu_np[i]);
 724                 fsl_rio_inbound_mem_init(priv);
 725
 726                 dbell->mport[i] = port;
 727                 pw->mport[i] = port;
 728
 729                 if (rio_register_mport(port)) {
 730                         release_resource(&port->iores);
 731                         kfree(priv);
 732                         kfree(port);
 733                         continue;
 734                 }
 735                 active_ports++;
 736         }
 737
 738         if (!active_ports) {
 739                 rc = -ENOLINK;
 740                 goto err;
 741         }
 742
 743         fsl_rio_doorbell_init(dbell);
 744         fsl_rio_port_write_init(pw);
 745
 746         return 0;
 747 err:
 748         kfree(pw);
 749         pw = NULL;
 750 err_pw:
 751         kfree(dbell);
 752         dbell = NULL;
 753 err_dbell:
 754         iounmap(rmu_regs_win);
 755         rmu_regs_win = NULL;
 756 err_rmu:
 757         kfree(ops);
 758 err_ops:
 759         iounmap(rio_regs_win);
 760         rio_regs_win = NULL;
 761 err_rio_regs:
 762         return rc;
 763 }
 764
 765 /* The probe function for RapidIO peer-to-peer network.
 766  */
 767 static int fsl_of_rio_rpn_probe(struct platform_device *dev)
 768 {
 769         printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
 770                         dev->dev.of_node);
 771
 772         return fsl_rio_setup(dev);
 773 };
 774
 775 static const struct of_device_id fsl_of_rio_rpn_ids[] = {
 776         {
 777                 .compatible = "fsl,srio",
 778         },
 779         {},
 780 };
 781
 782 static struct platform_driver fsl_of_rio_rpn_driver = {
 783         .driver = {
 784                 .name = "fsl-of-rio",
 785                 .of_match_table = fsl_of_rio_rpn_ids,
 786         },
 787         .probe = fsl_of_rio_rpn_probe,
 788 };
 789
 790 static __init int fsl_of_rio_rpn_init(void)
 791 {
 792         return platform_driver_register(&fsl_of_rio_rpn_driver);
 793 }
 794
 795 subsys_initcall(fsl_of_rio_rpn_init);