arch/powerpc/sysdev/xive/spapr.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2016,2017 IBM Corporation.
   4  */
   5
   6 #define pr_fmt(fmt) "xive: " fmt
   7
   8 #include <linux/types.h>
   9 #include <linux/irq.h>
  10 #include <linux/smp.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/init.h>
  13 #include <linux/of.h>
  14 #include <linux/slab.h>
  15 #include <linux/spinlock.h>
  16 #include <linux/cpumask.h>
  17 #include <linux/mm.h>
  18 #include <linux/delay.h>
  19 #include <linux/libfdt.h>
  20
  21 #include <asm/prom.h>
  22 #include <asm/io.h>
  23 #include <asm/smp.h>
  24 #include <asm/irq.h>
  25 #include <asm/errno.h>
  26 #include <asm/xive.h>
  27 #include <asm/xive-regs.h>
  28 #include <asm/hvcall.h>
  29
  30 #include "xive-internal.h"
  31
  32 static u32 xive_queue_shift;
  33
  34 struct xive_irq_bitmap {
  35         unsigned long           *bitmap;
  36         unsigned int            base;
  37         unsigned int            count;
  38         spinlock_t              lock;
  39         struct list_head        list;
  40 };
  41
  42 static LIST_HEAD(xive_irq_bitmaps);
  43
  44 static int xive_irq_bitmap_add(int base, int count)
  45 {
  46         struct xive_irq_bitmap *xibm;
  47
  48         xibm = kzalloc(sizeof(*xibm), GFP_KERNEL);
  49         if (!xibm)
  50                 return -ENOMEM;
  51
  52         spin_lock_init(&xibm->lock);
  53         xibm->base = base;
  54         xibm->count = count;
  55         xibm->bitmap = kzalloc(xibm->count, GFP_KERNEL);
  56         if (!xibm->bitmap) {
  57                 kfree(xibm);
  58                 return -ENOMEM;
  59         }
  60         list_add(&xibm->list, &xive_irq_bitmaps);
  61
  62         pr_info("Using IRQ range [%x-%x]", xibm->base,
  63                 xibm->base + xibm->count - 1);
  64         return 0;
  65 }
  66
  67 static int __xive_irq_bitmap_alloc(struct xive_irq_bitmap *xibm)
  68 {
  69         int irq;
  70
  71         irq = find_first_zero_bit(xibm->bitmap, xibm->count);
  72         if (irq != xibm->count) {
  73                 set_bit(irq, xibm->bitmap);
  74                 irq += xibm->base;
  75         } else {
  76                 irq = -ENOMEM;
  77         }
  78
  79         return irq;
  80 }
  81
  82 static int xive_irq_bitmap_alloc(void)
  83 {
  84         struct xive_irq_bitmap *xibm;
  85         unsigned long flags;
  86         int irq = -ENOENT;
  87
  88         list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
  89                 spin_lock_irqsave(&xibm->lock, flags);
  90                 irq = __xive_irq_bitmap_alloc(xibm);
  91                 spin_unlock_irqrestore(&xibm->lock, flags);
  92                 if (irq >= 0)
  93                         break;
  94         }
  95         return irq;
  96 }
  97
  98 static void xive_irq_bitmap_free(int irq)
  99 {
 100         unsigned long flags;
 101         struct xive_irq_bitmap *xibm;
 102
 103         list_for_each_entry(xibm, &xive_irq_bitmaps, list) {
 104                 if ((irq >= xibm->base) && (irq < xibm->base + xibm->count)) {
 105                         spin_lock_irqsave(&xibm->lock, flags);
 106                         clear_bit(irq - xibm->base, xibm->bitmap);
 107                         spin_unlock_irqrestore(&xibm->lock, flags);
 108                         break;
 109                 }
 110         }
 111 }
 112
 113
 114 /* Based on the similar routines in RTAS */
 115 static unsigned int plpar_busy_delay_time(long rc)
 116 {
 117         unsigned int ms = 0;
 118
 119         if (H_IS_LONG_BUSY(rc)) {
 120                 ms = get_longbusy_msecs(rc);
 121         } else if (rc == H_BUSY) {
 122                 ms = 10; /* seems appropriate for XIVE hcalls */
 123         }
 124
 125         return ms;
 126 }
 127
 128 static unsigned int plpar_busy_delay(int rc)
 129 {
 130         unsigned int ms;
 131
 132         ms = plpar_busy_delay_time(rc);
 133         if (ms)
 134                 mdelay(ms);
 135
 136         return ms;
 137 }
 138
 139 /*
 140  * Note: this call has a partition wide scope and can take a while to
 141  * complete. If it returns H_LONG_BUSY_* it should be retried
 142  * periodically.
 143  */
 144 static long plpar_int_reset(unsigned long flags)
 145 {
 146         long rc;
 147
 148         do {
 149                 rc = plpar_hcall_norets(H_INT_RESET, flags);
 150         } while (plpar_busy_delay(rc));
 151
 152         if (rc)
 153                 pr_err("H_INT_RESET failed %ld\n", rc);
 154
 155         return rc;
 156 }
 157
 158 static long plpar_int_get_source_info(unsigned long flags,
 159                                       unsigned long lisn,
 160                                       unsigned long *src_flags,
 161                                       unsigned long *eoi_page,
 162                                       unsigned long *trig_page,
 163                                       unsigned long *esb_shift)
 164 {
 165         unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
 166         long rc;
 167
 168         do {
 169                 rc = plpar_hcall(H_INT_GET_SOURCE_INFO, retbuf, flags, lisn);
 170         } while (plpar_busy_delay(rc));
 171
 172         if (rc) {
 173                 pr_err("H_INT_GET_SOURCE_INFO lisn=%ld failed %ld\n", lisn, rc);
 174                 return rc;
 175         }
 176
 177         *src_flags = retbuf[0];
 178         *eoi_page  = retbuf[1];
 179         *trig_page = retbuf[2];
 180         *esb_shift = retbuf[3];
 181
 182         pr_devel("H_INT_GET_SOURCE_INFO flags=%lx eoi=%lx trig=%lx shift=%lx\n",
 183                 retbuf[0], retbuf[1], retbuf[2], retbuf[3]);
 184
 185         return 0;
 186 }
 187
 188 #define XIVE_SRC_SET_EISN (1ull << (63 - 62))
 189 #define XIVE_SRC_MASK     (1ull << (63 - 63)) /* unused */
 190
 191 static long plpar_int_set_source_config(unsigned long flags,
 192                                         unsigned long lisn,
 193                                         unsigned long target,
 194                                         unsigned long prio,
 195                                         unsigned long sw_irq)
 196 {
 197         long rc;
 198
 199
 200         pr_devel("H_INT_SET_SOURCE_CONFIG flags=%lx lisn=%lx target=%lx prio=%lx sw_irq=%lx\n",
 201                 flags, lisn, target, prio, sw_irq);
 202
 203
 204         do {
 205                 rc = plpar_hcall_norets(H_INT_SET_SOURCE_CONFIG, flags, lisn,
 206                                         target, prio, sw_irq);
 207         } while (plpar_busy_delay(rc));
 208
 209         if (rc) {
 210                 pr_err("H_INT_SET_SOURCE_CONFIG lisn=%ld target=%lx prio=%lx failed %ld\n",
 211                        lisn, target, prio, rc);
 212                 return rc;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static long plpar_int_get_source_config(unsigned long flags,
 219                                         unsigned long lisn,
 220                                         unsigned long *target,
 221                                         unsigned long *prio,
 222                                         unsigned long *sw_irq)
 223 {
 224         unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
 225         long rc;
 226
 227         pr_devel("H_INT_GET_SOURCE_CONFIG flags=%lx lisn=%lx\n", flags, lisn);
 228
 229         do {
 230                 rc = plpar_hcall(H_INT_GET_SOURCE_CONFIG, retbuf, flags, lisn,
 231                                  target, prio, sw_irq);
 232         } while (plpar_busy_delay(rc));
 233
 234         if (rc) {
 235                 pr_err("H_INT_GET_SOURCE_CONFIG lisn=%ld failed %ld\n",
 236                        lisn, rc);
 237                 return rc;
 238         }
 239
 240         *target = retbuf[0];
 241         *prio   = retbuf[1];
 242         *sw_irq = retbuf[2];
 243
 244         pr_devel("H_INT_GET_SOURCE_CONFIG target=%lx prio=%lx sw_irq=%lx\n",
 245                 retbuf[0], retbuf[1], retbuf[2]);
 246
 247         return 0;
 248 }
 249
 250 static long plpar_int_get_queue_info(unsigned long flags,
 251                                      unsigned long target,
 252                                      unsigned long priority,
 253                                      unsigned long *esn_page,
 254                                      unsigned long *esn_size)
 255 {
 256         unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
 257         long rc;
 258
 259         do {
 260                 rc = plpar_hcall(H_INT_GET_QUEUE_INFO, retbuf, flags, target,
 261                                  priority);
 262         } while (plpar_busy_delay(rc));
 263
 264         if (rc) {
 265                 pr_err("H_INT_GET_QUEUE_INFO cpu=%ld prio=%ld failed %ld\n",
 266                        target, priority, rc);
 267                 return rc;
 268         }
 269
 270         *esn_page = retbuf[0];
 271         *esn_size = retbuf[1];
 272
 273         pr_devel("H_INT_GET_QUEUE_INFO page=%lx size=%lx\n",
 274                 retbuf[0], retbuf[1]);
 275
 276         return 0;
 277 }
 278
 279 #define XIVE_EQ_ALWAYS_NOTIFY (1ull << (63 - 63))
 280
 281 static long plpar_int_set_queue_config(unsigned long flags,
 282                                        unsigned long target,
 283                                        unsigned long priority,
 284                                        unsigned long qpage,
 285                                        unsigned long qsize)
 286 {
 287         long rc;
 288
 289         pr_devel("H_INT_SET_QUEUE_CONFIG flags=%lx target=%lx priority=%lx qpage=%lx qsize=%lx\n",
 290                 flags,  target, priority, qpage, qsize);
 291
 292         do {
 293                 rc = plpar_hcall_norets(H_INT_SET_QUEUE_CONFIG, flags, target,
 294                                         priority, qpage, qsize);
 295         } while (plpar_busy_delay(rc));
 296
 297         if (rc) {
 298                 pr_err("H_INT_SET_QUEUE_CONFIG cpu=%ld prio=%ld qpage=%lx returned %ld\n",
 299                        target, priority, qpage, rc);
 300                 return  rc;
 301         }
 302
 303         return 0;
 304 }
 305
 306 static long plpar_int_sync(unsigned long flags, unsigned long lisn)
 307 {
 308         long rc;
 309
 310         do {
 311                 rc = plpar_hcall_norets(H_INT_SYNC, flags, lisn);
 312         } while (plpar_busy_delay(rc));
 313
 314         if (rc) {
 315                 pr_err("H_INT_SYNC lisn=%ld returned %ld\n", lisn, rc);
 316                 return  rc;
 317         }
 318
 319         return 0;
 320 }
 321
 322 #define XIVE_ESB_FLAG_STORE (1ull << (63 - 63))
 323
 324 static long plpar_int_esb(unsigned long flags,
 325                           unsigned long lisn,
 326                           unsigned long offset,
 327                           unsigned long in_data,
 328                           unsigned long *out_data)
 329 {
 330         unsigned long retbuf[PLPAR_HCALL_BUFSIZE];
 331         long rc;
 332
 333         pr_devel("H_INT_ESB flags=%lx lisn=%lx offset=%lx in=%lx\n",
 334                 flags,  lisn, offset, in_data);
 335
 336         do {
 337                 rc = plpar_hcall(H_INT_ESB, retbuf, flags, lisn, offset,
 338                                  in_data);
 339         } while (plpar_busy_delay(rc));
 340
 341         if (rc) {
 342                 pr_err("H_INT_ESB lisn=%ld offset=%ld returned %ld\n",
 343                        lisn, offset, rc);
 344                 return  rc;
 345         }
 346
 347         *out_data = retbuf[0];
 348
 349         return 0;
 350 }
 351
 352 static u64 xive_spapr_esb_rw(u32 lisn, u32 offset, u64 data, bool write)
 353 {
 354         unsigned long read_data;
 355         long rc;
 356
 357         rc = plpar_int_esb(write ? XIVE_ESB_FLAG_STORE : 0,
 358                            lisn, offset, data, &read_data);
 359         if (rc)
 360                 return -1;
 361
 362         return write ? 0 : read_data;
 363 }
 364
 365 #define XIVE_SRC_H_INT_ESB     (1ull << (63 - 60))
 366 #define XIVE_SRC_LSI           (1ull << (63 - 61))
 367 #define XIVE_SRC_TRIGGER       (1ull << (63 - 62))
 368 #define XIVE_SRC_STORE_EOI     (1ull << (63 - 63))
 369
 370 static int xive_spapr_populate_irq_data(u32 hw_irq, struct xive_irq_data *data)
 371 {
 372         long rc;
 373         unsigned long flags;
 374         unsigned long eoi_page;
 375         unsigned long trig_page;
 376         unsigned long esb_shift;
 377
 378         memset(data, 0, sizeof(*data));
 379
 380         rc = plpar_int_get_source_info(0, hw_irq, &flags, &eoi_page, &trig_page,
 381                                        &esb_shift);
 382         if (rc)
 383                 return  -EINVAL;
 384
 385         if (flags & XIVE_SRC_H_INT_ESB)
 386                 data->flags  |= XIVE_IRQ_FLAG_H_INT_ESB;
 387         if (flags & XIVE_SRC_STORE_EOI)
 388                 data->flags  |= XIVE_IRQ_FLAG_STORE_EOI;
 389         if (flags & XIVE_SRC_LSI)
 390                 data->flags  |= XIVE_IRQ_FLAG_LSI;
 391         data->eoi_page  = eoi_page;
 392         data->esb_shift = esb_shift;
 393         data->trig_page = trig_page;
 394
 395         data->hw_irq = hw_irq;
 396
 397         /*
 398          * No chip-id for the sPAPR backend. This has an impact how we
 399          * pick a target. See xive_pick_irq_target().
 400          */
 401         data->src_chip = XIVE_INVALID_CHIP_ID;
 402
 403         /*
 404          * When the H_INT_ESB flag is set, the H_INT_ESB hcall should
 405          * be used for interrupt management. Skip the remapping of the
 406          * ESB pages which are not available.
 407          */
 408         if (data->flags & XIVE_IRQ_FLAG_H_INT_ESB)
 409                 return 0;
 410
 411         data->eoi_mmio = ioremap(data->eoi_page, 1u << data->esb_shift);
 412         if (!data->eoi_mmio) {
 413                 pr_err("Failed to map EOI page for irq 0x%x\n", hw_irq);
 414                 return -ENOMEM;
 415         }
 416
 417         /* Full function page supports trigger */
 418         if (flags & XIVE_SRC_TRIGGER) {
 419                 data->trig_mmio = data->eoi_mmio;
 420                 return 0;
 421         }
 422
 423         data->trig_mmio = ioremap(data->trig_page, 1u << data->esb_shift);
 424         if (!data->trig_mmio) {
 425                 pr_err("Failed to map trigger page for irq 0x%x\n", hw_irq);
 426                 return -ENOMEM;
 427         }
 428         return 0;
 429 }
 430
 431 static int xive_spapr_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq)
 432 {
 433         long rc;
 434
 435         rc = plpar_int_set_source_config(XIVE_SRC_SET_EISN, hw_irq, target,
 436                                          prio, sw_irq);
 437
 438         return rc == 0 ? 0 : -ENXIO;
 439 }
 440
 441 static int xive_spapr_get_irq_config(u32 hw_irq, u32 *target, u8 *prio,
 442                                      u32 *sw_irq)
 443 {
 444         long rc;
 445         unsigned long h_target;
 446         unsigned long h_prio;
 447         unsigned long h_sw_irq;
 448
 449         rc = plpar_int_get_source_config(0, hw_irq, &h_target, &h_prio,
 450                                          &h_sw_irq);
 451
 452         *target = h_target;
 453         *prio = h_prio;
 454         *sw_irq = h_sw_irq;
 455
 456         return rc == 0 ? 0 : -ENXIO;
 457 }
 458
 459 /* This can be called multiple time to change a queue configuration */
 460 static int xive_spapr_configure_queue(u32 target, struct xive_q *q, u8 prio,
 461                                    __be32 *qpage, u32 order)
 462 {
 463         s64 rc = 0;
 464         unsigned long esn_page;
 465         unsigned long esn_size;
 466         u64 flags, qpage_phys;
 467
 468         /* If there's an actual queue page, clean it */
 469         if (order) {
 470                 if (WARN_ON(!qpage))
 471                         return -EINVAL;
 472                 qpage_phys = __pa(qpage);
 473         } else {
 474                 qpage_phys = 0;
 475         }
 476
 477         /* Initialize the rest of the fields */
 478         q->msk = order ? ((1u << (order - 2)) - 1) : 0;
 479         q->idx = 0;
 480         q->toggle = 0;
 481
 482         rc = plpar_int_get_queue_info(0, target, prio, &esn_page, &esn_size);
 483         if (rc) {
 484                 pr_err("Error %lld getting queue info CPU %d prio %d\n", rc,
 485                        target, prio);
 486                 rc = -EIO;
 487                 goto fail;
 488         }
 489
 490         /* TODO: add support for the notification page */
 491         q->eoi_phys = esn_page;
 492
 493         /* Default is to always notify */
 494         flags = XIVE_EQ_ALWAYS_NOTIFY;
 495
 496         /* Configure and enable the queue in HW */
 497         rc = plpar_int_set_queue_config(flags, target, prio, qpage_phys, order);
 498         if (rc) {
 499                 pr_err("Error %lld setting queue for CPU %d prio %d\n", rc,
 500                        target, prio);
 501                 rc = -EIO;
 502         } else {
 503                 q->qpage = qpage;
 504         }
 505 fail:
 506         return rc;
 507 }
 508
 509 static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc,
 510                                   u8 prio)
 511 {
 512         struct xive_q *q = &xc->queue[prio];
 513         __be32 *qpage;
 514
 515         qpage = xive_queue_page_alloc(cpu, xive_queue_shift);
 516         if (IS_ERR(qpage))
 517                 return PTR_ERR(qpage);
 518
 519         return xive_spapr_configure_queue(get_hard_smp_processor_id(cpu),
 520                                           q, prio, qpage, xive_queue_shift);
 521 }
 522
 523 static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc,
 524                                   u8 prio)
 525 {
 526         struct xive_q *q = &xc->queue[prio];
 527         unsigned int alloc_order;
 528         long rc;
 529         int hw_cpu = get_hard_smp_processor_id(cpu);
 530
 531         rc = plpar_int_set_queue_config(0, hw_cpu, prio, 0, 0);
 532         if (rc)
 533                 pr_err("Error %ld setting queue for CPU %d prio %d\n", rc,
 534                        hw_cpu, prio);
 535
 536         alloc_order = xive_alloc_order(xive_queue_shift);
 537         free_pages((unsigned long)q->qpage, alloc_order);
 538         q->qpage = NULL;
 539 }
 540
 541 static bool xive_spapr_match(struct device_node *node)
 542 {
 543         /* Ignore cascaded controllers for the moment */
 544         return 1;
 545 }
 546
 547 #ifdef CONFIG_SMP
 548 static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc)
 549 {
 550         int irq = xive_irq_bitmap_alloc();
 551
 552         if (irq < 0) {
 553                 pr_err("Failed to allocate IPI on CPU %d\n", cpu);
 554                 return -ENXIO;
 555         }
 556
 557         xc->hw_ipi = irq;
 558         return 0;
 559 }
 560
 561 static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc)
 562 {
 563         if (!xc->hw_ipi)
 564                 return;
 565
 566         xive_irq_bitmap_free(xc->hw_ipi);
 567         xc->hw_ipi = 0;
 568 }
 569 #endif /* CONFIG_SMP */
 570
 571 static void xive_spapr_shutdown(void)
 572 {
 573         plpar_int_reset(0);
 574 }
 575
 576 /*
 577  * Perform an "ack" cycle on the current thread. Grab the pending
 578  * active priorities and update the CPPR to the most favored one.
 579  */
 580 static void xive_spapr_update_pending(struct xive_cpu *xc)
 581 {
 582         u8 nsr, cppr;
 583         u16 ack;
 584
 585         /*
 586          * Perform the "Acknowledge O/S to Register" cycle.
 587          *
 588          * Let's speedup the access to the TIMA using the raw I/O
 589          * accessor as we don't need the synchronisation routine of
 590          * the higher level ones
 591          */
 592         ack = be16_to_cpu(__raw_readw(xive_tima + TM_SPC_ACK_OS_REG));
 593
 594         /* Synchronize subsequent queue accesses */
 595         mb();
 596
 597         /*
 598          * Grab the CPPR and the "NSR" field which indicates the source
 599          * of the interrupt (if any)
 600          */
 601         cppr = ack & 0xff;
 602         nsr = ack >> 8;
 603
 604         if (nsr & TM_QW1_NSR_EO) {
 605                 if (cppr == 0xff)
 606                         return;
 607                 /* Mark the priority pending */
 608                 xc->pending_prio |= 1 << cppr;
 609
 610                 /*
 611                  * A new interrupt should never have a CPPR less favored
 612                  * than our current one.
 613                  */
 614                 if (cppr >= xc->cppr)
 615                         pr_err("CPU %d odd ack CPPR, got %d at %d\n",
 616                                smp_processor_id(), cppr, xc->cppr);
 617
 618                 /* Update our idea of what the CPPR is */
 619                 xc->cppr = cppr;
 620         }
 621 }
 622
 623 static void xive_spapr_eoi(u32 hw_irq)
 624 {
 625         /* Not used */;
 626 }
 627
 628 static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc)
 629 {
 630         /* Only some debug on the TIMA settings */
 631         pr_debug("(HW value: %08x %08x %08x)\n",
 632                  in_be32(xive_tima + TM_QW1_OS + TM_WORD0),
 633                  in_be32(xive_tima + TM_QW1_OS + TM_WORD1),
 634                  in_be32(xive_tima + TM_QW1_OS + TM_WORD2));
 635 }
 636
 637 static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc)
 638 {
 639         /* Nothing to do */;
 640 }
 641
 642 static void xive_spapr_sync_source(u32 hw_irq)
 643 {
 644         /* Specs are unclear on what this is doing */
 645         plpar_int_sync(0, hw_irq);
 646 }
 647
 648 static const struct xive_ops xive_spapr_ops = {
 649         .populate_irq_data      = xive_spapr_populate_irq_data,
 650         .configure_irq          = xive_spapr_configure_irq,
 651         .get_irq_config         = xive_spapr_get_irq_config,
 652         .setup_queue            = xive_spapr_setup_queue,
 653         .cleanup_queue          = xive_spapr_cleanup_queue,
 654         .match                  = xive_spapr_match,
 655         .shutdown               = xive_spapr_shutdown,
 656         .update_pending         = xive_spapr_update_pending,
 657         .eoi                    = xive_spapr_eoi,
 658         .setup_cpu              = xive_spapr_setup_cpu,
 659         .teardown_cpu           = xive_spapr_teardown_cpu,
 660         .sync_source            = xive_spapr_sync_source,
 661         .esb_rw                 = xive_spapr_esb_rw,
 662 #ifdef CONFIG_SMP
 663         .get_ipi                = xive_spapr_get_ipi,
 664         .put_ipi                = xive_spapr_put_ipi,
 665 #endif /* CONFIG_SMP */
 666         .name                   = "spapr",
 667 };
 668
 669 /*
 670  * get max priority from "/ibm,plat-res-int-priorities"
 671  */
 672 static bool xive_get_max_prio(u8 *max_prio)
 673 {
 674         struct device_node *rootdn;
 675         const __be32 *reg;
 676         u32 len;
 677         int prio, found;
 678
 679         rootdn = of_find_node_by_path("/");
 680         if (!rootdn) {
 681                 pr_err("not root node found !\n");
 682                 return false;
 683         }
 684
 685         reg = of_get_property(rootdn, "ibm,plat-res-int-priorities", &len);
 686         if (!reg) {
 687                 pr_err("Failed to read 'ibm,plat-res-int-priorities' property\n");
 688                 return false;
 689         }
 690
 691         if (len % (2 * sizeof(u32)) != 0) {
 692                 pr_err("invalid 'ibm,plat-res-int-priorities' property\n");
 693                 return false;
 694         }
 695
 696         /* HW supports priorities in the range [0-7] and 0xFF is a
 697          * wildcard priority used to mask. We scan the ranges reserved
 698          * by the hypervisor to find the lowest priority we can use.
 699          */
 700         found = 0xFF;
 701         for (prio = 0; prio < 8; prio++) {
 702                 int reserved = 0;
 703                 int i;
 704
 705                 for (i = 0; i < len / (2 * sizeof(u32)); i++) {
 706                         int base  = be32_to_cpu(reg[2 * i]);
 707                         int range = be32_to_cpu(reg[2 * i + 1]);
 708
 709                         if (prio >= base && prio < base + range)
 710                                 reserved++;
 711                 }
 712
 713                 if (!reserved)
 714                         found = prio;
 715         }
 716
 717         if (found == 0xFF) {
 718                 pr_err("no valid priority found in 'ibm,plat-res-int-priorities'\n");
 719                 return false;
 720         }
 721
 722         *max_prio = found;
 723         return true;
 724 }
 725
 726 static const u8 *get_vec5_feature(unsigned int index)
 727 {
 728         unsigned long root, chosen;
 729         int size;
 730         const u8 *vec5;
 731
 732         root = of_get_flat_dt_root();
 733         chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
 734         if (chosen == -FDT_ERR_NOTFOUND)
 735                 return NULL;
 736
 737         vec5 = of_get_flat_dt_prop(chosen, "ibm,architecture-vec-5", &size);
 738         if (!vec5)
 739                 return NULL;
 740
 741         if (size <= index)
 742                 return NULL;
 743
 744         return vec5 + index;
 745 }
 746
 747 static bool xive_spapr_disabled(void)
 748 {
 749         const u8 *vec5_xive;
 750
 751         vec5_xive = get_vec5_feature(OV5_INDX(OV5_XIVE_SUPPORT));
 752         if (vec5_xive) {
 753                 u8 val;
 754
 755                 val = *vec5_xive & OV5_FEAT(OV5_XIVE_SUPPORT);
 756                 switch (val) {
 757                 case OV5_FEAT(OV5_XIVE_EITHER):
 758                 case OV5_FEAT(OV5_XIVE_LEGACY):
 759                         break;
 760                 case OV5_FEAT(OV5_XIVE_EXPLOIT):
 761                         /* Hypervisor only supports XIVE */
 762                         if (xive_cmdline_disabled)
 763                                 pr_warn("WARNING: Ignoring cmdline option xive=off\n");
 764                         return false;
 765                 default:
 766                         pr_warn("%s: Unknown xive support option: 0x%x\n",
 767                                 __func__, val);
 768                         break;
 769                 }
 770         }
 771
 772         return xive_cmdline_disabled;
 773 }
 774
 775 bool __init xive_spapr_init(void)
 776 {
 777         struct device_node *np;
 778         struct resource r;
 779         void __iomem *tima;
 780         struct property *prop;
 781         u8 max_prio;
 782         u32 val;
 783         u32 len;
 784         const __be32 *reg;
 785         int i;
 786
 787         if (xive_spapr_disabled())
 788                 return false;
 789
 790         pr_devel("%s()\n", __func__);
 791         np = of_find_compatible_node(NULL, NULL, "ibm,power-ivpe");
 792         if (!np) {
 793                 pr_devel("not found !\n");
 794                 return false;
 795         }
 796         pr_devel("Found %s\n", np->full_name);
 797
 798         /* Resource 1 is the OS ring TIMA */
 799         if (of_address_to_resource(np, 1, &r)) {
 800                 pr_err("Failed to get thread mgmnt area resource\n");
 801                 return false;
 802         }
 803         tima = ioremap(r.start, resource_size(&r));
 804         if (!tima) {
 805                 pr_err("Failed to map thread mgmnt area\n");
 806                 return false;
 807         }
 808
 809         if (!xive_get_max_prio(&max_prio))
 810                 return false;
 811
 812         /* Feed the IRQ number allocator with the ranges given in the DT */
 813         reg = of_get_property(np, "ibm,xive-lisn-ranges", &len);
 814         if (!reg) {
 815                 pr_err("Failed to read 'ibm,xive-lisn-ranges' property\n");
 816                 return false;
 817         }
 818
 819         if (len % (2 * sizeof(u32)) != 0) {
 820                 pr_err("invalid 'ibm,xive-lisn-ranges' property\n");
 821                 return false;
 822         }
 823
 824         for (i = 0; i < len / (2 * sizeof(u32)); i++, reg += 2)
 825                 xive_irq_bitmap_add(be32_to_cpu(reg[0]),
 826                                     be32_to_cpu(reg[1]));
 827
 828         /* Iterate the EQ sizes and pick one */
 829         of_property_for_each_u32(np, "ibm,xive-eq-sizes", prop, reg, val) {
 830                 xive_queue_shift = val;
 831                 if (val == PAGE_SHIFT)
 832                         break;
 833         }
 834
 835         /* Initialize XIVE core with our backend */
 836         if (!xive_core_init(&xive_spapr_ops, tima, TM_QW1_OS, max_prio))
 837                 return false;
 838
 839         pr_info("Using %dkB queues\n", 1 << (xive_queue_shift - 10));
 840         return true;
 841 }