drivers/clk/at91/sama5d2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #include <linux/clk-provider.h>
   3 #include <linux/mfd/syscon.h>
   4 #include <linux/slab.h>
   5
   6 #include <dt-bindings/clock/at91.h>
   7
   8 #include "pmc.h"
   9
  10 static const struct clk_master_characteristics mck_characteristics = {
  11         .output = { .min = 124000000, .max = 166000000 },
  12         .divisors = { 1, 2, 4, 3 },
  13 };
  14
  15 static u8 plla_out[] = { 0 };
  16
  17 static u16 plla_icpll[] = { 0 };
  18
  19 static const struct clk_range plla_outputs[] = {
  20         { .min = 600000000, .max = 1200000000 },
  21 };
  22
  23 static const struct clk_pll_characteristics plla_characteristics = {
  24         .input = { .min = 12000000, .max = 24000000 },
  25         .num_output = ARRAY_SIZE(plla_outputs),
  26         .output = plla_outputs,
  27         .icpll = plla_icpll,
  28         .out = plla_out,
  29 };
  30
  31 static const struct clk_pcr_layout sama5d2_pcr_layout = {
  32         .offset = 0x10c,
  33         .cmd = BIT(12),
  34         .gckcss_mask = GENMASK(10, 8),
  35         .pid_mask = GENMASK(6, 0),
  36 };
  37
  38 static const struct {
  39         char *n;
  40         char *p;
  41         u8 id;
  42 } sama5d2_systemck[] = {
  43         { .n = "ddrck", .p = "masterck", .id = 2 },
  44         { .n = "lcdck", .p = "masterck", .id = 3 },
  45         { .n = "uhpck", .p = "usbck",    .id = 6 },
  46         { .n = "udpck", .p = "usbck",    .id = 7 },
  47         { .n = "pck0",  .p = "prog0",    .id = 8 },
  48         { .n = "pck1",  .p = "prog1",    .id = 9 },
  49         { .n = "pck2",  .p = "prog2",    .id = 10 },
  50         { .n = "iscck", .p = "masterck", .id = 18 },
  51 };
  52
  53 static const struct {
  54         char *n;
  55         u8 id;
  56         struct clk_range r;
  57 } sama5d2_periph32ck[] = {
  58         { .n = "macb0_clk",   .id = 5,  .r = { .min = 0, .max = 83000000 }, },
  59         { .n = "tdes_clk",    .id = 11, .r = { .min = 0, .max = 83000000 }, },
  60         { .n = "matrix1_clk", .id = 14, },
  61         { .n = "hsmc_clk",    .id = 17, },
  62         { .n = "pioA_clk",    .id = 18, .r = { .min = 0, .max = 83000000 }, },
  63         { .n = "flx0_clk",    .id = 19, .r = { .min = 0, .max = 83000000 }, },
  64         { .n = "flx1_clk",    .id = 20, .r = { .min = 0, .max = 83000000 }, },
  65         { .n = "flx2_clk",    .id = 21, .r = { .min = 0, .max = 83000000 }, },
  66         { .n = "flx3_clk",    .id = 22, .r = { .min = 0, .max = 83000000 }, },
  67         { .n = "flx4_clk",    .id = 23, .r = { .min = 0, .max = 83000000 }, },
  68         { .n = "uart0_clk",   .id = 24, .r = { .min = 0, .max = 83000000 }, },
  69         { .n = "uart1_clk",   .id = 25, .r = { .min = 0, .max = 83000000 }, },
  70         { .n = "uart2_clk",   .id = 26, .r = { .min = 0, .max = 83000000 }, },
  71         { .n = "uart3_clk",   .id = 27, .r = { .min = 0, .max = 83000000 }, },
  72         { .n = "uart4_clk",   .id = 28, .r = { .min = 0, .max = 83000000 }, },
  73         { .n = "twi0_clk",    .id = 29, .r = { .min = 0, .max = 83000000 }, },
  74         { .n = "twi1_clk",    .id = 30, .r = { .min = 0, .max = 83000000 }, },
  75         { .n = "spi0_clk",    .id = 33, .r = { .min = 0, .max = 83000000 }, },
  76         { .n = "spi1_clk",    .id = 34, .r = { .min = 0, .max = 83000000 }, },
  77         { .n = "tcb0_clk",    .id = 35, .r = { .min = 0, .max = 83000000 }, },
  78         { .n = "tcb1_clk",    .id = 36, .r = { .min = 0, .max = 83000000 }, },
  79         { .n = "pwm_clk",     .id = 38, .r = { .min = 0, .max = 83000000 }, },
  80         { .n = "adc_clk",     .id = 40, .r = { .min = 0, .max = 83000000 }, },
  81         { .n = "uhphs_clk",   .id = 41, .r = { .min = 0, .max = 83000000 }, },
  82         { .n = "udphs_clk",   .id = 42, .r = { .min = 0, .max = 83000000 }, },
  83         { .n = "ssc0_clk",    .id = 43, .r = { .min = 0, .max = 83000000 }, },
  84         { .n = "ssc1_clk",    .id = 44, .r = { .min = 0, .max = 83000000 }, },
  85         { .n = "trng_clk",    .id = 47, .r = { .min = 0, .max = 83000000 }, },
  86         { .n = "pdmic_clk",   .id = 48, .r = { .min = 0, .max = 83000000 }, },
  87         { .n = "securam_clk", .id = 51, },
  88         { .n = "i2s0_clk",    .id = 54, .r = { .min = 0, .max = 83000000 }, },
  89         { .n = "i2s1_clk",    .id = 55, .r = { .min = 0, .max = 83000000 }, },
  90         { .n = "can0_clk",    .id = 56, .r = { .min = 0, .max = 83000000 }, },
  91         { .n = "can1_clk",    .id = 57, .r = { .min = 0, .max = 83000000 }, },
  92         { .n = "classd_clk",  .id = 59, .r = { .min = 0, .max = 83000000 }, },
  93 };
  94
  95 static const struct {
  96         char *n;
  97         u8 id;
  98 } sama5d2_periphck[] = {
  99         { .n = "dma0_clk",    .id = 6, },
 100         { .n = "dma1_clk",    .id = 7, },
 101         { .n = "aes_clk",     .id = 9, },
 102         { .n = "aesb_clk",    .id = 10, },
 103         { .n = "sha_clk",     .id = 12, },
 104         { .n = "mpddr_clk",   .id = 13, },
 105         { .n = "matrix0_clk", .id = 15, },
 106         { .n = "sdmmc0_hclk", .id = 31, },
 107         { .n = "sdmmc1_hclk", .id = 32, },
 108         { .n = "lcdc_clk",    .id = 45, },
 109         { .n = "isc_clk",     .id = 46, },
 110         { .n = "qspi0_clk",   .id = 52, },
 111         { .n = "qspi1_clk",   .id = 53, },
 112 };
 113
 114 static const struct {
 115         char *n;
 116         u8 id;
 117         struct clk_range r;
 118         bool pll;
 119 } sama5d2_gck[] = {
 120         { .n = "sdmmc0_gclk", .id = 31, },
 121         { .n = "sdmmc1_gclk", .id = 32, },
 122         { .n = "tcb0_gclk",   .id = 35, .r = { .min = 0, .max = 83000000 }, },
 123         { .n = "tcb1_gclk",   .id = 36, .r = { .min = 0, .max = 83000000 }, },
 124         { .n = "pwm_gclk",    .id = 38, .r = { .min = 0, .max = 83000000 }, },
 125         { .n = "isc_gclk",    .id = 46, },
 126         { .n = "pdmic_gclk",  .id = 48, },
 127         { .n = "i2s0_gclk",   .id = 54, .pll = true },
 128         { .n = "i2s1_gclk",   .id = 55, .pll = true },
 129         { .n = "can0_gclk",   .id = 56, .r = { .min = 0, .max = 80000000 }, },
 130         { .n = "can1_gclk",   .id = 57, .r = { .min = 0, .max = 80000000 }, },
 131         { .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 100000000 },
 132           .pll = true },
 133 };
 134
 135 static const struct clk_programmable_layout sama5d2_programmable_layout = {
 136         .pres_mask = 0xff,
 137         .pres_shift = 4,
 138         .css_mask = 0x7,
 139         .have_slck_mck = 0,
 140         .is_pres_direct = 1,
 141 };
 142
 143 static void __init sama5d2_pmc_setup(struct device_node *np)
 144 {
 145         struct clk_range range = CLK_RANGE(0, 0);
 146         const char *slck_name, *mainxtal_name;
 147         struct pmc_data *sama5d2_pmc;
 148         const char *parent_names[6];
 149         struct regmap *regmap, *regmap_sfr;
 150         struct clk_hw *hw;
 151         int i;
 152         bool bypass;
 153
 154         i = of_property_match_string(np, "clock-names", "slow_clk");
 155         if (i < 0)
 156                 return;
 157
 158         slck_name = of_clk_get_parent_name(np, i);
 159
 160         i = of_property_match_string(np, "clock-names", "main_xtal");
 161         if (i < 0)
 162                 return;
 163         mainxtal_name = of_clk_get_parent_name(np, i);
 164
 165         regmap = device_node_to_regmap(np);
 166         if (IS_ERR(regmap))
 167                 return;
 168
 169         sama5d2_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
 170                                         nck(sama5d2_systemck),
 171                                         nck(sama5d2_periph32ck),
 172                                         nck(sama5d2_gck));
 173         if (!sama5d2_pmc)
 174                 return;
 175
 176         hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
 177                                            100000000);
 178         if (IS_ERR(hw))
 179                 goto err_free;
 180
 181         bypass = of_property_read_bool(np, "atmel,osc-bypass");
 182
 183         hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
 184                                         bypass);
 185         if (IS_ERR(hw))
 186                 goto err_free;
 187
 188         parent_names[0] = "main_rc_osc";
 189         parent_names[1] = "main_osc";
 190         hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
 191         if (IS_ERR(hw))
 192                 goto err_free;
 193
 194         sama5d2_pmc->chws[PMC_MAIN] = hw;
 195
 196         hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
 197                                    &sama5d3_pll_layout, &plla_characteristics);
 198         if (IS_ERR(hw))
 199                 goto err_free;
 200
 201         hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
 202         if (IS_ERR(hw))
 203                 goto err_free;
 204
 205         hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
 206                                               "mainck");
 207         if (IS_ERR(hw))
 208                 goto err_free;
 209
 210         hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
 211                                              "audiopll_fracck");
 212         if (IS_ERR(hw))
 213                 goto err_free;
 214
 215         hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
 216                                              "audiopll_fracck");
 217         if (IS_ERR(hw))
 218                 goto err_free;
 219
 220         regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
 221         if (IS_ERR(regmap_sfr))
 222                 regmap_sfr = NULL;
 223
 224         hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
 225         if (IS_ERR(hw))
 226                 goto err_free;
 227
 228         sama5d2_pmc->chws[PMC_UTMI] = hw;
 229
 230         parent_names[0] = slck_name;
 231         parent_names[1] = "mainck";
 232         parent_names[2] = "plladivck";
 233         parent_names[3] = "utmick";
 234         hw = at91_clk_register_master(regmap, "masterck", 4, parent_names,
 235                                       &at91sam9x5_master_layout,
 236                                       &mck_characteristics);
 237         if (IS_ERR(hw))
 238                 goto err_free;
 239
 240         sama5d2_pmc->chws[PMC_MCK] = hw;
 241
 242         hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck");
 243         if (IS_ERR(hw))
 244                 goto err_free;
 245
 246         sama5d2_pmc->chws[PMC_MCK2] = hw;
 247
 248         parent_names[0] = "plladivck";
 249         parent_names[1] = "utmick";
 250         hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
 251         if (IS_ERR(hw))
 252                 goto err_free;
 253
 254         parent_names[0] = slck_name;
 255         parent_names[1] = "mainck";
 256         parent_names[2] = "plladivck";
 257         parent_names[3] = "utmick";
 258         parent_names[4] = "masterck";
 259         parent_names[5] = "audiopll_pmcck";
 260         for (i = 0; i < 3; i++) {
 261                 char name[6];
 262
 263                 snprintf(name, sizeof(name), "prog%d", i);
 264
 265                 hw = at91_clk_register_programmable(regmap, name,
 266                                                     parent_names, 6, i,
 267                                                     &sama5d2_programmable_layout);
 268                 if (IS_ERR(hw))
 269                         goto err_free;
 270         }
 271
 272         for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
 273                 hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
 274                                               sama5d2_systemck[i].p,
 275                                               sama5d2_systemck[i].id);
 276                 if (IS_ERR(hw))
 277                         goto err_free;
 278
 279                 sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
 280         }
 281
 282         for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
 283                 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 284                                                          &sama5d2_pcr_layout,
 285                                                          sama5d2_periphck[i].n,
 286                                                          "masterck",
 287                                                          sama5d2_periphck[i].id,
 288                                                          &range);
 289                 if (IS_ERR(hw))
 290                         goto err_free;
 291
 292                 sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
 293         }
 294
 295         for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
 296                 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
 297                                                          &sama5d2_pcr_layout,
 298                                                          sama5d2_periph32ck[i].n,
 299                                                          "h32mxck",
 300                                                          sama5d2_periph32ck[i].id,
 301                                                          &sama5d2_periph32ck[i].r);
 302                 if (IS_ERR(hw))
 303                         goto err_free;
 304
 305                 sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
 306         }
 307
 308         parent_names[0] = slck_name;
 309         parent_names[1] = "mainck";
 310         parent_names[2] = "plladivck";
 311         parent_names[3] = "utmick";
 312         parent_names[4] = "masterck";
 313         parent_names[5] = "audiopll_pmcck";
 314         for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
 315                 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
 316                                                  &sama5d2_pcr_layout,
 317                                                  sama5d2_gck[i].n,
 318                                                  parent_names, 6,
 319                                                  sama5d2_gck[i].id,
 320                                                  sama5d2_gck[i].pll,
 321                                                  &sama5d2_gck[i].r);
 322                 if (IS_ERR(hw))
 323                         goto err_free;
 324
 325                 sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
 326         }
 327
 328         if (regmap_sfr) {
 329                 parent_names[0] = "i2s0_clk";
 330                 parent_names[1] = "i2s0_gclk";
 331                 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
 332                                                parent_names, 2, 0);
 333                 if (IS_ERR(hw))
 334                         goto err_free;
 335
 336                 sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
 337
 338                 parent_names[0] = "i2s1_clk";
 339                 parent_names[1] = "i2s1_gclk";
 340                 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
 341                                                parent_names, 2, 1);
 342                 if (IS_ERR(hw))
 343                         goto err_free;
 344
 345                 sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
 346         }
 347
 348         of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
 349
 350         return;
 351
 352 err_free:
 353         pmc_data_free(sama5d2_pmc);
 354 }
 355 CLK_OF_DECLARE_DRIVER(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);