dm writecache: fix incorrect flush sequence when doing SSD mode commit
[linux/fpc-iii.git] / drivers / clk / hisilicon / clk-hip04.c
blob785b9faf3ea59a4f471f6c49698f589c46a4ae92
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Hisilicon HiP04 clock driver
5 * Copyright (c) 2013-2014 Hisilicon Limited.
6 * Copyright (c) 2013-2014 Linaro Limited.
8 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
9 */
11 #include <linux/kernel.h>
12 #include <linux/clk-provider.h>
13 #include <linux/io.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/slab.h>
19 #include <dt-bindings/clock/hip04-clock.h>
21 #include "clk.h"
23 /* fixed rate clocks */
24 static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
25 { HIP04_OSC50M, "osc50m", NULL, 0, 50000000, },
26 { HIP04_CLK_50M, "clk50m", NULL, 0, 50000000, },
27 { HIP04_CLK_168M, "clk168m", NULL, 0, 168750000, },
30 static void __init hip04_clk_init(struct device_node *np)
32 struct hisi_clock_data *clk_data;
34 clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
35 if (!clk_data)
36 return;
38 hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
39 ARRAY_SIZE(hip04_fixed_rate_clks),
40 clk_data);
42 CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);