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dm writecache: fix incorrect flush sequence when doing SSD mode commit
[linux/fpc-iii.git] / drivers / clk / samsung / clk-exynos5420.c
blob3a991ca1ee3605af87831a603914db9ee3fe5deb
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
4 * Authors: Thomas Abraham <thomas.ab@samsung.com>
5 * Chander Kashyap <k.chander@samsung.com>
6 *
7 * Common Clock Framework support for Exynos5420 SoC.
8 */
9
10 #include <dt-bindings/clock/exynos5420.h>
11 #include <linux/slab.h>
12 #include <linux/clk-provider.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15
16 #include "clk.h"
17 #include "clk-cpu.h"
18 #include "clk-exynos5-subcmu.h"
19
20 #define APLL_LOCK 0x0
21 #define APLL_CON0 0x100
22 #define SRC_CPU 0x200
23 #define DIV_CPU0 0x500
24 #define DIV_CPU1 0x504
25 #define GATE_BUS_CPU 0x700
26 #define GATE_SCLK_CPU 0x800
27 #define CLKOUT_CMU_CPU 0xa00
28 #define SRC_MASK_CPERI 0x4300
29 #define GATE_IP_G2D 0x8800
30 #define CPLL_LOCK 0x10020
31 #define DPLL_LOCK 0x10030
32 #define EPLL_LOCK 0x10040
33 #define RPLL_LOCK 0x10050
34 #define IPLL_LOCK 0x10060
35 #define SPLL_LOCK 0x10070
36 #define VPLL_LOCK 0x10080
37 #define MPLL_LOCK 0x10090
38 #define CPLL_CON0 0x10120
39 #define DPLL_CON0 0x10128
40 #define EPLL_CON0 0x10130
41 #define EPLL_CON1 0x10134
42 #define EPLL_CON2 0x10138
43 #define RPLL_CON0 0x10140
44 #define RPLL_CON1 0x10144
45 #define RPLL_CON2 0x10148
46 #define IPLL_CON0 0x10150
47 #define SPLL_CON0 0x10160
48 #define VPLL_CON0 0x10170
49 #define MPLL_CON0 0x10180
50 #define SRC_TOP0 0x10200
51 #define SRC_TOP1 0x10204
52 #define SRC_TOP2 0x10208
53 #define SRC_TOP3 0x1020c
54 #define SRC_TOP4 0x10210
55 #define SRC_TOP5 0x10214
56 #define SRC_TOP6 0x10218
57 #define SRC_TOP7 0x1021c
58 #define SRC_TOP8 0x10220 /* 5800 specific */
59 #define SRC_TOP9 0x10224 /* 5800 specific */
60 #define SRC_DISP10 0x1022c
61 #define SRC_MAU 0x10240
62 #define SRC_FSYS 0x10244
63 #define SRC_PERIC0 0x10250
64 #define SRC_PERIC1 0x10254
65 #define SRC_ISP 0x10270
66 #define SRC_CAM 0x10274 /* 5800 specific */
67 #define SRC_TOP10 0x10280
68 #define SRC_TOP11 0x10284
69 #define SRC_TOP12 0x10288
70 #define SRC_TOP13 0x1028c /* 5800 specific */
71 #define SRC_MASK_TOP0 0x10300
72 #define SRC_MASK_TOP1 0x10304
73 #define SRC_MASK_TOP2 0x10308
74 #define SRC_MASK_TOP7 0x1031c
75 #define SRC_MASK_DISP10 0x1032c
76 #define SRC_MASK_MAU 0x10334
77 #define SRC_MASK_FSYS 0x10340
78 #define SRC_MASK_PERIC0 0x10350
79 #define SRC_MASK_PERIC1 0x10354
80 #define SRC_MASK_ISP 0x10370
81 #define DIV_TOP0 0x10500
82 #define DIV_TOP1 0x10504
83 #define DIV_TOP2 0x10508
84 #define DIV_TOP8 0x10520 /* 5800 specific */
85 #define DIV_TOP9 0x10524 /* 5800 specific */
86 #define DIV_DISP10 0x1052c
87 #define DIV_MAU 0x10544
88 #define DIV_FSYS0 0x10548
89 #define DIV_FSYS1 0x1054c
90 #define DIV_FSYS2 0x10550
91 #define DIV_PERIC0 0x10558
92 #define DIV_PERIC1 0x1055c
93 #define DIV_PERIC2 0x10560
94 #define DIV_PERIC3 0x10564
95 #define DIV_PERIC4 0x10568
96 #define DIV_CAM 0x10574 /* 5800 specific */
97 #define SCLK_DIV_ISP0 0x10580
98 #define SCLK_DIV_ISP1 0x10584
99 #define DIV2_RATIO0 0x10590
100 #define DIV4_RATIO 0x105a0
101 #define GATE_BUS_TOP 0x10700
102 #define GATE_BUS_DISP1 0x10728
103 #define GATE_BUS_GEN 0x1073c
104 #define GATE_BUS_FSYS0 0x10740
105 #define GATE_BUS_FSYS2 0x10748
106 #define GATE_BUS_PERIC 0x10750
107 #define GATE_BUS_PERIC1 0x10754
108 #define GATE_BUS_PERIS0 0x10760
109 #define GATE_BUS_PERIS1 0x10764
110 #define GATE_BUS_NOC 0x10770
111 #define GATE_TOP_SCLK_ISP 0x10870
112 #define GATE_IP_GSCL0 0x10910
113 #define GATE_IP_GSCL1 0x10920
114 #define GATE_IP_CAM 0x10924 /* 5800 specific */
115 #define GATE_IP_MFC 0x1092c
116 #define GATE_IP_DISP1 0x10928
117 #define GATE_IP_G3D 0x10930
118 #define GATE_IP_GEN 0x10934
119 #define GATE_IP_FSYS 0x10944
120 #define GATE_IP_PERIC 0x10950
121 #define GATE_IP_PERIS 0x10960
122 #define GATE_IP_MSCL 0x10970
123 #define GATE_TOP_SCLK_GSCL 0x10820
124 #define GATE_TOP_SCLK_DISP1 0x10828
125 #define GATE_TOP_SCLK_MAU 0x1083c
126 #define GATE_TOP_SCLK_FSYS 0x10840
127 #define GATE_TOP_SCLK_PERIC 0x10850
128 #define TOP_SPARE2 0x10b08
129 #define BPLL_LOCK 0x20010
130 #define BPLL_CON0 0x20110
131 #define SRC_CDREX 0x20200
132 #define DIV_CDREX0 0x20500
133 #define DIV_CDREX1 0x20504
134 #define GATE_BUS_CDREX0 0x20700
135 #define GATE_BUS_CDREX1 0x20704
136 #define KPLL_LOCK 0x28000
137 #define KPLL_CON0 0x28100
138 #define SRC_KFC 0x28200
139 #define DIV_KFC0 0x28500
140
141 /* Exynos5x SoC type */
142 enum exynos5x_soc {
143 EXYNOS5420,
144 EXYNOS5800,
145 };
146
147 /* list of PLLs */
148 enum exynos5x_plls {
149 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
150 bpll, kpll,
151 nr_plls /* number of PLLs */
152 };
153
154 static void __iomem *reg_base;
155 static enum exynos5x_soc exynos5x_soc;
156
157 /*
158 * list of controller registers to be saved and restored during a
159 * suspend/resume cycle.
160 */
161 static const unsigned long exynos5x_clk_regs[] __initconst = {
162 SRC_CPU,
163 DIV_CPU0,
164 DIV_CPU1,
165 GATE_BUS_CPU,
166 GATE_SCLK_CPU,
167 CLKOUT_CMU_CPU,
168 APLL_CON0,
169 KPLL_CON0,
170 CPLL_CON0,
171 DPLL_CON0,
172 EPLL_CON0,
173 EPLL_CON1,
174 EPLL_CON2,
175 RPLL_CON0,
176 RPLL_CON1,
177 RPLL_CON2,
178 IPLL_CON0,
179 SPLL_CON0,
180 VPLL_CON0,
181 MPLL_CON0,
182 SRC_TOP0,
183 SRC_TOP1,
184 SRC_TOP2,
185 SRC_TOP3,
186 SRC_TOP4,
187 SRC_TOP5,
188 SRC_TOP6,
189 SRC_TOP7,
190 SRC_DISP10,
191 SRC_MAU,
192 SRC_FSYS,
193 SRC_PERIC0,
194 SRC_PERIC1,
195 SRC_TOP10,
196 SRC_TOP11,
197 SRC_TOP12,
198 SRC_MASK_TOP2,
199 SRC_MASK_TOP7,
200 SRC_MASK_DISP10,
201 SRC_MASK_FSYS,
202 SRC_MASK_PERIC0,
203 SRC_MASK_PERIC1,
204 SRC_MASK_TOP0,
205 SRC_MASK_TOP1,
206 SRC_MASK_MAU,
207 SRC_MASK_ISP,
208 SRC_ISP,
209 DIV_TOP0,
210 DIV_TOP1,
211 DIV_TOP2,
212 DIV_DISP10,
213 DIV_MAU,
214 DIV_FSYS0,
215 DIV_FSYS1,
216 DIV_FSYS2,
217 DIV_PERIC0,
218 DIV_PERIC1,
219 DIV_PERIC2,
220 DIV_PERIC3,
221 DIV_PERIC4,
222 SCLK_DIV_ISP0,
223 SCLK_DIV_ISP1,
224 DIV2_RATIO0,
225 DIV4_RATIO,
226 GATE_BUS_DISP1,
227 GATE_BUS_TOP,
228 GATE_BUS_GEN,
229 GATE_BUS_FSYS0,
230 GATE_BUS_FSYS2,
231 GATE_BUS_PERIC,
232 GATE_BUS_PERIC1,
233 GATE_BUS_PERIS0,
234 GATE_BUS_PERIS1,
235 GATE_BUS_NOC,
236 GATE_TOP_SCLK_ISP,
237 GATE_IP_GSCL0,
238 GATE_IP_GSCL1,
239 GATE_IP_MFC,
240 GATE_IP_DISP1,
241 GATE_IP_G3D,
242 GATE_IP_GEN,
243 GATE_IP_FSYS,
244 GATE_IP_PERIC,
245 GATE_IP_PERIS,
246 GATE_IP_MSCL,
247 GATE_TOP_SCLK_GSCL,
248 GATE_TOP_SCLK_DISP1,
249 GATE_TOP_SCLK_MAU,
250 GATE_TOP_SCLK_FSYS,
251 GATE_TOP_SCLK_PERIC,
252 TOP_SPARE2,
253 SRC_CDREX,
254 DIV_CDREX0,
255 DIV_CDREX1,
256 SRC_KFC,
257 DIV_KFC0,
258 GATE_BUS_CDREX0,
259 GATE_BUS_CDREX1,
260 };
261
262 static const unsigned long exynos5800_clk_regs[] __initconst = {
263 SRC_TOP8,
264 SRC_TOP9,
265 SRC_CAM,
266 SRC_TOP1,
267 DIV_TOP8,
268 DIV_TOP9,
269 DIV_CAM,
270 GATE_IP_CAM,
271 };
272
273 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
274 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
275 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
276 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
277 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
278 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
279 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
280 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
281 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
282 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
283 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
284 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
285 { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
286 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
287 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
288 { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
289 };
290
291 /* list of all parent clocks */
292 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
293 "mout_sclk_mpll", "mout_sclk_spll"};
294 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
295 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
296 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
297 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
298 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
299 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
300 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
301 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
302 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
303 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
304 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
305 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
306 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
307
308 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
309 "mout_sclk_mpll"};
310 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
311 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
312 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
313 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
314 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
315 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
316
317 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
318 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
319 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
320 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
321
322 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
323 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
324 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
325 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
326
327 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
328 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
329 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
330 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
331
332 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
333 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
334 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
335
336 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
337 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
338
339 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
340 "mout_sclk_spll"};
341 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
342
343 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
344 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
345
346 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
347 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
348
349 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
350 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
351
352 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
353 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
354
355 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
356 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
357
358 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
359 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
360 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
361
362 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
363 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
364
365 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
366 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
367
368 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
369 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
370 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
371 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
372
373 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
374 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
375
376 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
377 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
378
379 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
380 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
381
382 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
383 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
384
385 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
386 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
387 "mout_sclk_epll", "mout_sclk_rpll"};
388 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
389 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
390 "mout_sclk_epll", "mout_sclk_rpll"};
391 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
392 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
393 "mout_sclk_epll", "mout_sclk_rpll"};
394 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
395 "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
396 "mout_sclk_epll", "mout_sclk_rpll"};
397 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
398 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
399 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
400 "mout_sclk_epll", "mout_sclk_rpll"};
401 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
402 "mout_sclk_mpll", "mout_sclk_spll"};
403 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
404
405 /* List of parents specific to exynos5800 */
406 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
407 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
408 "mout_sclk_mpll", "ff_dout_spll2" };
409 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
410 "mout_sclk_mpll", "ff_dout_spll2",
411 "mout_epll2", "mout_sclk_ipll" };
412 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
413 "mout_sclk_mpll", "ff_dout_spll2",
414 "mout_epll2" };
415 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
416 "mout_sclk_mpll", "mout_sclk_spll" };
417 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
418 "mout_sclk_mpll", "ff_dout_spll2" };
419 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
420 "mout_sclk_mpll", "mout_sclk_spll",
421 "mout_epll2", "mout_sclk_ipll" };
422 PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll",
423 "mout_sclk_mpll", "ff_dout_spll2",
424 "mout_sclk_spll", "mout_sclk_epll"};
425 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
426 "mout_sclk_mpll",
427 "ff_dout_spll2" };
428 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
429 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
430 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
431 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
432 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
433 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
434 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
435 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
436 PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
437 PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
438 "mout_sclk_mpll", "ff_dout_spll2",
439 "mout_sclk_spll", "mout_sclk_epll"};
440
441 /* fixed rate clocks generated outside the soc */
442 static struct samsung_fixed_rate_clock
443 exynos5x_fixed_rate_ext_clks[] __initdata = {
444 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
445 };
446
447 /* fixed rate clocks generated inside the soc */
448 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
449 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
450 FRATE(0, "sclk_pwi", NULL, 0, 24000000),
451 FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
452 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
453 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
454 };
455
456 static const struct samsung_fixed_factor_clock
457 exynos5x_fixed_factor_clks[] __initconst = {
458 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
459 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
460 };
461
462 static const struct samsung_fixed_factor_clock
463 exynos5800_fixed_factor_clks[] __initconst = {
464 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
465 FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
466 };
467
468 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
469 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
470 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
471 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
472 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
473
474 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
475 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
476 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
477 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
478 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
479
480 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
481 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
482 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
483 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
484 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
485 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
486
487 MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy",
488 mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3),
489
490 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
491 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3),
492 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
493 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
494 MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
495 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
496
497 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
498 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
499 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
500 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
501
502 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
503 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
504 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
505 SRC_TOP9, 16, 1),
506 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
507 SRC_TOP9, 20, 1),
508 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
509 SRC_TOP9, 24, 1),
510 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
511 SRC_TOP9, 28, 1),
512
513 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
514 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
515 SRC_TOP13, 20, 1),
516 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
517 SRC_TOP13, 24, 1),
518 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
519 SRC_TOP13, 28, 1),
520
521 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
522 };
523
524 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
525 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
526 "mout_aclk400_wcore", DIV_TOP0, 16, 3),
527 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
528 DIV_TOP8, 16, 3),
529 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
530 DIV_TOP8, 20, 3),
531 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
532 DIV_TOP8, 24, 3),
533 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
534 DIV_TOP8, 28, 3),
535
536 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
537 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
538 };
539
540 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
541 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
542 GATE_BUS_TOP, 24, 0, 0),
543 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
544 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
545 };
546
547 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
548 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
549 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
550 TOP_SPARE2, 4, 1),
551
552 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
553 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
554 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
555 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
556
557 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
558 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
559 SRC_TOP1, 4, 2),
560 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
561 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
562 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
563
564 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
565 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
566 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
567 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
568 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
569 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
570
571 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
572 mout_group5_5800_p, SRC_TOP7, 16, 2),
573 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
574 CLK_SET_RATE_PARENT, 0),
575
576 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
577 };
578
579 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
580 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
581 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
582 };
583
584 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
585 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
586 /* Maudio Block */
587 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
588 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
589 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
590 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
591 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
592 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
593 };
594
595 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
596 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
597 SRC_TOP7, 4, 1),
598 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
599 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
600
601 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
602 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
603 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
604 MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
605 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
606 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
607
608 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
609 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
610 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
611 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
612
613 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
614 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
615
616 MUX_F(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1,
617 CLK_SET_RATE_PARENT, 0),
618
619 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
620 SRC_TOP3, 0, 1),
621 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
622 SRC_TOP3, 4, 1),
623 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
624 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
625 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
626 SRC_TOP3, 12, 1),
627 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
628 SRC_TOP3, 16, 1),
629 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
630 SRC_TOP3, 20, 1),
631 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
632 SRC_TOP3, 24, 1),
633 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
634 SRC_TOP3, 28, 1),
635
636 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
637 SRC_TOP4, 0, 1),
638 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
639 SRC_TOP4, 4, 1),
640 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
641 SRC_TOP4, 8, 1),
642 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
643 SRC_TOP4, 12, 1),
644 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
645 SRC_TOP4, 16, 1),
646 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
647 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
648 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
649 SRC_TOP4, 28, 1),
650
651 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
652 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
653 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
654 SRC_TOP5, 4, 1),
655 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
656 SRC_TOP5, 8, 1),
657 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
658 SRC_TOP5, 12, 1),
659 MUX_F(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
660 SRC_TOP5, 16, 1, CLK_SET_RATE_PARENT, 0),
661 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
662 SRC_TOP5, 20, 1),
663 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
664 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
665 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
666 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
667
668 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
669 MUX_F(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1,
670 CLK_SET_RATE_PARENT, 0),
671 MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
672 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
673 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
674 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
675 CLK_SET_RATE_PARENT, 0),
676 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
677 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
678
679 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
680 SRC_TOP10, 0, 1),
681 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
682 SRC_TOP10, 4, 1),
683 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
684 SRC_TOP10, 8, 1),
685 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
686 SRC_TOP10, 12, 1),
687 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
688 SRC_TOP10, 16, 1),
689 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
690 SRC_TOP10, 20, 1),
691 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
692 SRC_TOP10, 24, 1),
693 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
694 SRC_TOP10, 28, 1),
695
696 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
697 SRC_TOP11, 0, 1),
698 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
699 SRC_TOP11, 4, 1),
700 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
701 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
702 SRC_TOP11, 12, 1),
703 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
704 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
705 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
706 SRC_TOP11, 28, 1),
707
708 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
709 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
710 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
711 SRC_TOP12, 8, 1),
712 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
713 SRC_TOP12, 12, 1),
714 MUX_F(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1,
715 CLK_SET_RATE_PARENT, 0),
716 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
717 SRC_TOP12, 20, 1),
718 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
719 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
720 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
721 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
722
723 /* DISP1 Block */
724 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
725 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
726 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
727 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
728 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
729
730 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
731
732 /* CDREX block */
733 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
734 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
735 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
736 CLK_SET_RATE_PARENT, 0),
737
738 /* MAU Block */
739 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
740
741 /* FSYS Block */
742 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
743 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
744 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
745 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
746 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
747 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
748 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
749
750 /* PERIC Block */
751 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
752 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
753 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
754 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
755 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
756 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
757 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
758 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
759 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
760 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
761 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
762 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
763
764 /* ISP Block */
765 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
766 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
767 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
768 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
769 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
770 };
771
772 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
773 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
774 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
775 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
776 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
777 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
778
779 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
780 DIV_TOP0, 0, 3),
781 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
782 DIV_TOP0, 4, 3),
783 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
784 DIV_TOP0, 8, 3),
785 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
786 DIV_TOP0, 12, 3),
787 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
788 DIV_TOP0, 20, 3),
789 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
790 DIV_TOP0, 24, 3),
791 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
792 DIV_TOP0, 28, 3),
793 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
794 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
795 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
796 "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
797 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
798 DIV_TOP1, 8, 6),
799 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
800 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
801 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
802 DIV_TOP1, 20, 3),
803 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
804 DIV_TOP1, 24, 3),
805 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
806 DIV_TOP1, 28, 3),
807
808 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
809 DIV_TOP2, 8, 3),
810 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
811 DIV_TOP2, 12, 3),
812 DIV_F(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
813 16, 3, CLK_SET_RATE_PARENT, 0),
814 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
815 DIV_TOP2, 20, 3),
816 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
817 "mout_aclk300_disp1", DIV_TOP2, 24, 3),
818 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
819 DIV_TOP2, 28, 3),
820
821 /* DISP1 Block */
822 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
823 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
824 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
825 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
826 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
827 "mout_aclk400_disp1", DIV_TOP2, 4, 3),
828
829 /* CDREX Block */
830 /*
831 * The three clocks below are controlled using the same register and
832 * bits. They are put into one because there is a need of
833 * synchronization between the BUS and DREXs (two external memory
834 * interfaces).
835 * They are put here to show this HW assumption and for clock
836 * information summary completeness.
837 */
838 DIV_F(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
839 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
840 DIV_F(CLK_DOUT_PCLK_DREX0, "dout_pclk_drex0", "dout_cclk_drex0",
841 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
842 DIV_F(CLK_DOUT_PCLK_DREX1, "dout_pclk_drex1", "dout_cclk_drex0",
843 DIV_CDREX0, 28, 3, CLK_GET_RATE_NOCACHE, 0),
844
845 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
846 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
847 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
848 DIV_CDREX0, 16, 3),
849 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
850 DIV_CDREX0, 8, 3),
851 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
852 DIV_CDREX0, 3, 5),
853
854 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
855 DIV_CDREX1, 8, 3),
856
857 /* Audio Block */
858 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
859 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
860
861 /* USB3.0 */
862 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
863 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
864 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
865 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
866
867 /* MMC */
868 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
869 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
870 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
871
872 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
873 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
874
875 /* UART and PWM */
876 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
877 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
878 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
879 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
880 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
881
882 /* SPI */
883 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
884 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
885 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
886
887
888 /* PCM */
889 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
890 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
891
892 /* Audio - I2S */
893 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
894 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
895 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
896 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
897 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
898
899 /* SPI Pre-Ratio */
900 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
901 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
902 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
903
904 /* GSCL Block */
905 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
906
907 /* PSGEN */
908 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
909 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
910
911 /* ISP Block */
912 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
913 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
914 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
915 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
916 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
917 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
918 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
919 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
920 CLK_SET_RATE_PARENT, 0),
921 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
922 CLK_SET_RATE_PARENT, 0),
923 };
924
925 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
926 /* G2D */
927 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
928 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
929 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
930 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
931 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
932
933 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
934 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
935 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
936 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
937
938 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
939 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
940 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
941 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
942 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
943 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
944 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
945 GATE_BUS_TOP, 5, 0, 0),
946 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
947 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
948 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
949 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
950 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
951 GATE_BUS_TOP, 8, 0, 0),
952 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
953 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
954 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
955 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
956 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
957 GATE_BUS_TOP, 13, 0, 0),
958 GATE(0, "aclk166", "mout_user_aclk166",
959 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
960 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
961 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
962 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
963 GATE_BUS_TOP, 16, 0, 0),
964 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
965 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
966 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
967 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
968 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
969 GATE_BUS_TOP, 28, 0, 0),
970 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
971 GATE_BUS_TOP, 29, 0, 0),
972
973 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
974 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
975
976 /* sclk */
977 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
978 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
979 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
980 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
981 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
982 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
983 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
984 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
985 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
986 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
987 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
988 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
989 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
990 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
991 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
992 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
993 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
994 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
995 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
996 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
997 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
998 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
999 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
1000 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
1001 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
1002 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
1003
1004 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
1005 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
1006 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
1007 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
1008 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
1009 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1010 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
1011 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
1012 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
1013 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
1014 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
1015 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
1016 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
1017 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1018
1019 /* Display */
1020 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
1021 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1022 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
1023 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1024 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
1025 GATE_TOP_SCLK_DISP1, 9, 0, 0),
1026 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
1027 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1028 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1029 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1030
1031 /* FSYS Block */
1032 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1033 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1034 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1035 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1036 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1037 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1038 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1039 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1040 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1041 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1042 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1043 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1044 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1045 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1046 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1047
1048 /* PERIC Block */
1049 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1050 GATE_IP_PERIC, 0, 0, 0),
1051 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1052 GATE_IP_PERIC, 1, 0, 0),
1053 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1054 GATE_IP_PERIC, 2, 0, 0),
1055 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1056 GATE_IP_PERIC, 3, 0, 0),
1057 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1058 GATE_IP_PERIC, 6, 0, 0),
1059 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1060 GATE_IP_PERIC, 7, 0, 0),
1061 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1062 GATE_IP_PERIC, 8, 0, 0),
1063 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1064 GATE_IP_PERIC, 9, 0, 0),
1065 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1066 GATE_IP_PERIC, 10, 0, 0),
1067 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1068 GATE_IP_PERIC, 11, 0, 0),
1069 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1070 GATE_IP_PERIC, 12, 0, 0),
1071 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1072 GATE_IP_PERIC, 13, 0, 0),
1073 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1074 GATE_IP_PERIC, 14, 0, 0),
1075 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1076 GATE_IP_PERIC, 15, 0, 0),
1077 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1078 GATE_IP_PERIC, 16, 0, 0),
1079 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1080 GATE_IP_PERIC, 17, 0, 0),
1081 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1082 GATE_IP_PERIC, 18, 0, 0),
1083 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1084 GATE_IP_PERIC, 20, 0, 0),
1085 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1086 GATE_IP_PERIC, 21, 0, 0),
1087 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1088 GATE_IP_PERIC, 22, 0, 0),
1089 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1090 GATE_IP_PERIC, 23, 0, 0),
1091 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1092 GATE_IP_PERIC, 24, 0, 0),
1093 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1094 GATE_IP_PERIC, 26, 0, 0),
1095 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1096 GATE_IP_PERIC, 28, 0, 0),
1097 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1098 GATE_IP_PERIC, 30, 0, 0),
1099 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1100 GATE_IP_PERIC, 31, 0, 0),
1101
1102 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1103 GATE_BUS_PERIC, 22, 0, 0),
1104
1105 /* PERIS Block */
1106 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1107 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1108 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1109 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1110 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1111 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1112 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1113 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1114 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1115 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1116 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1117 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1118 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1119 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1120 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1121 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1122 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1123 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1124 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1125 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1126
1127 /* GEN Block */
1128 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1129 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1130 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1131 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1132 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1133 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1134 GATE_IP_GEN, 6, 0, 0),
1135 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1136 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1137 GATE_IP_GEN, 9, 0, 0),
1138
1139 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1140 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1141 GATE_BUS_GEN, 28, 0, 0),
1142 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1143
1144 /* GSCL Block */
1145 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1146 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1147 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1148 GATE_TOP_SCLK_GSCL, 7, 0, 0),
1149
1150 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1151 GATE_IP_GSCL0, 4, 0, 0),
1152 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1153 GATE_IP_GSCL0, 5, 0, 0),
1154 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1155 GATE_IP_GSCL0, 6, 0, 0),
1156
1157 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1158 GATE_IP_GSCL1, 2, 0, 0),
1159 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1160 GATE_IP_GSCL1, 3, 0, 0),
1161 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1162 GATE_IP_GSCL1, 4, 0, 0),
1163 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12, 0, 0),
1164 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13, 0, 0),
1165 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1166 GATE_IP_GSCL1, 16, 0, 0),
1167 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1168 GATE_IP_GSCL1, 17, 0, 0),
1169
1170 /* ISP */
1171 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1172 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1173 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1174 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1175 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1176 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1177 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1178 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1179 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1180 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1181 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1182 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1183 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1184 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1185
1186 /* CDREX */
1187 GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex",
1188 GATE_BUS_CDREX0, 0, 0, 0),
1189 GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex",
1190 GATE_BUS_CDREX0, 1, 0, 0),
1191 GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy",
1192 SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0),
1193
1194 GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1",
1195 GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0),
1196 GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1",
1197 GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0),
1198 GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1",
1199 GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0),
1200 GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1",
1201 GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0),
1202
1203 GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex",
1204 GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0),
1205 GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex",
1206 GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0),
1207 GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex",
1208 GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0),
1209 GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex",
1210 GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0),
1211 };
1212
1213 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
1214 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1215 };
1216
1217 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
1218 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1219 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1220 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1221 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1222 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1223 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1224 GATE_IP_DISP1, 7, 0, 0),
1225 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1226 GATE_IP_DISP1, 8, 0, 0),
1227 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1228 GATE_IP_DISP1, 9, 0, 0),
1229 };
1230
1231 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
1232 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1233 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
1234 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
1235 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
1236 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
1237 };
1238
1239 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
1240 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1241 DIV2_RATIO0, 4, 2),
1242 };
1243
1244 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
1245 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1246 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1247 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1248 GATE_IP_GSCL1, 6, 0, 0),
1249 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1250 GATE_IP_GSCL1, 7, 0, 0),
1251 };
1252
1253 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
1254 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
1255 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
1256 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
1257 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
1258 };
1259
1260 static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
1261 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
1262 CLK_SET_RATE_PARENT, 0),
1263 };
1264
1265 static struct exynos5_subcmu_reg_dump exynos5x_g3d_suspend_regs[] = {
1266 { GATE_IP_G3D, 0x3ff, 0x3ff }, /* G3D gates */
1267 { SRC_TOP5, 0, BIT(16) }, /* MUX mout_user_aclk_g3d */
1268 };
1269
1270 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
1271 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1272 };
1273
1274 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
1275 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1276 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1277 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1278 };
1279
1280 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
1281 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1282 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
1283 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
1284 };
1285
1286 static const struct samsung_gate_clock exynos5x_mscl_gate_clks[] __initconst = {
1287 /* MSCL Block */
1288 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1289 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1290 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1291 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1292 GATE_IP_MSCL, 8, 0, 0),
1293 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1294 GATE_IP_MSCL, 9, 0, 0),
1295 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1296 GATE_IP_MSCL, 10, 0, 0),
1297 };
1298
1299 static const struct samsung_div_clock exynos5x_mscl_div_clks[] __initconst = {
1300 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
1301 };
1302
1303 static struct exynos5_subcmu_reg_dump exynos5x_mscl_suspend_regs[] = {
1304 { GATE_IP_MSCL, 0xffffffff, 0xffffffff }, /* MSCL gates */
1305 { SRC_TOP3, 0, BIT(4) }, /* MUX mout_user_aclk400_mscl */
1306 { DIV2_RATIO0, 0, 0x30000000 }, /* DIV dout_mscl_blk */
1307 };
1308
1309 static const struct samsung_gate_clock exynos5800_mau_gate_clks[] __initconst = {
1310 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
1311 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
1312 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1313 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1314 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1315 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1316 };
1317
1318 static struct exynos5_subcmu_reg_dump exynos5800_mau_suspend_regs[] = {
1319 { SRC_TOP9, 0, BIT(8) }, /* MUX mout_user_mau_epll */
1320 };
1321
1322 static const struct exynos5_subcmu_info exynos5x_disp_subcmu = {
1323 .div_clks = exynos5x_disp_div_clks,
1324 .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
1325 .gate_clks = exynos5x_disp_gate_clks,
1326 .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
1327 .suspend_regs = exynos5x_disp_suspend_regs,
1328 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1329 .pd_name = "DISP",
1330 };
1331
1332 static const struct exynos5_subcmu_info exynos5x_gsc_subcmu = {
1333 .div_clks = exynos5x_gsc_div_clks,
1334 .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
1335 .gate_clks = exynos5x_gsc_gate_clks,
1336 .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
1337 .suspend_regs = exynos5x_gsc_suspend_regs,
1338 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1339 .pd_name = "GSC",
1340 };
1341
1342 static const struct exynos5_subcmu_info exynos5x_g3d_subcmu = {
1343 .gate_clks = exynos5x_g3d_gate_clks,
1344 .nr_gate_clks = ARRAY_SIZE(exynos5x_g3d_gate_clks),
1345 .suspend_regs = exynos5x_g3d_suspend_regs,
1346 .nr_suspend_regs = ARRAY_SIZE(exynos5x_g3d_suspend_regs),
1347 .pd_name = "G3D",
1348 };
1349
1350 static const struct exynos5_subcmu_info exynos5x_mfc_subcmu = {
1351 .div_clks = exynos5x_mfc_div_clks,
1352 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
1353 .gate_clks = exynos5x_mfc_gate_clks,
1354 .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
1355 .suspend_regs = exynos5x_mfc_suspend_regs,
1356 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1357 .pd_name = "MFC",
1358 };
1359
1360 static const struct exynos5_subcmu_info exynos5x_mscl_subcmu = {
1361 .div_clks = exynos5x_mscl_div_clks,
1362 .nr_div_clks = ARRAY_SIZE(exynos5x_mscl_div_clks),
1363 .gate_clks = exynos5x_mscl_gate_clks,
1364 .nr_gate_clks = ARRAY_SIZE(exynos5x_mscl_gate_clks),
1365 .suspend_regs = exynos5x_mscl_suspend_regs,
1366 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mscl_suspend_regs),
1367 .pd_name = "MSC",
1368 };
1369
1370 static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
1371 .gate_clks = exynos5800_mau_gate_clks,
1372 .nr_gate_clks = ARRAY_SIZE(exynos5800_mau_gate_clks),
1373 .suspend_regs = exynos5800_mau_suspend_regs,
1374 .nr_suspend_regs = ARRAY_SIZE(exynos5800_mau_suspend_regs),
1375 .pd_name = "MAU",
1376 };
1377
1378 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
1379 &exynos5x_disp_subcmu,
1380 &exynos5x_gsc_subcmu,
1381 &exynos5x_g3d_subcmu,
1382 &exynos5x_mfc_subcmu,
1383 &exynos5x_mscl_subcmu,
1384 };
1385
1386 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
1387 &exynos5x_disp_subcmu,
1388 &exynos5x_gsc_subcmu,
1389 &exynos5x_g3d_subcmu,
1390 &exynos5x_mfc_subcmu,
1391 &exynos5x_mscl_subcmu,
1392 &exynos5800_mau_subcmu,
1393 };
1394
1395 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1396 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1397 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1398 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1399 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1400 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1401 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1402 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1403 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1404 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1405 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
1406 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
1407 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1),
1408 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
1409 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
1410 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2),
1411 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
1412 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
1413 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3),
1414 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
1415 };
1416
1417 static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
1418 PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
1419 PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
1420 PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
1421 PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
1422 PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
1423 PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
1424 PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
1425 PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
1426 };
1427
1428 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1429 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1430 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1431 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1432 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
1433 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1434 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1435 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
1436 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
1437 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1438 PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923),
1439 PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762),
1440 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719),
1441 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
1442 PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762),
1443 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
1444 };
1445
1446 static const struct samsung_pll_rate_table exynos5420_vpll_24mhz_tbl[] = {
1447 PLL_35XX_RATE(24 * MHZ, 600000000U, 200, 2, 2),
1448 PLL_35XX_RATE(24 * MHZ, 543000000U, 181, 2, 2),
1449 PLL_35XX_RATE(24 * MHZ, 480000000U, 160, 2, 2),
1450 PLL_35XX_RATE(24 * MHZ, 420000000U, 140, 2, 2),
1451 PLL_35XX_RATE(24 * MHZ, 350000000U, 175, 3, 2),
1452 PLL_35XX_RATE(24 * MHZ, 266000000U, 266, 3, 3),
1453 PLL_35XX_RATE(24 * MHZ, 177000000U, 118, 2, 3),
1454 PLL_35XX_RATE(24 * MHZ, 100000000U, 200, 3, 4),
1455 };
1456
1457 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1458 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1459 APLL_CON0, NULL),
1460 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1461 CPLL_CON0, NULL),
1462 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1463 DPLL_CON0, NULL),
1464 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1465 EPLL_CON0, NULL),
1466 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1467 RPLL_CON0, NULL),
1468 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1469 IPLL_CON0, NULL),
1470 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1471 SPLL_CON0, NULL),
1472 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1473 VPLL_CON0, NULL),
1474 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1475 MPLL_CON0, NULL),
1476 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1477 BPLL_CON0, NULL),
1478 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1479 KPLL_CON0, NULL),
1480 };
1481
1482 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
1483 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1484 ((cpud) << 4)))
1485
1486 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
1487 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1488 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1489 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1490 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1491 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1492 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1493 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1494 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1495 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1496 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1497 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1498 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1499 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1500 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1501 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1502 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1503 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1504 { 0 },
1505 };
1506
1507 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
1508 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1509 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1510 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1511 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1512 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1513 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1514 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1515 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1516 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1517 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1518 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1519 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1520 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1521 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1522 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1523 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1524 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1525 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1526 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
1527 { 0 },
1528 };
1529
1530 #define E5420_KFC_DIV(kpll, pclk, aclk) \
1531 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
1532
1533 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
1534 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
1535 { 1300000, E5420_KFC_DIV(3, 5, 2), },
1536 { 1200000, E5420_KFC_DIV(3, 5, 2), },
1537 { 1100000, E5420_KFC_DIV(3, 5, 2), },
1538 { 1000000, E5420_KFC_DIV(3, 5, 2), },
1539 { 900000, E5420_KFC_DIV(3, 5, 2), },
1540 { 800000, E5420_KFC_DIV(3, 5, 2), },
1541 { 700000, E5420_KFC_DIV(3, 4, 2), },
1542 { 600000, E5420_KFC_DIV(3, 4, 2), },
1543 { 500000, E5420_KFC_DIV(3, 4, 2), },
1544 { 400000, E5420_KFC_DIV(3, 3, 2), },
1545 { 300000, E5420_KFC_DIV(3, 3, 2), },
1546 { 200000, E5420_KFC_DIV(3, 3, 2), },
1547 { 0 },
1548 };
1549
1550 static const struct of_device_id ext_clk_match[] __initconst = {
1551 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1552 { },
1553 };
1554
1555 /* register exynos5420 clocks */
1556 static void __init exynos5x_clk_init(struct device_node *np,
1557 enum exynos5x_soc soc)
1558 {
1559 struct samsung_clk_provider *ctx;
1560
1561 if (np) {
1562 reg_base = of_iomap(np, 0);
1563 if (!reg_base)
1564 panic("%s: failed to map registers\n", __func__);
1565 } else {
1566 panic("%s: unable to determine soc\n", __func__);
1567 }
1568
1569 exynos5x_soc = soc;
1570
1571 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1572
1573 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1574 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1575 ext_clk_match);
1576
1577 if (_get_rate("fin_pll") == 24 * MHZ) {
1578 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1579 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
1580 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1581 exynos5x_plls[vpll].rate_table = exynos5420_vpll_24mhz_tbl;
1582 }
1583
1584 if (soc == EXYNOS5420)
1585 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1586 else
1587 exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
1588
1589 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1590 reg_base);
1591 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1592 ARRAY_SIZE(exynos5x_fixed_rate_clks));
1593 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1594 ARRAY_SIZE(exynos5x_fixed_factor_clks));
1595 samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1596 ARRAY_SIZE(exynos5x_mux_clks));
1597 samsung_clk_register_div(ctx, exynos5x_div_clks,
1598 ARRAY_SIZE(exynos5x_div_clks));
1599 samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1600 ARRAY_SIZE(exynos5x_gate_clks));
1601
1602 if (soc == EXYNOS5420) {
1603 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1604 ARRAY_SIZE(exynos5420_mux_clks));
1605 samsung_clk_register_div(ctx, exynos5420_div_clks,
1606 ARRAY_SIZE(exynos5420_div_clks));
1607 samsung_clk_register_gate(ctx, exynos5420_gate_clks,
1608 ARRAY_SIZE(exynos5420_gate_clks));
1609 } else {
1610 samsung_clk_register_fixed_factor(
1611 ctx, exynos5800_fixed_factor_clks,
1612 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1613 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1614 ARRAY_SIZE(exynos5800_mux_clks));
1615 samsung_clk_register_div(ctx, exynos5800_div_clks,
1616 ARRAY_SIZE(exynos5800_div_clks));
1617 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1618 ARRAY_SIZE(exynos5800_gate_clks));
1619 }
1620
1621 if (soc == EXYNOS5420) {
1622 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1623 mout_cpu_p[0], mout_cpu_p[1], 0x200,
1624 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1625 } else {
1626 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1627 mout_cpu_p[0], mout_cpu_p[1], 0x200,
1628 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1629 }
1630 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1631 mout_kfc_p[0], mout_kfc_p[1], 0x28200,
1632 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
1633
1634 samsung_clk_extended_sleep_init(reg_base,
1635 exynos5x_clk_regs, ARRAY_SIZE(exynos5x_clk_regs),
1636 exynos5420_set_clksrc, ARRAY_SIZE(exynos5420_set_clksrc));
1637
1638 if (soc == EXYNOS5800) {
1639 samsung_clk_sleep_init(reg_base, exynos5800_clk_regs,
1640 ARRAY_SIZE(exynos5800_clk_regs));
1641
1642 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5800_subcmus),
1643 exynos5800_subcmus);
1644 } else {
1645 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1646 exynos5x_subcmus);
1647 }
1648
1649 samsung_clk_of_add_provider(np, ctx);
1650 }
1651
1652 static void __init exynos5420_clk_init(struct device_node *np)
1653 {
1654 exynos5x_clk_init(np, EXYNOS5420);
1655 }
1656 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1657 exynos5420_clk_init);
1658
1659 static void __init exynos5800_clk_init(struct device_node *np)
1660 {
1661 exynos5x_clk_init(np, EXYNOS5800);
1662 }
1663 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
1664 exynos5800_clk_init);
Linux with added FPC-III support