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dm writecache: fix incorrect flush sequence when doing SSD mode commit
[linux/fpc-iii.git] / drivers / clk / tegra / clk-tegra20.c
blob4d8222f5c63893ea348ca0003a7ace0b5b487ab4
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/io.h>
7 #include <linux/clk-provider.h>
8 #include <linux/clkdev.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/clk/tegra.h>
12 #include <linux/delay.h>
13 #include <dt-bindings/clock/tegra20-car.h>
14
15 #include "clk.h"
16 #include "clk-id.h"
17
18 #define MISC_CLK_ENB 0x48
19
20 #define OSC_CTRL 0x50
21 #define OSC_CTRL_OSC_FREQ_MASK (3<<30)
22 #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
23 #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
24 #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
25 #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
26 #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
27
28 #define OSC_CTRL_PLL_REF_DIV_MASK (3<<28)
29 #define OSC_CTRL_PLL_REF_DIV_1 (0<<28)
30 #define OSC_CTRL_PLL_REF_DIV_2 (1<<28)
31 #define OSC_CTRL_PLL_REF_DIV_4 (2<<28)
32
33 #define OSC_FREQ_DET 0x58
34 #define OSC_FREQ_DET_TRIG (1<<31)
35
36 #define OSC_FREQ_DET_STATUS 0x5c
37 #define OSC_FREQ_DET_BUSY (1<<31)
38 #define OSC_FREQ_DET_CNT_MASK 0xFFFF
39
40 #define TEGRA20_CLK_PERIPH_BANKS 3
41
42 #define PLLS_BASE 0xf0
43 #define PLLS_MISC 0xf4
44 #define PLLC_BASE 0x80
45 #define PLLC_MISC 0x8c
46 #define PLLM_BASE 0x90
47 #define PLLM_MISC 0x9c
48 #define PLLP_BASE 0xa0
49 #define PLLP_MISC 0xac
50 #define PLLA_BASE 0xb0
51 #define PLLA_MISC 0xbc
52 #define PLLU_BASE 0xc0
53 #define PLLU_MISC 0xcc
54 #define PLLD_BASE 0xd0
55 #define PLLD_MISC 0xdc
56 #define PLLX_BASE 0xe0
57 #define PLLX_MISC 0xe4
58 #define PLLE_BASE 0xe8
59 #define PLLE_MISC 0xec
60
61 #define PLL_BASE_LOCK BIT(27)
62 #define PLLE_MISC_LOCK BIT(11)
63
64 #define PLL_MISC_LOCK_ENABLE 18
65 #define PLLDU_MISC_LOCK_ENABLE 22
66 #define PLLE_MISC_LOCK_ENABLE 9
67
68 #define PLLC_OUT 0x84
69 #define PLLM_OUT 0x94
70 #define PLLP_OUTA 0xa4
71 #define PLLP_OUTB 0xa8
72 #define PLLA_OUT 0xb4
73
74 #define CCLK_BURST_POLICY 0x20
75 #define SUPER_CCLK_DIVIDER 0x24
76 #define SCLK_BURST_POLICY 0x28
77 #define SUPER_SCLK_DIVIDER 0x2c
78 #define CLK_SYSTEM_RATE 0x30
79
80 #define CCLK_BURST_POLICY_SHIFT 28
81 #define CCLK_RUN_POLICY_SHIFT 4
82 #define CCLK_IDLE_POLICY_SHIFT 0
83 #define CCLK_IDLE_POLICY 1
84 #define CCLK_RUN_POLICY 2
85 #define CCLK_BURST_POLICY_PLLX 8
86
87 #define CLK_SOURCE_I2S1 0x100
88 #define CLK_SOURCE_I2S2 0x104
89 #define CLK_SOURCE_PWM 0x110
90 #define CLK_SOURCE_SPI 0x114
91 #define CLK_SOURCE_XIO 0x120
92 #define CLK_SOURCE_TWC 0x12c
93 #define CLK_SOURCE_IDE 0x144
94 #define CLK_SOURCE_HDMI 0x18c
95 #define CLK_SOURCE_DISP1 0x138
96 #define CLK_SOURCE_DISP2 0x13c
97 #define CLK_SOURCE_CSITE 0x1d4
98 #define CLK_SOURCE_I2C1 0x124
99 #define CLK_SOURCE_I2C2 0x198
100 #define CLK_SOURCE_I2C3 0x1b8
101 #define CLK_SOURCE_DVC 0x128
102 #define CLK_SOURCE_UARTA 0x178
103 #define CLK_SOURCE_UARTB 0x17c
104 #define CLK_SOURCE_UARTC 0x1a0
105 #define CLK_SOURCE_UARTD 0x1c0
106 #define CLK_SOURCE_UARTE 0x1c4
107 #define CLK_SOURCE_EMC 0x19c
108
109 #define AUDIO_SYNC_CLK 0x38
110
111 /* Tegra CPU clock and reset control regs */
112 #define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
113 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
114 #define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
115
116 #define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
117 #define CPU_RESET(cpu) (0x1111ul << (cpu))
118
119 #ifdef CONFIG_PM_SLEEP
120 static struct cpu_clk_suspend_context {
121 u32 pllx_misc;
122 u32 pllx_base;
123
124 u32 cpu_burst;
125 u32 clk_csite_src;
126 u32 cclk_divider;
127 } tegra20_cpu_clk_sctx;
128 #endif
129
130 static void __iomem *clk_base;
131 static void __iomem *pmc_base;
132
133 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
134 _clk_num, _gate_flags, _clk_id) \
135 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
136 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
137 _clk_num, \
138 _gate_flags, _clk_id)
139
140 #define TEGRA_INIT_DATA_DIV16(_name, _parents, _offset, \
141 _clk_num, _gate_flags, _clk_id) \
142 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
143 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, \
144 _clk_num, _gate_flags, \
145 _clk_id)
146
147 #define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
148 _mux_shift, _mux_width, _clk_num, \
149 _gate_flags, _clk_id) \
150 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
151 _mux_shift, _mux_width, 0, 0, 0, 0, 0, \
152 _clk_num, _gate_flags, \
153 _clk_id)
154
155 static struct clk **clks;
156
157 static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
158 { 12000000, 600000000, 600, 12, 1, 8 },
159 { 13000000, 600000000, 600, 13, 1, 8 },
160 { 19200000, 600000000, 500, 16, 1, 6 },
161 { 26000000, 600000000, 600, 26, 1, 8 },
162 { 0, 0, 0, 0, 0, 0 },
163 };
164
165 static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
166 { 12000000, 666000000, 666, 12, 1, 8 },
167 { 13000000, 666000000, 666, 13, 1, 8 },
168 { 19200000, 666000000, 555, 16, 1, 8 },
169 { 26000000, 666000000, 666, 26, 1, 8 },
170 { 12000000, 600000000, 600, 12, 1, 8 },
171 { 13000000, 600000000, 600, 13, 1, 8 },
172 { 19200000, 600000000, 375, 12, 1, 6 },
173 { 26000000, 600000000, 600, 26, 1, 8 },
174 { 0, 0, 0, 0, 0, 0 },
175 };
176
177 static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
178 { 12000000, 216000000, 432, 12, 2, 8 },
179 { 13000000, 216000000, 432, 13, 2, 8 },
180 { 19200000, 216000000, 90, 4, 2, 1 },
181 { 26000000, 216000000, 432, 26, 2, 8 },
182 { 12000000, 432000000, 432, 12, 1, 8 },
183 { 13000000, 432000000, 432, 13, 1, 8 },
184 { 19200000, 432000000, 90, 4, 1, 1 },
185 { 26000000, 432000000, 432, 26, 1, 8 },
186 { 0, 0, 0, 0, 0, 0 },
187 };
188
189 static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
190 { 28800000, 56448000, 49, 25, 1, 1 },
191 { 28800000, 73728000, 64, 25, 1, 1 },
192 { 28800000, 24000000, 5, 6, 1, 1 },
193 { 0, 0, 0, 0, 0, 0 },
194 };
195
196 static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
197 { 12000000, 216000000, 216, 12, 1, 4 },
198 { 13000000, 216000000, 216, 13, 1, 4 },
199 { 19200000, 216000000, 135, 12, 1, 3 },
200 { 26000000, 216000000, 216, 26, 1, 4 },
201 { 12000000, 594000000, 594, 12, 1, 8 },
202 { 13000000, 594000000, 594, 13, 1, 8 },
203 { 19200000, 594000000, 495, 16, 1, 8 },
204 { 26000000, 594000000, 594, 26, 1, 8 },
205 { 12000000, 1000000000, 1000, 12, 1, 12 },
206 { 13000000, 1000000000, 1000, 13, 1, 12 },
207 { 19200000, 1000000000, 625, 12, 1, 8 },
208 { 26000000, 1000000000, 1000, 26, 1, 12 },
209 { 0, 0, 0, 0, 0, 0 },
210 };
211
212 static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
213 { 12000000, 480000000, 960, 12, 1, 0 },
214 { 13000000, 480000000, 960, 13, 1, 0 },
215 { 19200000, 480000000, 200, 4, 1, 0 },
216 { 26000000, 480000000, 960, 26, 1, 0 },
217 { 0, 0, 0, 0, 0, 0 },
218 };
219
220 static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
221 /* 1 GHz */
222 { 12000000, 1000000000, 1000, 12, 1, 12 },
223 { 13000000, 1000000000, 1000, 13, 1, 12 },
224 { 19200000, 1000000000, 625, 12, 1, 8 },
225 { 26000000, 1000000000, 1000, 26, 1, 12 },
226 /* 912 MHz */
227 { 12000000, 912000000, 912, 12, 1, 12 },
228 { 13000000, 912000000, 912, 13, 1, 12 },
229 { 19200000, 912000000, 760, 16, 1, 8 },
230 { 26000000, 912000000, 912, 26, 1, 12 },
231 /* 816 MHz */
232 { 12000000, 816000000, 816, 12, 1, 12 },
233 { 13000000, 816000000, 816, 13, 1, 12 },
234 { 19200000, 816000000, 680, 16, 1, 8 },
235 { 26000000, 816000000, 816, 26, 1, 12 },
236 /* 760 MHz */
237 { 12000000, 760000000, 760, 12, 1, 12 },
238 { 13000000, 760000000, 760, 13, 1, 12 },
239 { 19200000, 760000000, 950, 24, 1, 8 },
240 { 26000000, 760000000, 760, 26, 1, 12 },
241 /* 750 MHz */
242 { 12000000, 750000000, 750, 12, 1, 12 },
243 { 13000000, 750000000, 750, 13, 1, 12 },
244 { 19200000, 750000000, 625, 16, 1, 8 },
245 { 26000000, 750000000, 750, 26, 1, 12 },
246 /* 608 MHz */
247 { 12000000, 608000000, 608, 12, 1, 12 },
248 { 13000000, 608000000, 608, 13, 1, 12 },
249 { 19200000, 608000000, 380, 12, 1, 8 },
250 { 26000000, 608000000, 608, 26, 1, 12 },
251 /* 456 MHz */
252 { 12000000, 456000000, 456, 12, 1, 12 },
253 { 13000000, 456000000, 456, 13, 1, 12 },
254 { 19200000, 456000000, 380, 16, 1, 8 },
255 { 26000000, 456000000, 456, 26, 1, 12 },
256 /* 312 MHz */
257 { 12000000, 312000000, 312, 12, 1, 12 },
258 { 13000000, 312000000, 312, 13, 1, 12 },
259 { 19200000, 312000000, 260, 16, 1, 8 },
260 { 26000000, 312000000, 312, 26, 1, 12 },
261 { 0, 0, 0, 0, 0, 0 },
262 };
263
264 static const struct pdiv_map plle_p[] = {
265 { .pdiv = 1, .hw_val = 1 },
266 { .pdiv = 0, .hw_val = 0 },
267 };
268
269 static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
270 { 12000000, 100000000, 200, 24, 1, 0 },
271 { 0, 0, 0, 0, 0, 0 },
272 };
273
274 /* PLL parameters */
275 static struct tegra_clk_pll_params pll_c_params = {
276 .input_min = 2000000,
277 .input_max = 31000000,
278 .cf_min = 1000000,
279 .cf_max = 6000000,
280 .vco_min = 20000000,
281 .vco_max = 1400000000,
282 .base_reg = PLLC_BASE,
283 .misc_reg = PLLC_MISC,
284 .lock_mask = PLL_BASE_LOCK,
285 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
286 .lock_delay = 300,
287 .freq_table = pll_c_freq_table,
288 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
289 };
290
291 static struct tegra_clk_pll_params pll_m_params = {
292 .input_min = 2000000,
293 .input_max = 31000000,
294 .cf_min = 1000000,
295 .cf_max = 6000000,
296 .vco_min = 20000000,
297 .vco_max = 1200000000,
298 .base_reg = PLLM_BASE,
299 .misc_reg = PLLM_MISC,
300 .lock_mask = PLL_BASE_LOCK,
301 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
302 .lock_delay = 300,
303 .freq_table = pll_m_freq_table,
304 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
305 };
306
307 static struct tegra_clk_pll_params pll_p_params = {
308 .input_min = 2000000,
309 .input_max = 31000000,
310 .cf_min = 1000000,
311 .cf_max = 6000000,
312 .vco_min = 20000000,
313 .vco_max = 1400000000,
314 .base_reg = PLLP_BASE,
315 .misc_reg = PLLP_MISC,
316 .lock_mask = PLL_BASE_LOCK,
317 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
318 .lock_delay = 300,
319 .freq_table = pll_p_freq_table,
320 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON |
321 TEGRA_PLL_HAS_LOCK_ENABLE,
322 .fixed_rate = 216000000,
323 };
324
325 static struct tegra_clk_pll_params pll_a_params = {
326 .input_min = 2000000,
327 .input_max = 31000000,
328 .cf_min = 1000000,
329 .cf_max = 6000000,
330 .vco_min = 20000000,
331 .vco_max = 1400000000,
332 .base_reg = PLLA_BASE,
333 .misc_reg = PLLA_MISC,
334 .lock_mask = PLL_BASE_LOCK,
335 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
336 .lock_delay = 300,
337 .freq_table = pll_a_freq_table,
338 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
339 };
340
341 static struct tegra_clk_pll_params pll_d_params = {
342 .input_min = 2000000,
343 .input_max = 40000000,
344 .cf_min = 1000000,
345 .cf_max = 6000000,
346 .vco_min = 40000000,
347 .vco_max = 1000000000,
348 .base_reg = PLLD_BASE,
349 .misc_reg = PLLD_MISC,
350 .lock_mask = PLL_BASE_LOCK,
351 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
352 .lock_delay = 1000,
353 .freq_table = pll_d_freq_table,
354 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
355 };
356
357 static const struct pdiv_map pllu_p[] = {
358 { .pdiv = 1, .hw_val = 1 },
359 { .pdiv = 2, .hw_val = 0 },
360 { .pdiv = 0, .hw_val = 0 },
361 };
362
363 static struct tegra_clk_pll_params pll_u_params = {
364 .input_min = 2000000,
365 .input_max = 40000000,
366 .cf_min = 1000000,
367 .cf_max = 6000000,
368 .vco_min = 48000000,
369 .vco_max = 960000000,
370 .base_reg = PLLU_BASE,
371 .misc_reg = PLLU_MISC,
372 .lock_mask = PLL_BASE_LOCK,
373 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
374 .lock_delay = 1000,
375 .pdiv_tohw = pllu_p,
376 .freq_table = pll_u_freq_table,
377 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
378 };
379
380 static struct tegra_clk_pll_params pll_x_params = {
381 .input_min = 2000000,
382 .input_max = 31000000,
383 .cf_min = 1000000,
384 .cf_max = 6000000,
385 .vco_min = 20000000,
386 .vco_max = 1200000000,
387 .base_reg = PLLX_BASE,
388 .misc_reg = PLLX_MISC,
389 .lock_mask = PLL_BASE_LOCK,
390 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
391 .lock_delay = 300,
392 .freq_table = pll_x_freq_table,
393 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE,
394 };
395
396 static struct tegra_clk_pll_params pll_e_params = {
397 .input_min = 12000000,
398 .input_max = 12000000,
399 .cf_min = 0,
400 .cf_max = 0,
401 .vco_min = 0,
402 .vco_max = 0,
403 .base_reg = PLLE_BASE,
404 .misc_reg = PLLE_MISC,
405 .lock_mask = PLLE_MISC_LOCK,
406 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
407 .lock_delay = 0,
408 .pdiv_tohw = plle_p,
409 .freq_table = pll_e_freq_table,
410 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC |
411 TEGRA_PLL_HAS_LOCK_ENABLE,
412 .fixed_rate = 100000000,
413 };
414
415 static struct tegra_devclk devclks[] __initdata = {
416 { .con_id = "pll_c", .dt_id = TEGRA20_CLK_PLL_C },
417 { .con_id = "pll_c_out1", .dt_id = TEGRA20_CLK_PLL_C_OUT1 },
418 { .con_id = "pll_p", .dt_id = TEGRA20_CLK_PLL_P },
419 { .con_id = "pll_p_out1", .dt_id = TEGRA20_CLK_PLL_P_OUT1 },
420 { .con_id = "pll_p_out2", .dt_id = TEGRA20_CLK_PLL_P_OUT2 },
421 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
422 { .con_id = "pll_p_out4", .dt_id = TEGRA20_CLK_PLL_P_OUT4 },
423 { .con_id = "pll_m", .dt_id = TEGRA20_CLK_PLL_M },
424 { .con_id = "pll_m_out1", .dt_id = TEGRA20_CLK_PLL_M_OUT1 },
425 { .con_id = "pll_x", .dt_id = TEGRA20_CLK_PLL_X },
426 { .con_id = "pll_u", .dt_id = TEGRA20_CLK_PLL_U },
427 { .con_id = "pll_d", .dt_id = TEGRA20_CLK_PLL_D },
428 { .con_id = "pll_d_out0", .dt_id = TEGRA20_CLK_PLL_D_OUT0 },
429 { .con_id = "pll_a", .dt_id = TEGRA20_CLK_PLL_A },
430 { .con_id = "pll_a_out0", .dt_id = TEGRA20_CLK_PLL_A_OUT0 },
431 { .con_id = "pll_e", .dt_id = TEGRA20_CLK_PLL_E },
432 { .con_id = "cclk", .dt_id = TEGRA20_CLK_CCLK },
433 { .con_id = "sclk", .dt_id = TEGRA20_CLK_SCLK },
434 { .con_id = "hclk", .dt_id = TEGRA20_CLK_HCLK },
435 { .con_id = "pclk", .dt_id = TEGRA20_CLK_PCLK },
436 { .con_id = "fuse", .dt_id = TEGRA20_CLK_FUSE },
437 { .con_id = "twd", .dt_id = TEGRA20_CLK_TWD },
438 { .con_id = "audio", .dt_id = TEGRA20_CLK_AUDIO },
439 { .con_id = "audio_2x", .dt_id = TEGRA20_CLK_AUDIO_2X },
440 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
441 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
442 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
443 { .dev_id = "timer", .dt_id = TEGRA20_CLK_TIMER },
444 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
445 { .con_id = "csus", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSUS },
446 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_VCP },
447 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA20_CLK_BSEA },
448 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA20_CLK_BSEV },
449 { .con_id = "emc", .dt_id = TEGRA20_CLK_EMC },
450 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA20_CLK_USBD },
451 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA20_CLK_USB2 },
452 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA20_CLK_USB3 },
453 { .dev_id = "dsi", .dt_id = TEGRA20_CLK_DSI },
454 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_CSI },
455 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_ISP },
456 { .con_id = "pex", .dt_id = TEGRA20_CLK_PEX },
457 { .con_id = "afi", .dt_id = TEGRA20_CLK_AFI },
458 { .con_id = "cdev1", .dt_id = TEGRA20_CLK_CDEV1 },
459 { .con_id = "cdev2", .dt_id = TEGRA20_CLK_CDEV2 },
460 { .con_id = "clk_32k", .dt_id = TEGRA20_CLK_CLK_32K },
461 { .con_id = "blink", .dt_id = TEGRA20_CLK_BLINK },
462 { .con_id = "clk_m", .dt_id = TEGRA20_CLK_CLK_M },
463 { .con_id = "pll_ref", .dt_id = TEGRA20_CLK_PLL_REF },
464 { .dev_id = "tegra20-i2s.0", .dt_id = TEGRA20_CLK_I2S1 },
465 { .dev_id = "tegra20-i2s.1", .dt_id = TEGRA20_CLK_I2S2 },
466 { .con_id = "spdif_out", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_OUT },
467 { .con_id = "spdif_in", .dev_id = "tegra20-spdif", .dt_id = TEGRA20_CLK_SPDIF_IN },
468 { .dev_id = "spi_tegra.0", .dt_id = TEGRA20_CLK_SBC1 },
469 { .dev_id = "spi_tegra.1", .dt_id = TEGRA20_CLK_SBC2 },
470 { .dev_id = "spi_tegra.2", .dt_id = TEGRA20_CLK_SBC3 },
471 { .dev_id = "spi_tegra.3", .dt_id = TEGRA20_CLK_SBC4 },
472 { .dev_id = "spi", .dt_id = TEGRA20_CLK_SPI },
473 { .dev_id = "xio", .dt_id = TEGRA20_CLK_XIO },
474 { .dev_id = "twc", .dt_id = TEGRA20_CLK_TWC },
475 { .dev_id = "ide", .dt_id = TEGRA20_CLK_IDE },
476 { .dev_id = "tegra_nand", .dt_id = TEGRA20_CLK_NDFLASH },
477 { .dev_id = "vfir", .dt_id = TEGRA20_CLK_VFIR },
478 { .dev_id = "csite", .dt_id = TEGRA20_CLK_CSITE },
479 { .dev_id = "la", .dt_id = TEGRA20_CLK_LA },
480 { .dev_id = "tegra_w1", .dt_id = TEGRA20_CLK_OWR },
481 { .dev_id = "mipi", .dt_id = TEGRA20_CLK_MIPI },
482 { .dev_id = "vde", .dt_id = TEGRA20_CLK_VDE },
483 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI },
484 { .dev_id = "epp", .dt_id = TEGRA20_CLK_EPP },
485 { .dev_id = "mpe", .dt_id = TEGRA20_CLK_MPE },
486 { .dev_id = "host1x", .dt_id = TEGRA20_CLK_HOST1X },
487 { .dev_id = "3d", .dt_id = TEGRA20_CLK_GR3D },
488 { .dev_id = "2d", .dt_id = TEGRA20_CLK_GR2D },
489 { .dev_id = "tegra-nor", .dt_id = TEGRA20_CLK_NOR },
490 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA20_CLK_SDMMC1 },
491 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA20_CLK_SDMMC2 },
492 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA20_CLK_SDMMC3 },
493 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA20_CLK_SDMMC4 },
494 { .dev_id = "cve", .dt_id = TEGRA20_CLK_CVE },
495 { .dev_id = "tvo", .dt_id = TEGRA20_CLK_TVO },
496 { .dev_id = "tvdac", .dt_id = TEGRA20_CLK_TVDAC },
497 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA20_CLK_VI_SENSOR },
498 { .dev_id = "hdmi", .dt_id = TEGRA20_CLK_HDMI },
499 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA20_CLK_I2C1 },
500 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA20_CLK_I2C2 },
501 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA20_CLK_I2C3 },
502 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA20_CLK_DVC },
503 { .dev_id = "tegra-pwm", .dt_id = TEGRA20_CLK_PWM },
504 { .dev_id = "tegra_uart.0", .dt_id = TEGRA20_CLK_UARTA },
505 { .dev_id = "tegra_uart.1", .dt_id = TEGRA20_CLK_UARTB },
506 { .dev_id = "tegra_uart.2", .dt_id = TEGRA20_CLK_UARTC },
507 { .dev_id = "tegra_uart.3", .dt_id = TEGRA20_CLK_UARTD },
508 { .dev_id = "tegra_uart.4", .dt_id = TEGRA20_CLK_UARTE },
509 { .dev_id = "tegradc.0", .dt_id = TEGRA20_CLK_DISP1 },
510 { .dev_id = "tegradc.1", .dt_id = TEGRA20_CLK_DISP2 },
511 };
512
513 static struct tegra_clk tegra20_clks[tegra_clk_max] __initdata = {
514 [tegra_clk_ahbdma] = { .dt_id = TEGRA20_CLK_AHBDMA, .present = true },
515 [tegra_clk_apbdma] = { .dt_id = TEGRA20_CLK_APBDMA, .present = true },
516 [tegra_clk_spdif_out] = { .dt_id = TEGRA20_CLK_SPDIF_OUT, .present = true },
517 [tegra_clk_spdif_in] = { .dt_id = TEGRA20_CLK_SPDIF_IN, .present = true },
518 [tegra_clk_sdmmc1] = { .dt_id = TEGRA20_CLK_SDMMC1, .present = true },
519 [tegra_clk_sdmmc2] = { .dt_id = TEGRA20_CLK_SDMMC2, .present = true },
520 [tegra_clk_sdmmc3] = { .dt_id = TEGRA20_CLK_SDMMC3, .present = true },
521 [tegra_clk_sdmmc4] = { .dt_id = TEGRA20_CLK_SDMMC4, .present = true },
522 [tegra_clk_la] = { .dt_id = TEGRA20_CLK_LA, .present = true },
523 [tegra_clk_csite] = { .dt_id = TEGRA20_CLK_CSITE, .present = true },
524 [tegra_clk_vfir] = { .dt_id = TEGRA20_CLK_VFIR, .present = true },
525 [tegra_clk_mipi] = { .dt_id = TEGRA20_CLK_MIPI, .present = true },
526 [tegra_clk_nor] = { .dt_id = TEGRA20_CLK_NOR, .present = true },
527 [tegra_clk_rtc] = { .dt_id = TEGRA20_CLK_RTC, .present = true },
528 [tegra_clk_timer] = { .dt_id = TEGRA20_CLK_TIMER, .present = true },
529 [tegra_clk_kbc] = { .dt_id = TEGRA20_CLK_KBC, .present = true },
530 [tegra_clk_csus] = { .dt_id = TEGRA20_CLK_CSUS, .present = true },
531 [tegra_clk_vcp] = { .dt_id = TEGRA20_CLK_VCP, .present = true },
532 [tegra_clk_bsea] = { .dt_id = TEGRA20_CLK_BSEA, .present = true },
533 [tegra_clk_bsev] = { .dt_id = TEGRA20_CLK_BSEV, .present = true },
534 [tegra_clk_usbd] = { .dt_id = TEGRA20_CLK_USBD, .present = true },
535 [tegra_clk_usb2] = { .dt_id = TEGRA20_CLK_USB2, .present = true },
536 [tegra_clk_usb3] = { .dt_id = TEGRA20_CLK_USB3, .present = true },
537 [tegra_clk_csi] = { .dt_id = TEGRA20_CLK_CSI, .present = true },
538 [tegra_clk_isp] = { .dt_id = TEGRA20_CLK_ISP, .present = true },
539 [tegra_clk_clk_32k] = { .dt_id = TEGRA20_CLK_CLK_32K, .present = true },
540 [tegra_clk_blink] = { .dt_id = TEGRA20_CLK_BLINK, .present = true },
541 [tegra_clk_hclk] = { .dt_id = TEGRA20_CLK_HCLK, .present = true },
542 [tegra_clk_pclk] = { .dt_id = TEGRA20_CLK_PCLK, .present = true },
543 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA20_CLK_PLL_P_OUT1, .present = true },
544 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA20_CLK_PLL_P_OUT2, .present = true },
545 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
546 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA20_CLK_PLL_P_OUT4, .present = true },
547 [tegra_clk_pll_p] = { .dt_id = TEGRA20_CLK_PLL_P, .present = true },
548 [tegra_clk_owr] = { .dt_id = TEGRA20_CLK_OWR, .present = true },
549 [tegra_clk_sbc1] = { .dt_id = TEGRA20_CLK_SBC1, .present = true },
550 [tegra_clk_sbc2] = { .dt_id = TEGRA20_CLK_SBC2, .present = true },
551 [tegra_clk_sbc3] = { .dt_id = TEGRA20_CLK_SBC3, .present = true },
552 [tegra_clk_sbc4] = { .dt_id = TEGRA20_CLK_SBC4, .present = true },
553 [tegra_clk_vde] = { .dt_id = TEGRA20_CLK_VDE, .present = true },
554 [tegra_clk_vi] = { .dt_id = TEGRA20_CLK_VI, .present = true },
555 [tegra_clk_epp] = { .dt_id = TEGRA20_CLK_EPP, .present = true },
556 [tegra_clk_mpe] = { .dt_id = TEGRA20_CLK_MPE, .present = true },
557 [tegra_clk_host1x] = { .dt_id = TEGRA20_CLK_HOST1X, .present = true },
558 [tegra_clk_gr2d] = { .dt_id = TEGRA20_CLK_GR2D, .present = true },
559 [tegra_clk_gr3d] = { .dt_id = TEGRA20_CLK_GR3D, .present = true },
560 [tegra_clk_ndflash] = { .dt_id = TEGRA20_CLK_NDFLASH, .present = true },
561 [tegra_clk_cve] = { .dt_id = TEGRA20_CLK_CVE, .present = true },
562 [tegra_clk_tvo] = { .dt_id = TEGRA20_CLK_TVO, .present = true },
563 [tegra_clk_tvdac] = { .dt_id = TEGRA20_CLK_TVDAC, .present = true },
564 [tegra_clk_vi_sensor] = { .dt_id = TEGRA20_CLK_VI_SENSOR, .present = true },
565 [tegra_clk_afi] = { .dt_id = TEGRA20_CLK_AFI, .present = true },
566 [tegra_clk_fuse] = { .dt_id = TEGRA20_CLK_FUSE, .present = true },
567 [tegra_clk_kfuse] = { .dt_id = TEGRA20_CLK_KFUSE, .present = true },
568 };
569
570 static unsigned long tegra20_clk_measure_input_freq(void)
571 {
572 u32 osc_ctrl = readl_relaxed(clk_base + OSC_CTRL);
573 u32 auto_clk_control = osc_ctrl & OSC_CTRL_OSC_FREQ_MASK;
574 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
575 unsigned long input_freq;
576
577 switch (auto_clk_control) {
578 case OSC_CTRL_OSC_FREQ_12MHZ:
579 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
580 input_freq = 12000000;
581 break;
582 case OSC_CTRL_OSC_FREQ_13MHZ:
583 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
584 input_freq = 13000000;
585 break;
586 case OSC_CTRL_OSC_FREQ_19_2MHZ:
587 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
588 input_freq = 19200000;
589 break;
590 case OSC_CTRL_OSC_FREQ_26MHZ:
591 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
592 input_freq = 26000000;
593 break;
594 default:
595 pr_err("Unexpected clock autodetect value %d",
596 auto_clk_control);
597 BUG();
598 return 0;
599 }
600
601 return input_freq;
602 }
603
604 static unsigned int tegra20_get_pll_ref_div(void)
605 {
606 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) &
607 OSC_CTRL_PLL_REF_DIV_MASK;
608
609 switch (pll_ref_div) {
610 case OSC_CTRL_PLL_REF_DIV_1:
611 return 1;
612 case OSC_CTRL_PLL_REF_DIV_2:
613 return 2;
614 case OSC_CTRL_PLL_REF_DIV_4:
615 return 4;
616 default:
617 pr_err("Invalid pll ref divider %d\n", pll_ref_div);
618 BUG();
619 }
620 return 0;
621 }
622
623 static void tegra20_pll_init(void)
624 {
625 struct clk *clk;
626
627 /* PLLC */
628 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, NULL, 0,
629 &pll_c_params, NULL);
630 clks[TEGRA20_CLK_PLL_C] = clk;
631
632 /* PLLC_OUT1 */
633 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
634 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
635 8, 8, 1, NULL);
636 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
637 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
638 0, NULL);
639 clks[TEGRA20_CLK_PLL_C_OUT1] = clk;
640
641 /* PLLM */
642 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, NULL,
643 CLK_SET_RATE_GATE, &pll_m_params, NULL);
644 clks[TEGRA20_CLK_PLL_M] = clk;
645
646 /* PLLM_OUT1 */
647 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
648 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
649 8, 8, 1, NULL);
650 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
651 clk_base + PLLM_OUT, 1, 0,
652 CLK_SET_RATE_PARENT, 0, NULL);
653 clks[TEGRA20_CLK_PLL_M_OUT1] = clk;
654
655 /* PLLX */
656 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, NULL, 0,
657 &pll_x_params, NULL);
658 clks[TEGRA20_CLK_PLL_X] = clk;
659
660 /* PLLU */
661 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, NULL, 0,
662 &pll_u_params, NULL);
663 clks[TEGRA20_CLK_PLL_U] = clk;
664
665 /* PLLD */
666 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, NULL, 0,
667 &pll_d_params, NULL);
668 clks[TEGRA20_CLK_PLL_D] = clk;
669
670 /* PLLD_OUT0 */
671 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
672 CLK_SET_RATE_PARENT, 1, 2);
673 clks[TEGRA20_CLK_PLL_D_OUT0] = clk;
674
675 /* PLLA */
676 clk = tegra_clk_register_pll("pll_a", "pll_p_out1", clk_base, NULL, 0,
677 &pll_a_params, NULL);
678 clks[TEGRA20_CLK_PLL_A] = clk;
679
680 /* PLLA_OUT0 */
681 clk = tegra_clk_register_divider("pll_a_out0_div", "pll_a",
682 clk_base + PLLA_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
683 8, 8, 1, NULL);
684 clk = tegra_clk_register_pll_out("pll_a_out0", "pll_a_out0_div",
685 clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |
686 CLK_SET_RATE_PARENT, 0, NULL);
687 clks[TEGRA20_CLK_PLL_A_OUT0] = clk;
688
689 /* PLLE */
690 clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base,
691 0, &pll_e_params, NULL);
692 clks[TEGRA20_CLK_PLL_E] = clk;
693 }
694
695 static const char *cclk_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
696 "pll_p", "pll_p_out4",
697 "pll_p_out3", "clk_d", "pll_x" };
698 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
699 "pll_p_out3", "pll_p_out2", "clk_d",
700 "clk_32k", "pll_m_out1" };
701
702 static void tegra20_super_clk_init(void)
703 {
704 struct clk *clk;
705
706 /* CCLK */
707 clk = tegra_clk_register_super_mux("cclk", cclk_parents,
708 ARRAY_SIZE(cclk_parents), CLK_SET_RATE_PARENT,
709 clk_base + CCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
710 clks[TEGRA20_CLK_CCLK] = clk;
711
712 /* SCLK */
713 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
714 ARRAY_SIZE(sclk_parents),
715 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
716 clk_base + SCLK_BURST_POLICY, 0, 4, 0, 0, NULL);
717 clks[TEGRA20_CLK_SCLK] = clk;
718
719 /* twd */
720 clk = clk_register_fixed_factor(NULL, "twd", "cclk", 0, 1, 4);
721 clks[TEGRA20_CLK_TWD] = clk;
722 }
723
724 static const char *audio_parents[] = { "spdif_in", "i2s1", "i2s2", "unused",
725 "pll_a_out0", "unused", "unused",
726 "unused" };
727
728 static void __init tegra20_audio_clk_init(void)
729 {
730 struct clk *clk;
731
732 /* audio */
733 clk = clk_register_mux(NULL, "audio_mux", audio_parents,
734 ARRAY_SIZE(audio_parents),
735 CLK_SET_RATE_NO_REPARENT,
736 clk_base + AUDIO_SYNC_CLK, 0, 3, 0, NULL);
737 clk = clk_register_gate(NULL, "audio", "audio_mux", 0,
738 clk_base + AUDIO_SYNC_CLK, 4,
739 CLK_GATE_SET_TO_DISABLE, NULL);
740 clks[TEGRA20_CLK_AUDIO] = clk;
741
742 /* audio_2x */
743 clk = clk_register_fixed_factor(NULL, "audio_doubler", "audio",
744 CLK_SET_RATE_PARENT, 2, 1);
745 clk = tegra_clk_register_periph_gate("audio_2x", "audio_doubler",
746 TEGRA_PERIPH_NO_RESET, clk_base,
747 CLK_SET_RATE_PARENT, 89,
748 periph_clk_enb_refcnt);
749 clks[TEGRA20_CLK_AUDIO_2X] = clk;
750 }
751
752 static const char *i2s1_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
753 "clk_m" };
754 static const char *i2s2_parents[] = { "pll_a_out0", "audio_2x", "pll_p",
755 "clk_m" };
756 static const char *pwm_parents[] = { "pll_p", "pll_c", "audio", "clk_m",
757 "clk_32k" };
758 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
759 static const char *mux_pllpdc_clkm[] = { "pll_p", "pll_d_out0", "pll_c",
760 "clk_m" };
761
762 static struct tegra_periph_init_data tegra_periph_clk_list[] = {
763 TEGRA_INIT_DATA_MUX("i2s1", i2s1_parents, CLK_SOURCE_I2S1, 11, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S1),
764 TEGRA_INIT_DATA_MUX("i2s2", i2s2_parents, CLK_SOURCE_I2S2, 18, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2S2),
765 TEGRA_INIT_DATA_MUX("spi", mux_pllpcm_clkm, CLK_SOURCE_SPI, 43, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_SPI),
766 TEGRA_INIT_DATA_MUX("xio", mux_pllpcm_clkm, CLK_SOURCE_XIO, 45, 0, TEGRA20_CLK_XIO),
767 TEGRA_INIT_DATA_MUX("twc", mux_pllpcm_clkm, CLK_SOURCE_TWC, 16, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_TWC),
768 TEGRA_INIT_DATA_MUX("ide", mux_pllpcm_clkm, CLK_SOURCE_XIO, 25, 0, TEGRA20_CLK_IDE),
769 TEGRA_INIT_DATA_DIV16("dvc", mux_pllpcm_clkm, CLK_SOURCE_DVC, 47, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_DVC),
770 TEGRA_INIT_DATA_DIV16("i2c1", mux_pllpcm_clkm, CLK_SOURCE_I2C1, 12, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C1),
771 TEGRA_INIT_DATA_DIV16("i2c2", mux_pllpcm_clkm, CLK_SOURCE_I2C2, 54, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C2),
772 TEGRA_INIT_DATA_DIV16("i2c3", mux_pllpcm_clkm, CLK_SOURCE_I2C3, 67, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_I2C3),
773 TEGRA_INIT_DATA_MUX("hdmi", mux_pllpdc_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA20_CLK_HDMI),
774 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 3, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_PWM),
775 };
776
777 static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
778 TEGRA_INIT_DATA_NODIV("uarta", mux_pllpcm_clkm, CLK_SOURCE_UARTA, 30, 2, 6, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTA),
779 TEGRA_INIT_DATA_NODIV("uartb", mux_pllpcm_clkm, CLK_SOURCE_UARTB, 30, 2, 7, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTB),
780 TEGRA_INIT_DATA_NODIV("uartc", mux_pllpcm_clkm, CLK_SOURCE_UARTC, 30, 2, 55, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTC),
781 TEGRA_INIT_DATA_NODIV("uartd", mux_pllpcm_clkm, CLK_SOURCE_UARTD, 30, 2, 65, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTD),
782 TEGRA_INIT_DATA_NODIV("uarte", mux_pllpcm_clkm, CLK_SOURCE_UARTE, 30, 2, 66, TEGRA_PERIPH_ON_APB, TEGRA20_CLK_UARTE),
783 TEGRA_INIT_DATA_NODIV("disp1", mux_pllpdc_clkm, CLK_SOURCE_DISP1, 30, 2, 27, 0, TEGRA20_CLK_DISP1),
784 TEGRA_INIT_DATA_NODIV("disp2", mux_pllpdc_clkm, CLK_SOURCE_DISP2, 30, 2, 26, 0, TEGRA20_CLK_DISP2),
785 };
786
787 static void __init tegra20_periph_clk_init(void)
788 {
789 struct tegra_periph_init_data *data;
790 struct clk *clk;
791 unsigned int i;
792
793 /* ac97 */
794 clk = tegra_clk_register_periph_gate("ac97", "pll_a_out0",
795 TEGRA_PERIPH_ON_APB,
796 clk_base, 0, 3, periph_clk_enb_refcnt);
797 clks[TEGRA20_CLK_AC97] = clk;
798
799 /* emc */
800 clk = tegra20_clk_register_emc(clk_base + CLK_SOURCE_EMC, false);
801
802 clks[TEGRA20_CLK_EMC] = clk;
803
804 clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,
805 NULL);
806 clks[TEGRA20_CLK_MC] = clk;
807
808 /* dsi */
809 clk = tegra_clk_register_periph_gate("dsi", "pll_d", 0, clk_base, 0,
810 48, periph_clk_enb_refcnt);
811 clk_register_clkdev(clk, NULL, "dsi");
812 clks[TEGRA20_CLK_DSI] = clk;
813
814 /* pex */
815 clk = tegra_clk_register_periph_gate("pex", "clk_m", 0, clk_base, 0, 70,
816 periph_clk_enb_refcnt);
817 clks[TEGRA20_CLK_PEX] = clk;
818
819 /* dev1 OSC divider */
820 clk_register_divider(NULL, "dev1_osc_div", "clk_m",
821 0, clk_base + MISC_CLK_ENB, 22, 2,
822 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
823 NULL);
824
825 /* dev2 OSC divider */
826 clk_register_divider(NULL, "dev2_osc_div", "clk_m",
827 0, clk_base + MISC_CLK_ENB, 20, 2,
828 CLK_DIVIDER_POWER_OF_TWO | CLK_DIVIDER_READ_ONLY,
829 NULL);
830
831 /* cdev1 */
832 clk = tegra_clk_register_periph_gate("cdev1", "cdev1_mux", 0,
833 clk_base, 0, 94, periph_clk_enb_refcnt);
834 clks[TEGRA20_CLK_CDEV1] = clk;
835
836 /* cdev2 */
837 clk = tegra_clk_register_periph_gate("cdev2", "cdev2_mux", 0,
838 clk_base, 0, 93, periph_clk_enb_refcnt);
839 clks[TEGRA20_CLK_CDEV2] = clk;
840
841 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
842 data = &tegra_periph_clk_list[i];
843 clk = tegra_clk_register_periph_data(clk_base, data);
844 clks[data->clk_id] = clk;
845 }
846
847 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
848 data = &tegra_periph_nodiv_clk_list[i];
849 clk = tegra_clk_register_periph_nodiv(data->name,
850 data->p.parent_names,
851 data->num_parents, &data->periph,
852 clk_base, data->offset);
853 clks[data->clk_id] = clk;
854 }
855
856 tegra_periph_clk_init(clk_base, pmc_base, tegra20_clks, &pll_p_params);
857 }
858
859 static void __init tegra20_osc_clk_init(void)
860 {
861 struct clk *clk;
862 unsigned long input_freq;
863 unsigned int pll_ref_div;
864
865 input_freq = tegra20_clk_measure_input_freq();
866
867 /* clk_m */
868 clk = clk_register_fixed_rate(NULL, "clk_m", NULL, CLK_IGNORE_UNUSED,
869 input_freq);
870 clks[TEGRA20_CLK_CLK_M] = clk;
871
872 /* pll_ref */
873 pll_ref_div = tegra20_get_pll_ref_div();
874 clk = clk_register_fixed_factor(NULL, "pll_ref", "clk_m",
875 CLK_SET_RATE_PARENT, 1, pll_ref_div);
876 clks[TEGRA20_CLK_PLL_REF] = clk;
877 }
878
879 /* Tegra20 CPU clock and reset control functions */
880 static void tegra20_wait_cpu_in_reset(u32 cpu)
881 {
882 unsigned int reg;
883
884 do {
885 reg = readl(clk_base +
886 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
887 cpu_relax();
888 } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
889
890 return;
891 }
892
893 static void tegra20_put_cpu_in_reset(u32 cpu)
894 {
895 writel(CPU_RESET(cpu),
896 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
897 dmb();
898 }
899
900 static void tegra20_cpu_out_of_reset(u32 cpu)
901 {
902 writel(CPU_RESET(cpu),
903 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
904 wmb();
905 }
906
907 static void tegra20_enable_cpu_clock(u32 cpu)
908 {
909 unsigned int reg;
910
911 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
912 writel(reg & ~CPU_CLOCK(cpu),
913 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
914 barrier();
915 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
916 }
917
918 static void tegra20_disable_cpu_clock(u32 cpu)
919 {
920 unsigned int reg;
921
922 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
923 writel(reg | CPU_CLOCK(cpu),
924 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
925 }
926
927 #ifdef CONFIG_PM_SLEEP
928 static bool tegra20_cpu_rail_off_ready(void)
929 {
930 unsigned int cpu_rst_status;
931
932 cpu_rst_status = readl(clk_base +
933 TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
934
935 return !!(cpu_rst_status & 0x2);
936 }
937
938 static void tegra20_cpu_clock_suspend(void)
939 {
940 /* switch coresite to clk_m, save off original source */
941 tegra20_cpu_clk_sctx.clk_csite_src =
942 readl(clk_base + CLK_SOURCE_CSITE);
943 writel(3<<30, clk_base + CLK_SOURCE_CSITE);
944
945 tegra20_cpu_clk_sctx.cpu_burst =
946 readl(clk_base + CCLK_BURST_POLICY);
947 tegra20_cpu_clk_sctx.pllx_base =
948 readl(clk_base + PLLX_BASE);
949 tegra20_cpu_clk_sctx.pllx_misc =
950 readl(clk_base + PLLX_MISC);
951 tegra20_cpu_clk_sctx.cclk_divider =
952 readl(clk_base + SUPER_CCLK_DIVIDER);
953 }
954
955 static void tegra20_cpu_clock_resume(void)
956 {
957 unsigned int reg, policy;
958 u32 misc, base;
959
960 /* Is CPU complex already running on PLLX? */
961 reg = readl(clk_base + CCLK_BURST_POLICY);
962 policy = (reg >> CCLK_BURST_POLICY_SHIFT) & 0xF;
963
964 if (policy == CCLK_IDLE_POLICY)
965 reg = (reg >> CCLK_IDLE_POLICY_SHIFT) & 0xF;
966 else if (policy == CCLK_RUN_POLICY)
967 reg = (reg >> CCLK_RUN_POLICY_SHIFT) & 0xF;
968 else
969 BUG();
970
971 if (reg != CCLK_BURST_POLICY_PLLX) {
972 misc = readl_relaxed(clk_base + PLLX_MISC);
973 base = readl_relaxed(clk_base + PLLX_BASE);
974
975 if (misc != tegra20_cpu_clk_sctx.pllx_misc ||
976 base != tegra20_cpu_clk_sctx.pllx_base) {
977 /* restore PLLX settings if CPU is on different PLL */
978 writel(tegra20_cpu_clk_sctx.pllx_misc,
979 clk_base + PLLX_MISC);
980 writel(tegra20_cpu_clk_sctx.pllx_base,
981 clk_base + PLLX_BASE);
982
983 /* wait for PLL stabilization if PLLX was enabled */
984 if (tegra20_cpu_clk_sctx.pllx_base & (1 << 30))
985 udelay(300);
986 }
987 }
988
989 /*
990 * Restore original burst policy setting for calls resulting from CPU
991 * LP2 in idle or system suspend.
992 */
993 writel(tegra20_cpu_clk_sctx.cclk_divider,
994 clk_base + SUPER_CCLK_DIVIDER);
995 writel(tegra20_cpu_clk_sctx.cpu_burst,
996 clk_base + CCLK_BURST_POLICY);
997
998 writel(tegra20_cpu_clk_sctx.clk_csite_src,
999 clk_base + CLK_SOURCE_CSITE);
1000 }
1001 #endif
1002
1003 static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
1004 .wait_for_reset = tegra20_wait_cpu_in_reset,
1005 .put_in_reset = tegra20_put_cpu_in_reset,
1006 .out_of_reset = tegra20_cpu_out_of_reset,
1007 .enable_clock = tegra20_enable_cpu_clock,
1008 .disable_clock = tegra20_disable_cpu_clock,
1009 #ifdef CONFIG_PM_SLEEP
1010 .rail_off_ready = tegra20_cpu_rail_off_ready,
1011 .suspend = tegra20_cpu_clock_suspend,
1012 .resume = tegra20_cpu_clock_resume,
1013 #endif
1014 };
1015
1016 static struct tegra_clk_init_table init_table[] __initdata = {
1017 { TEGRA20_CLK_PLL_P, TEGRA20_CLK_CLK_MAX, 216000000, 1 },
1018 { TEGRA20_CLK_PLL_P_OUT1, TEGRA20_CLK_CLK_MAX, 28800000, 1 },
1019 { TEGRA20_CLK_PLL_P_OUT2, TEGRA20_CLK_CLK_MAX, 48000000, 1 },
1020 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },
1021 { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 },
1022 { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 },
1023 { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
1024 { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 },
1025 { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 },
1026 { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 },
1027 { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 },
1028 { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
1029 { TEGRA20_CLK_UARTA, TEGRA20_CLK_PLL_P, 0, 0 },
1030 { TEGRA20_CLK_UARTB, TEGRA20_CLK_PLL_P, 0, 0 },
1031 { TEGRA20_CLK_UARTC, TEGRA20_CLK_PLL_P, 0, 0 },
1032 { TEGRA20_CLK_UARTD, TEGRA20_CLK_PLL_P, 0, 0 },
1033 { TEGRA20_CLK_UARTE, TEGRA20_CLK_PLL_P, 0, 0 },
1034 { TEGRA20_CLK_PLL_A, TEGRA20_CLK_CLK_MAX, 56448000, 1 },
1035 { TEGRA20_CLK_PLL_A_OUT0, TEGRA20_CLK_CLK_MAX, 11289600, 1 },
1036 { TEGRA20_CLK_CDEV1, TEGRA20_CLK_CLK_MAX, 0, 1 },
1037 { TEGRA20_CLK_BLINK, TEGRA20_CLK_CLK_MAX, 32768, 1 },
1038 { TEGRA20_CLK_I2S1, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1039 { TEGRA20_CLK_I2S2, TEGRA20_CLK_PLL_A_OUT0, 11289600, 0 },
1040 { TEGRA20_CLK_SDMMC1, TEGRA20_CLK_PLL_P, 48000000, 0 },
1041 { TEGRA20_CLK_SDMMC3, TEGRA20_CLK_PLL_P, 48000000, 0 },
1042 { TEGRA20_CLK_SDMMC4, TEGRA20_CLK_PLL_P, 48000000, 0 },
1043 { TEGRA20_CLK_SPI, TEGRA20_CLK_PLL_P, 20000000, 0 },
1044 { TEGRA20_CLK_SBC1, TEGRA20_CLK_PLL_P, 100000000, 0 },
1045 { TEGRA20_CLK_SBC2, TEGRA20_CLK_PLL_P, 100000000, 0 },
1046 { TEGRA20_CLK_SBC3, TEGRA20_CLK_PLL_P, 100000000, 0 },
1047 { TEGRA20_CLK_SBC4, TEGRA20_CLK_PLL_P, 100000000, 0 },
1048 { TEGRA20_CLK_HOST1X, TEGRA20_CLK_PLL_C, 150000000, 0 },
1049 { TEGRA20_CLK_DISP1, TEGRA20_CLK_PLL_P, 600000000, 0 },
1050 { TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0 },
1051 { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1052 { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
1053 { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
1054 /* must be the last entry */
1055 { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
1056 };
1057
1058 static void __init tegra20_clock_apply_init_table(void)
1059 {
1060 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX);
1061 }
1062
1063 /*
1064 * Some clocks may be used by different drivers depending on the board
1065 * configuration. List those here to register them twice in the clock lookup
1066 * table under two names.
1067 */
1068 static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1069 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "utmip-pad", NULL),
1070 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-ehci.0", NULL),
1071 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_USBD, "tegra-otg", NULL),
1072 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CCLK, NULL, "cpu"),
1073 /* must be the last entry */
1074 TEGRA_CLK_DUPLICATE(TEGRA20_CLK_CLK_MAX, NULL, NULL),
1075 };
1076
1077 static const struct of_device_id pmc_match[] __initconst = {
1078 { .compatible = "nvidia,tegra20-pmc" },
1079 { },
1080 };
1081
1082 static struct clk *tegra20_clk_src_onecell_get(struct of_phandle_args *clkspec,
1083 void *data)
1084 {
1085 struct clk_hw *parent_hw;
1086 struct clk_hw *hw;
1087 struct clk *clk;
1088
1089 clk = of_clk_src_onecell_get(clkspec, data);
1090 if (IS_ERR(clk))
1091 return clk;
1092
1093 hw = __clk_get_hw(clk);
1094
1095 /*
1096 * Tegra20 CDEV1 and CDEV2 clocks are a bit special case, their parent
1097 * clock is created by the pinctrl driver. It is possible for clk user
1098 * to request these clocks before pinctrl driver got probed and hence
1099 * user will get an orphaned clock. That might be undesirable because
1100 * user may expect parent clock to be enabled by the child.
1101 */
1102 if (clkspec->args[0] == TEGRA20_CLK_CDEV1 ||
1103 clkspec->args[0] == TEGRA20_CLK_CDEV2) {
1104 parent_hw = clk_hw_get_parent(hw);
1105 if (!parent_hw)
1106 return ERR_PTR(-EPROBE_DEFER);
1107 }
1108
1109 if (clkspec->args[0] == TEGRA20_CLK_EMC) {
1110 if (!tegra20_clk_emc_driver_available(hw))
1111 return ERR_PTR(-EPROBE_DEFER);
1112 }
1113
1114 return clk;
1115 }
1116
1117 static void __init tegra20_clock_init(struct device_node *np)
1118 {
1119 struct device_node *node;
1120
1121 clk_base = of_iomap(np, 0);
1122 if (!clk_base) {
1123 pr_err("Can't map CAR registers\n");
1124 BUG();
1125 }
1126
1127 node = of_find_matching_node(NULL, pmc_match);
1128 if (!node) {
1129 pr_err("Failed to find pmc node\n");
1130 BUG();
1131 }
1132
1133 pmc_base = of_iomap(node, 0);
1134 if (!pmc_base) {
1135 pr_err("Can't map pmc registers\n");
1136 BUG();
1137 }
1138
1139 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX,
1140 TEGRA20_CLK_PERIPH_BANKS);
1141 if (!clks)
1142 return;
1143
1144 tegra20_osc_clk_init();
1145 tegra_fixed_clk_init(tegra20_clks);
1146 tegra20_pll_init();
1147 tegra20_super_clk_init();
1148 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra20_clks, NULL);
1149 tegra20_periph_clk_init();
1150 tegra20_audio_clk_init();
1151 tegra_pmc_clk_init(pmc_base, tegra20_clks);
1152
1153 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX);
1154
1155 tegra_add_of_provider(np, tegra20_clk_src_onecell_get);
1156 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1157
1158 tegra_clk_apply_init_table = tegra20_clock_apply_init_table;
1159
1160 tegra_cpu_car_ops = &tegra20_cpu_car_ops;
1161 }
1162 CLK_OF_DECLARE(tegra20, "nvidia,tegra20-car", tegra20_clock_init);
Linux with added FPC-III support