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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / arch / arm / mach-imx / mach-pcm037.c
blob89c213b81295cc7dc999c112916c2fbfcef17cff
1 /*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/types.h>
16 #include <linux/init.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20 #include <linux/mtd/plat-ram.h>
21 #include <linux/memory.h>
22 #include <linux/gpio.h>
23 #include <linux/smsc911x.h>
24 #include <linux/interrupt.h>
25 #include <linux/i2c.h>
26 #include <linux/i2c/at24.h>
27 #include <linux/delay.h>
28 #include <linux/spi/spi.h>
29 #include <linux/irq.h>
30 #include <linux/can/platform/sja1000.h>
31 #include <linux/usb/otg.h>
32 #include <linux/usb/ulpi.h>
33 #include <linux/gfp.h>
34 #include <linux/memblock.h>
35
36 #include <media/soc_camera.h>
37
38 #include <asm/mach-types.h>
39 #include <asm/mach/arch.h>
40 #include <asm/mach/time.h>
41 #include <asm/mach/map.h>
42 #include <mach/common.h>
43 #include <mach/hardware.h>
44 #include <mach/iomux-mx3.h>
45 #include <mach/ulpi.h>
46
47 #include "devices-imx31.h"
48 #include "pcm037.h"
49
50 static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
51
52 static int __init pcm037_variant_setup(char *str)
53 {
54 if (!strcmp("eet", str))
55 pcm037_instance = PCM037_EET;
56 else if (strcmp("pcm970", str))
57 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
58
59 return 1;
60 }
61
62 /* Supported values: "pcm970" (default) and "eet" */
63 __setup("pcm037_variant=", pcm037_variant_setup);
64
65 enum pcm037_board_variant pcm037_variant(void)
66 {
67 return pcm037_instance;
68 }
69
70 /* UART1 with RTS/CTS handshake signals */
71 static unsigned int pcm037_uart1_handshake_pins[] = {
72 MX31_PIN_CTS1__CTS1,
73 MX31_PIN_RTS1__RTS1,
74 MX31_PIN_TXD1__TXD1,
75 MX31_PIN_RXD1__RXD1,
76 };
77
78 /* UART1 without RTS/CTS handshake signals */
79 static unsigned int pcm037_uart1_pins[] = {
80 MX31_PIN_TXD1__TXD1,
81 MX31_PIN_RXD1__RXD1,
82 };
83
84 static unsigned int pcm037_pins[] = {
85 /* I2C */
86 MX31_PIN_CSPI2_MOSI__SCL,
87 MX31_PIN_CSPI2_MISO__SDA,
88 MX31_PIN_CSPI2_SS2__I2C3_SDA,
89 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
90 /* SDHC1 */
91 MX31_PIN_SD1_DATA3__SD1_DATA3,
92 MX31_PIN_SD1_DATA2__SD1_DATA2,
93 MX31_PIN_SD1_DATA1__SD1_DATA1,
94 MX31_PIN_SD1_DATA0__SD1_DATA0,
95 MX31_PIN_SD1_CLK__SD1_CLK,
96 MX31_PIN_SD1_CMD__SD1_CMD,
97 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
98 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
99 /* SPI1 */
100 MX31_PIN_CSPI1_MOSI__MOSI,
101 MX31_PIN_CSPI1_MISO__MISO,
102 MX31_PIN_CSPI1_SCLK__SCLK,
103 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
104 MX31_PIN_CSPI1_SS0__SS0,
105 MX31_PIN_CSPI1_SS1__SS1,
106 MX31_PIN_CSPI1_SS2__SS2,
107 /* UART2 */
108 MX31_PIN_TXD2__TXD2,
109 MX31_PIN_RXD2__RXD2,
110 MX31_PIN_CTS2__CTS2,
111 MX31_PIN_RTS2__RTS2,
112 /* UART3 */
113 MX31_PIN_CSPI3_MOSI__RXD3,
114 MX31_PIN_CSPI3_MISO__TXD3,
115 MX31_PIN_CSPI3_SCLK__RTS3,
116 MX31_PIN_CSPI3_SPI_RDY__CTS3,
117 /* LAN9217 irq pin */
118 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
119 /* Onewire */
120 MX31_PIN_BATT_LINE__OWIRE,
121 /* Framebuffer */
122 MX31_PIN_LD0__LD0,
123 MX31_PIN_LD1__LD1,
124 MX31_PIN_LD2__LD2,
125 MX31_PIN_LD3__LD3,
126 MX31_PIN_LD4__LD4,
127 MX31_PIN_LD5__LD5,
128 MX31_PIN_LD6__LD6,
129 MX31_PIN_LD7__LD7,
130 MX31_PIN_LD8__LD8,
131 MX31_PIN_LD9__LD9,
132 MX31_PIN_LD10__LD10,
133 MX31_PIN_LD11__LD11,
134 MX31_PIN_LD12__LD12,
135 MX31_PIN_LD13__LD13,
136 MX31_PIN_LD14__LD14,
137 MX31_PIN_LD15__LD15,
138 MX31_PIN_LD16__LD16,
139 MX31_PIN_LD17__LD17,
140 MX31_PIN_VSYNC3__VSYNC3,
141 MX31_PIN_HSYNC__HSYNC,
142 MX31_PIN_FPSHIFT__FPSHIFT,
143 MX31_PIN_DRDY0__DRDY0,
144 MX31_PIN_D3_REV__D3_REV,
145 MX31_PIN_CONTRAST__CONTRAST,
146 MX31_PIN_D3_SPL__D3_SPL,
147 MX31_PIN_D3_CLS__D3_CLS,
148 MX31_PIN_LCS0__GPI03_23,
149 /* CSI */
150 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
151 MX31_PIN_CSI_D6__CSI_D6,
152 MX31_PIN_CSI_D7__CSI_D7,
153 MX31_PIN_CSI_D8__CSI_D8,
154 MX31_PIN_CSI_D9__CSI_D9,
155 MX31_PIN_CSI_D10__CSI_D10,
156 MX31_PIN_CSI_D11__CSI_D11,
157 MX31_PIN_CSI_D12__CSI_D12,
158 MX31_PIN_CSI_D13__CSI_D13,
159 MX31_PIN_CSI_D14__CSI_D14,
160 MX31_PIN_CSI_D15__CSI_D15,
161 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
162 MX31_PIN_CSI_MCLK__CSI_MCLK,
163 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
164 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
165 /* GPIO */
166 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
167 /* OTG */
168 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
169 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
170 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
171 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
172 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
173 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
174 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
175 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
176 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
177 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
178 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
179 MX31_PIN_USBOTG_STP__USBOTG_STP,
180 /* USB host 2 */
181 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
182 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
183 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
184 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
185 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
186 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
187 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
193 };
194
195 static struct physmap_flash_data pcm037_flash_data = {
196 .width = 2,
197 };
198
199 static struct resource pcm037_flash_resource = {
200 .start = 0xa0000000,
201 .end = 0xa1ffffff,
202 .flags = IORESOURCE_MEM,
203 };
204
205 static struct platform_device pcm037_flash = {
206 .name = "physmap-flash",
207 .id = 0,
208 .dev = {
209 .platform_data = &pcm037_flash_data,
210 },
211 .resource = &pcm037_flash_resource,
212 .num_resources = 1,
213 };
214
215 static const struct imxuart_platform_data uart_pdata __initconst = {
216 .flags = IMXUART_HAVE_RTSCTS,
217 };
218
219 static struct resource smsc911x_resources[] = {
220 {
221 .start = MX31_CS1_BASE_ADDR + 0x300,
222 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
223 .flags = IORESOURCE_MEM,
224 }, {
225 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
226 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
227 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
228 },
229 };
230
231 static struct smsc911x_platform_config smsc911x_info = {
232 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
233 SMSC911X_SAVE_MAC_ADDRESS,
234 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
235 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
236 .phy_interface = PHY_INTERFACE_MODE_MII,
237 };
238
239 static struct platform_device pcm037_eth = {
240 .name = "smsc911x",
241 .id = -1,
242 .num_resources = ARRAY_SIZE(smsc911x_resources),
243 .resource = smsc911x_resources,
244 .dev = {
245 .platform_data = &smsc911x_info,
246 },
247 };
248
249 static struct platdata_mtd_ram pcm038_sram_data = {
250 .bankwidth = 2,
251 };
252
253 static struct resource pcm038_sram_resource = {
254 .start = MX31_CS4_BASE_ADDR,
255 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
256 .flags = IORESOURCE_MEM,
257 };
258
259 static struct platform_device pcm037_sram_device = {
260 .name = "mtd-ram",
261 .id = 0,
262 .dev = {
263 .platform_data = &pcm038_sram_data,
264 },
265 .num_resources = 1,
266 .resource = &pcm038_sram_resource,
267 };
268
269 static const struct mxc_nand_platform_data
270 pcm037_nand_board_info __initconst = {
271 .width = 1,
272 .hw_ecc = 1,
273 };
274
275 static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
276 .bitrate = 100000,
277 };
278
279 static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
280 .bitrate = 20000,
281 };
282
283 static struct at24_platform_data board_eeprom = {
284 .byte_len = 4096,
285 .page_size = 32,
286 .flags = AT24_FLAG_ADDR16,
287 };
288
289 static int pcm037_camera_power(struct device *dev, int on)
290 {
291 /* disable or enable the camera in X7 or X8 PCM970 connector */
292 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
293 return 0;
294 }
295
296 static struct i2c_board_info pcm037_i2c_camera[] = {
297 {
298 I2C_BOARD_INFO("mt9t031", 0x5d),
299 }, {
300 I2C_BOARD_INFO("mt9v022", 0x48),
301 },
302 };
303
304 static struct soc_camera_link iclink_mt9v022 = {
305 .bus_id = 0, /* Must match with the camera ID */
306 .board_info = &pcm037_i2c_camera[1],
307 .i2c_adapter_id = 2,
308 };
309
310 static struct soc_camera_link iclink_mt9t031 = {
311 .bus_id = 0, /* Must match with the camera ID */
312 .power = pcm037_camera_power,
313 .board_info = &pcm037_i2c_camera[0],
314 .i2c_adapter_id = 2,
315 };
316
317 static struct i2c_board_info pcm037_i2c_devices[] = {
318 {
319 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
320 .platform_data = &board_eeprom,
321 }, {
322 I2C_BOARD_INFO("pcf8563", 0x51),
323 }
324 };
325
326 static struct platform_device pcm037_mt9t031 = {
327 .name = "soc-camera-pdrv",
328 .id = 0,
329 .dev = {
330 .platform_data = &iclink_mt9t031,
331 },
332 };
333
334 static struct platform_device pcm037_mt9v022 = {
335 .name = "soc-camera-pdrv",
336 .id = 1,
337 .dev = {
338 .platform_data = &iclink_mt9v022,
339 },
340 };
341
342 /* Not connected by default */
343 #ifdef PCM970_SDHC_RW_SWITCH
344 static int pcm970_sdhc1_get_ro(struct device *dev)
345 {
346 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
347 }
348 #endif
349
350 #define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
351 #define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
352
353 static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
354 void *data)
355 {
356 int ret;
357
358 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
359 if (ret)
360 return ret;
361
362 gpio_direction_input(SDHC1_GPIO_DET);
363
364 #ifdef PCM970_SDHC_RW_SWITCH
365 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
366 if (ret)
367 goto err_gpio_free;
368 gpio_direction_input(SDHC1_GPIO_WP);
369 #endif
370
371 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
372 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
373 "sdhc-detect", data);
374 if (ret)
375 goto err_gpio_free_2;
376
377 return 0;
378
379 err_gpio_free_2:
380 #ifdef PCM970_SDHC_RW_SWITCH
381 gpio_free(SDHC1_GPIO_WP);
382 err_gpio_free:
383 #endif
384 gpio_free(SDHC1_GPIO_DET);
385
386 return ret;
387 }
388
389 static void pcm970_sdhc1_exit(struct device *dev, void *data)
390 {
391 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
392 gpio_free(SDHC1_GPIO_DET);
393 gpio_free(SDHC1_GPIO_WP);
394 }
395
396 static const struct imxmmc_platform_data sdhc_pdata __initconst = {
397 #ifdef PCM970_SDHC_RW_SWITCH
398 .get_ro = pcm970_sdhc1_get_ro,
399 #endif
400 .init = pcm970_sdhc1_init,
401 .exit = pcm970_sdhc1_exit,
402 };
403
404 struct mx3_camera_pdata camera_pdata __initdata = {
405 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
406 .mclk_10khz = 2000,
407 };
408
409 static phys_addr_t mx3_camera_base __initdata;
410 #define MX3_CAMERA_BUF_SIZE SZ_4M
411
412 static int __init pcm037_init_camera(void)
413 {
414 int dma, ret = -ENOMEM;
415 struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
416
417 if (IS_ERR(pdev))
418 return PTR_ERR(pdev);
419
420 dma = dma_declare_coherent_memory(&pdev->dev,
421 mx3_camera_base, mx3_camera_base,
422 MX3_CAMERA_BUF_SIZE,
423 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
424 if (!(dma & DMA_MEMORY_MAP))
425 goto err;
426
427 ret = platform_device_add(pdev);
428 if (ret)
429 err:
430 platform_device_put(pdev);
431
432 return ret;
433 }
434
435 static struct platform_device *devices[] __initdata = {
436 &pcm037_flash,
437 &pcm037_sram_device,
438 &pcm037_mt9t031,
439 &pcm037_mt9v022,
440 };
441
442 static const struct ipu_platform_data mx3_ipu_data __initconst = {
443 .irq_base = MXC_IPU_IRQ_START,
444 };
445
446 static const struct fb_videomode fb_modedb[] = {
447 {
448 /* 240x320 @ 60 Hz Sharp */
449 .name = "Sharp-LQ035Q7DH06-QVGA",
450 .refresh = 60,
451 .xres = 240,
452 .yres = 320,
453 .pixclock = 185925,
454 .left_margin = 9,
455 .right_margin = 16,
456 .upper_margin = 7,
457 .lower_margin = 9,
458 .hsync_len = 1,
459 .vsync_len = 1,
460 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
461 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
462 .vmode = FB_VMODE_NONINTERLACED,
463 .flag = 0,
464 }, {
465 /* 240x320 @ 60 Hz */
466 .name = "TX090",
467 .refresh = 60,
468 .xres = 240,
469 .yres = 320,
470 .pixclock = 38255,
471 .left_margin = 144,
472 .right_margin = 0,
473 .upper_margin = 7,
474 .lower_margin = 40,
475 .hsync_len = 96,
476 .vsync_len = 1,
477 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
478 .vmode = FB_VMODE_NONINTERLACED,
479 .flag = 0,
480 }, {
481 /* 240x320 @ 60 Hz */
482 .name = "CMEL-OLED",
483 .refresh = 60,
484 .xres = 240,
485 .yres = 320,
486 .pixclock = 185925,
487 .left_margin = 9,
488 .right_margin = 16,
489 .upper_margin = 7,
490 .lower_margin = 9,
491 .hsync_len = 1,
492 .vsync_len = 1,
493 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
494 .vmode = FB_VMODE_NONINTERLACED,
495 .flag = 0,
496 },
497 };
498
499 static struct mx3fb_platform_data mx3fb_pdata = {
500 .name = "Sharp-LQ035Q7DH06-QVGA",
501 .mode = fb_modedb,
502 .num_modes = ARRAY_SIZE(fb_modedb),
503 };
504
505 static struct resource pcm970_sja1000_resources[] = {
506 {
507 .start = MX31_CS5_BASE_ADDR,
508 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
509 .flags = IORESOURCE_MEM,
510 }, {
511 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
512 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
513 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
514 },
515 };
516
517 struct sja1000_platform_data pcm970_sja1000_platform_data = {
518 .osc_freq = 16000000,
519 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
520 .cdr = CDR_CBP,
521 };
522
523 static struct platform_device pcm970_sja1000 = {
524 .name = "sja1000_platform",
525 .dev = {
526 .platform_data = &pcm970_sja1000_platform_data,
527 },
528 .resource = pcm970_sja1000_resources,
529 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
530 };
531
532 static int pcm037_otg_init(struct platform_device *pdev)
533 {
534 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
535 }
536
537 static struct mxc_usbh_platform_data otg_pdata __initdata = {
538 .init = pcm037_otg_init,
539 .portsc = MXC_EHCI_MODE_ULPI,
540 };
541
542 static int pcm037_usbh2_init(struct platform_device *pdev)
543 {
544 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
545 }
546
547 static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
548 .init = pcm037_usbh2_init,
549 .portsc = MXC_EHCI_MODE_ULPI,
550 };
551
552 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
553 .operating_mode = FSL_USB2_DR_DEVICE,
554 .phy_mode = FSL_USB2_PHY_ULPI,
555 };
556
557 static int otg_mode_host;
558
559 static int __init pcm037_otg_mode(char *options)
560 {
561 if (!strcmp(options, "host"))
562 otg_mode_host = 1;
563 else if (!strcmp(options, "device"))
564 otg_mode_host = 0;
565 else
566 pr_info("otg_mode neither \"host\" nor \"device\". "
567 "Defaulting to device\n");
568 return 0;
569 }
570 __setup("otg_mode=", pcm037_otg_mode);
571
572 /*
573 * Board specific initialization.
574 */
575 static void __init pcm037_init(void)
576 {
577 int ret;
578
579 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
580
581 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
582 "pcm037");
583
584 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
585 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
586
587 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
588 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
589 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
590 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
591 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
592 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
593 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
594 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
595 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
596 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
597 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
598 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
599
600 if (pcm037_variant() == PCM037_EET)
601 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
602 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
603 else
604 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
605 ARRAY_SIZE(pcm037_uart1_handshake_pins),
606 "pcm037_uart1");
607
608 platform_add_devices(devices, ARRAY_SIZE(devices));
609
610 imx31_add_imx2_wdt(NULL);
611 imx31_add_imx_uart0(&uart_pdata);
612 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
613 imx31_add_imx_uart1(&uart_pdata);
614 imx31_add_imx_uart2(&uart_pdata);
615
616 imx31_add_mxc_w1(NULL);
617
618 /* LAN9217 IRQ pin */
619 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
620 if (ret)
621 pr_warning("could not get LAN irq gpio\n");
622 else {
623 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
624 platform_device_register(&pcm037_eth);
625 }
626
627
628 /* I2C adapters and devices */
629 i2c_register_board_info(1, pcm037_i2c_devices,
630 ARRAY_SIZE(pcm037_i2c_devices));
631
632 imx31_add_imx_i2c1(&pcm037_i2c1_data);
633 imx31_add_imx_i2c2(&pcm037_i2c2_data);
634
635 imx31_add_mxc_nand(&pcm037_nand_board_info);
636 imx31_add_mxc_mmc(0, &sdhc_pdata);
637 imx31_add_ipu_core(&mx3_ipu_data);
638 imx31_add_mx3_sdc_fb(&mx3fb_pdata);
639
640 /* CSI */
641 /* Camera power: default - off */
642 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
643 if (!ret)
644 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
645 else
646 iclink_mt9t031.power = NULL;
647
648 pcm037_init_camera();
649
650 platform_device_register(&pcm970_sja1000);
651
652 if (otg_mode_host) {
653 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
654 ULPI_OTG_DRVVBUS_EXT);
655 if (otg_pdata.otg)
656 imx31_add_mxc_ehci_otg(&otg_pdata);
657 }
658
659 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
660 ULPI_OTG_DRVVBUS_EXT);
661 if (usbh2_pdata.otg)
662 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
663
664 if (!otg_mode_host)
665 imx31_add_fsl_usb2_udc(&otg_device_pdata);
666
667 }
668
669 static void __init pcm037_timer_init(void)
670 {
671 mx31_clocks_init(26000000);
672 }
673
674 struct sys_timer pcm037_timer = {
675 .init = pcm037_timer_init,
676 };
677
678 static void __init pcm037_reserve(void)
679 {
680 /* reserve 4 MiB for mx3-camera */
681 mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
682 MX3_CAMERA_BUF_SIZE);
683 memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
684 memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
685 }
686
687 MACHINE_START(PCM037, "Phytec Phycore pcm037")
688 /* Maintainer: Pengutronix */
689 .boot_params = MX3x_PHYS_OFFSET + 0x100,
690 .reserve = pcm037_reserve,
691 .map_io = mx31_map_io,
692 .init_early = imx31_init_early,
693 .init_irq = mx31_init_irq,
694 .timer = &pcm037_timer,
695 .init_machine = pcm037_init,
696 MACHINE_END
Linux with added FPC-III support