ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / arch / arm / mach-msm / include / mach / msm_iomap-7x00.h
blob8f99d97615a0b25f9c3636e3313af016b38d4648
1 /* arch/arm/mach-msm/include/mach/msm_iomap.h
3 * Copyright (C) 2007 Google, Inc.
4 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
5 * Author: Brian Swetland <swetland@google.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 * The MSM peripherals are spread all over across 768MB of physical
18 * space, which makes just having a simple IO_ADDRESS macro to slide
19 * them into the right virtual location rough. Instead, we will
20 * provide a master phys->virt mapping for peripherals here.
24 #ifndef __ASM_ARCH_MSM_IOMAP_7X00_H
25 #define __ASM_ARCH_MSM_IOMAP_7X00_H
27 #include <asm/sizes.h>
29 /* Physical base address and size of peripherals.
30 * Ordered by the virtual base addresses they will be mapped at.
32 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
33 * instruction, otherwise entry-macro.S will not compile.
35 * If you add or remove entries here, you'll want to edit the
36 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
37 * changes.
41 #ifdef __ASSEMBLY__
42 #define IOMEM(x) x
43 #else
44 #define IOMEM(x) ((void __force __iomem *)(x))
45 #endif
47 #define MSM_VIC_BASE IOMEM(0xE0000000)
48 #define MSM_VIC_PHYS 0xC0000000
49 #define MSM_VIC_SIZE SZ_4K
51 #define MSM7X00_CSR_PHYS 0xC0100000
52 #define MSM7X00_CSR_SIZE SZ_4K
54 #define MSM_DMOV_BASE IOMEM(0xE0002000)
55 #define MSM_DMOV_PHYS 0xA9700000
56 #define MSM_DMOV_SIZE SZ_4K
58 #define MSM_GPIO1_BASE IOMEM(0xE0003000)
59 #define MSM_GPIO1_PHYS 0xA9200000
60 #define MSM_GPIO1_SIZE SZ_4K
62 #define MSM_GPIO2_BASE IOMEM(0xE0004000)
63 #define MSM_GPIO2_PHYS 0xA9300000
64 #define MSM_GPIO2_SIZE SZ_4K
66 #define MSM_CLK_CTL_BASE IOMEM(0xE0005000)
67 #define MSM_CLK_CTL_PHYS 0xA8600000
68 #define MSM_CLK_CTL_SIZE SZ_4K
70 #define MSM_SHARED_RAM_BASE IOMEM(0xE0100000)
71 #define MSM_SHARED_RAM_PHYS 0x01F00000
72 #define MSM_SHARED_RAM_SIZE SZ_1M
74 #define MSM_UART1_PHYS 0xA9A00000
75 #define MSM_UART1_SIZE SZ_4K
77 #define MSM_UART2_PHYS 0xA9B00000
78 #define MSM_UART2_SIZE SZ_4K
80 #define MSM_UART3_PHYS 0xA9C00000
81 #define MSM_UART3_SIZE SZ_4K
83 #ifdef CONFIG_MSM_DEBUG_UART
84 #define MSM_DEBUG_UART_BASE 0xE1000000
85 #if CONFIG_MSM_DEBUG_UART == 1
86 #define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
87 #elif CONFIG_MSM_DEBUG_UART == 2
88 #define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
89 #elif CONFIG_MSM_DEBUG_UART == 3
90 #define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
91 #endif
92 #define MSM_DEBUG_UART_SIZE SZ_4K
93 #endif
95 #define MSM_SDC1_PHYS 0xA0400000
96 #define MSM_SDC1_SIZE SZ_4K
98 #define MSM_SDC2_PHYS 0xA0500000
99 #define MSM_SDC2_SIZE SZ_4K
101 #define MSM_SDC3_PHYS 0xA0600000
102 #define MSM_SDC3_SIZE SZ_4K
104 #define MSM_SDC4_PHYS 0xA0700000
105 #define MSM_SDC4_SIZE SZ_4K
107 #define MSM_I2C_PHYS 0xA9900000
108 #define MSM_I2C_SIZE SZ_4K
110 #define MSM_HSUSB_PHYS 0xA0800000
111 #define MSM_HSUSB_SIZE SZ_4K
113 #define MSM_PMDH_PHYS 0xAA600000
114 #define MSM_PMDH_SIZE SZ_4K
116 #define MSM_EMDH_PHYS 0xAA700000
117 #define MSM_EMDH_SIZE SZ_4K
119 #define MSM_MDP_PHYS 0xAA200000
120 #define MSM_MDP_SIZE 0x000F0000
122 #define MSM_MDC_PHYS 0xAA500000
123 #define MSM_MDC_SIZE SZ_1M
125 #define MSM_AD5_PHYS 0xAC000000
126 #define MSM_AD5_SIZE (SZ_1M*13)
129 #endif