arch/arm/mach-omap2/cminst44xx.c

   1 /*
   2  * OMAP4 CM instance functions
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This is needed since CM instances can be in the PRM, PRCM_MPU, CM1,
  12  * or CM2 hardware modules.  For example, the EMU_CM CM instance is in
  13  * the PRM hardware module.  What a mess...
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/errno.h>
  19 #include <linux/err.h>
  20 #include <linux/io.h>
  21
  22 #include <plat/common.h>
  23
  24 #include "cm.h"
  25 #include "cm1_44xx.h"
  26 #include "cm2_44xx.h"
  27 #include "cm44xx.h"
  28 #include "cminst44xx.h"
  29 #include "cm-regbits-34xx.h"
  30 #include "cm-regbits-44xx.h"
  31 #include "prcm44xx.h"
  32 #include "prm44xx.h"
  33 #include "prcm_mpu44xx.h"
  34
  35 static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
  36         [OMAP4430_INVALID_PRCM_PARTITION]       = 0,
  37         [OMAP4430_PRM_PARTITION]                = OMAP4430_PRM_BASE,
  38         [OMAP4430_CM1_PARTITION]                = OMAP4430_CM1_BASE,
  39         [OMAP4430_CM2_PARTITION]                = OMAP4430_CM2_BASE,
  40         [OMAP4430_SCRM_PARTITION]               = 0,
  41         [OMAP4430_PRCM_MPU_PARTITION]           = OMAP4430_PRCM_MPU_BASE,
  42 };
  43
  44 /* Read a register in a CM instance */
  45 u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
  46 {
  47         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  48                part == OMAP4430_INVALID_PRCM_PARTITION ||
  49                !_cm_bases[part]);
  50         return __raw_readl(OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
  51 }
  52
  53 /* Write into a register in a CM instance */
  54 void omap4_cminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
  55 {
  56         BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
  57                part == OMAP4430_INVALID_PRCM_PARTITION ||
  58                !_cm_bases[part]);
  59         __raw_writel(val, OMAP2_L4_IO_ADDRESS(_cm_bases[part] + inst + idx));
  60 }
  61
  62 /* Read-modify-write a register in CM1. Caller must lock */
  63 u32 omap4_cminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
  64                                    s16 idx)
  65 {
  66         u32 v;
  67
  68         v = omap4_cminst_read_inst_reg(part, inst, idx);
  69         v &= ~mask;
  70         v |= bits;
  71         omap4_cminst_write_inst_reg(v, part, inst, idx);
  72
  73         return v;
  74 }
  75
  76 u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
  77 {
  78         return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
  79 }
  80
  81 u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst, s16 idx)
  82 {
  83         return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
  84 }
  85
  86 u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx, u32 mask)
  87 {
  88         u32 v;
  89
  90         v = omap4_cminst_read_inst_reg(part, inst, idx);
  91         v &= mask;
  92         v >>= __ffs(mask);
  93
  94         return v;
  95 }
  96
  97 /*
  98  *
  99  */
 100
 101 /**
 102  * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
 103  * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
 104  * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
 105  * @inst: CM instance register offset (*_INST macro)
 106  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 107  *
 108  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
 109  * will handle the shift itself.
 110  */
 111 static void _clktrctrl_write(u8 c, u8 part, s16 inst, u16 cdoffs)
 112 {
 113         u32 v;
 114
 115         v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
 116         v &= ~OMAP4430_CLKTRCTRL_MASK;
 117         v |= c << OMAP4430_CLKTRCTRL_SHIFT;
 118         omap4_cminst_write_inst_reg(v, part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
 119 }
 120
 121 /**
 122  * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
 123  * @part: PRCM partition ID that the CM_CLKSTCTRL register exists in
 124  * @inst: CM instance register offset (*_INST macro)
 125  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 126  *
 127  * Returns true if the clockdomain referred to by (@part, @inst, @cdoffs)
 128  * is in hardware-supervised idle mode, or 0 otherwise.
 129  */
 130 bool omap4_cminst_is_clkdm_in_hwsup(u8 part, s16 inst, u16 cdoffs)
 131 {
 132         u32 v;
 133
 134         v = omap4_cminst_read_inst_reg(part, inst, cdoffs + OMAP4_CM_CLKSTCTRL);
 135         v &= OMAP4430_CLKTRCTRL_MASK;
 136         v >>= OMAP4430_CLKTRCTRL_SHIFT;
 137
 138         return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
 139 }
 140
 141 /**
 142  * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
 143  * @part: PRCM partition ID that the clockdomain registers exist in
 144  * @inst: CM instance register offset (*_INST macro)
 145  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 146  *
 147  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
 148  * hardware-supervised idle mode.  No return value.
 149  */
 150 void omap4_cminst_clkdm_enable_hwsup(u8 part, s16 inst, u16 cdoffs)
 151 {
 152         _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, part, inst, cdoffs);
 153 }
 154
 155 /**
 156  * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
 157  * @part: PRCM partition ID that the clockdomain registers exist in
 158  * @inst: CM instance register offset (*_INST macro)
 159  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 160  *
 161  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into
 162  * software-supervised idle mode, i.e., controlled manually by the
 163  * Linux OMAP clockdomain code.  No return value.
 164  */
 165 void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs)
 166 {
 167         _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, part, inst, cdoffs);
 168 }
 169
 170 /**
 171  * omap4_cminst_clkdm_force_sleep - try to put a clockdomain into idle
 172  * @part: PRCM partition ID that the clockdomain registers exist in
 173  * @inst: CM instance register offset (*_INST macro)
 174  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 175  *
 176  * Put a clockdomain referred to by (@part, @inst, @cdoffs) into idle
 177  * No return value.
 178  */
 179 void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs)
 180 {
 181         _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, part, inst, cdoffs);
 182 }
 183
 184 /**
 185  * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
 186  * @part: PRCM partition ID that the clockdomain registers exist in
 187  * @inst: CM instance register offset (*_INST macro)
 188  * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
 189  *
 190  * Take a clockdomain referred to by (@part, @inst, @cdoffs) out of idle,
 191  * waking it up.  No return value.
 192  */
 193 void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
 194 {
 195         _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, part, inst, cdoffs);
 196 }
 197
 198 /*
 199  *
 200  */
 201
 202 /**
 203  * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
 204  * @clkctrl_reg: CLKCTRL module address
 205  *
 206  * Wait for the module IDLEST to be functional. If the idle state is in any
 207  * the non functional state (trans, idle or disabled), module and thus the
 208  * sysconfig cannot be accessed and will probably lead to an "imprecise
 209  * external abort"
 210  *
 211  * Module idle state:
 212  *   0x0 func:     Module is fully functional, including OCP
 213  *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
 214  *                 abortion
 215  *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
 216  *                 using separate functional clock
 217  *   0x3 disabled: Module is disabled and cannot be accessed
 218  *
 219  */
 220 int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
 221 {
 222         int i = 0;
 223
 224         if (!clkctrl_reg)
 225                 return 0;
 226
 227         omap_test_timeout((
 228                 ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
 229                  (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
 230                   OMAP4430_IDLEST_SHIFT) == 0x2)),
 231                 MAX_MODULE_READY_TIME, i);
 232
 233         return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
 234 }
 235