| blob | 413684660aad22d4d94f1ceffe1c6ca43be20f74 |
1 /*
2 * linux/arch/arm/mm/proc-arm1026.S: MMU functions for ARM1026EJ-S
3 *
4 * Copyright (C) 2000 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 * hacked for non-paged-MM by Hyok S. Choi, 2003.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 *
14 * These are the low level assembler for performing cache and TLB
15 * functions on the ARM1026EJ-S.
16 */
17 #include <linux/linkage.h>
18 #include <linux/init.h>
19 #include <asm/assembler.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/hwcap.h>
22 #include <asm/pgtable-hwdef.h>
23 #include <asm/pgtable.h>
24 #include <asm/ptrace.h>
26 #include "proc-macros.S"
28 /*
29 * This is the maximum size of an area which will be invalidated
30 * using the single invalidate entry instructions. Anything larger
31 * than this, and we go for the whole cache.
32 *
33 * This value should be chosen such that we choose the cheapest
34 * alternative.
35 */
36 #define MAX_AREA_SIZE 32768
38 /*
39 * The size of one data cache line.
40 */
41 #define CACHE_DLINESIZE 32
43 /*
44 * The number of data cache segments.
45 */
46 #define CACHE_DSEGMENTS 16
48 /*
49 * The number of lines in a cache segment.
50 */
51 #define CACHE_DENTRIES 64
53 /*
54 * This is the size at which it becomes more efficient to
55 * clean the whole cache, rather than using the individual
56 * cache line maintenance instructions.
57 */
58 #define CACHE_DLIMIT 32768
60 .text
61 /*
62 * cpu_arm1026_proc_init()
63 */
64 ENTRY(cpu_arm1026_proc_init)
65 mov pc, lr
67 /*
68 * cpu_arm1026_proc_fin()
69 */
70 ENTRY(cpu_arm1026_proc_fin)
71 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
72 bic r0, r0, #0x1000 @ ...i............
73 bic r0, r0, #0x000e @ ............wca.
74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 mov pc, lr
77 /*
78 * cpu_arm1026_reset(loc)
79 *
80 * Perform a soft reset of the system. Put the CPU into the
81 * same state as it would be if it had been reset, and branch
82 * to what would be the reset vector.
83 *
84 * loc: location to jump to for soft reset
85 */
86 .align 5
87 ENTRY(cpu_arm1026_reset)
88 mov ip, #0
89 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
90 mcr p15, 0, ip, c7, c10, 4 @ drain WB
91 #ifdef CONFIG_MMU
92 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
93 #endif
94 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
95 bic ip, ip, #0x000f @ ............wcam
96 bic ip, ip, #0x1100 @ ...i...s........
97 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
98 mov pc, r0
100 /*
101 * cpu_arm1026_do_idle()
102 */
103 .align 5
104 ENTRY(cpu_arm1026_do_idle)
105 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
106 mov pc, lr
108 /* ================================= CACHE ================================ */
110 .align 5
112 /*
113 * flush_icache_all()
114 *
115 * Unconditionally clean and invalidate the entire icache.
116 */
117 ENTRY(arm1026_flush_icache_all)
118 #ifndef CONFIG_CPU_ICACHE_DISABLE
119 mov r0, #0
120 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
121 #endif
122 mov pc, lr
123 ENDPROC(arm1026_flush_icache_all)
125 /*
126 * flush_user_cache_all()
127 *
128 * Invalidate all cache entries in a particular address
129 * space.
130 */
131 ENTRY(arm1026_flush_user_cache_all)
132 /* FALLTHROUGH */
133 /*
134 * flush_kern_cache_all()
135 *
136 * Clean and invalidate the entire cache.
137 */
138 ENTRY(arm1026_flush_kern_cache_all)
139 mov r2, #VM_EXEC
140 mov ip, #0
141 __flush_whole_cache:
142 #ifndef CONFIG_CPU_DCACHE_DISABLE
143 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
144 bne 1b
145 #endif
146 tst r2, #VM_EXEC
147 #ifndef CONFIG_CPU_ICACHE_DISABLE
148 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
149 #endif
150 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
151 mov pc, lr
153 /*
154 * flush_user_cache_range(start, end, flags)
155 *
156 * Invalidate a range of cache entries in the specified
157 * address space.
158 *
159 * - start - start address (inclusive)
160 * - end - end address (exclusive)
161 * - flags - vm_flags for this space
162 */
163 ENTRY(arm1026_flush_user_cache_range)
164 mov ip, #0
165 sub r3, r1, r0 @ calculate total size
166 cmp r3, #CACHE_DLIMIT
167 bhs __flush_whole_cache
169 #ifndef CONFIG_CPU_DCACHE_DISABLE
170 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
171 add r0, r0, #CACHE_DLINESIZE
172 cmp r0, r1
173 blo 1b
174 #endif
175 tst r2, #VM_EXEC
176 #ifndef CONFIG_CPU_ICACHE_DISABLE
177 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
178 #endif
179 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
180 mov pc, lr
182 /*
183 * coherent_kern_range(start, end)
184 *
185 * Ensure coherency between the Icache and the Dcache in the
186 * region described by start. If you have non-snooping
187 * Harvard caches, you need to implement this function.
188 *
189 * - start - virtual start address
190 * - end - virtual end address
191 */
192 ENTRY(arm1026_coherent_kern_range)
193 /* FALLTHROUGH */
194 /*
195 * coherent_user_range(start, end)
196 *
197 * Ensure coherency between the Icache and the Dcache in the
198 * region described by start. If you have non-snooping
199 * Harvard caches, you need to implement this function.
200 *
201 * - start - virtual start address
202 * - end - virtual end address
203 */
204 ENTRY(arm1026_coherent_user_range)
205 mov ip, #0
206 bic r0, r0, #CACHE_DLINESIZE - 1
207 1:
208 #ifndef CONFIG_CPU_DCACHE_DISABLE
209 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
210 #endif
211 #ifndef CONFIG_CPU_ICACHE_DISABLE
212 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
213 #endif
214 add r0, r0, #CACHE_DLINESIZE
215 cmp r0, r1
216 blo 1b
217 mcr p15, 0, ip, c7, c10, 4 @ drain WB
218 mov pc, lr
220 /*
221 * flush_kern_dcache_area(void *addr, size_t size)
222 *
223 * Ensure no D cache aliasing occurs, either with itself or
224 * the I cache
225 *
226 * - addr - kernel address
227 * - size - region size
228 */
229 ENTRY(arm1026_flush_kern_dcache_area)
230 mov ip, #0
231 #ifndef CONFIG_CPU_DCACHE_DISABLE
232 add r1, r0, r1
233 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
234 add r0, r0, #CACHE_DLINESIZE
235 cmp r0, r1
236 blo 1b
237 #endif
238 mcr p15, 0, ip, c7, c10, 4 @ drain WB
239 mov pc, lr
241 /*
242 * dma_inv_range(start, end)
243 *
244 * Invalidate (discard) the specified virtual address range.
245 * May not write back any entries. If 'start' or 'end'
246 * are not cache line aligned, those lines must be written
247 * back.
248 *
249 * - start - virtual start address
250 * - end - virtual end address
251 *
252 * (same as v4wb)
253 */
254 arm1026_dma_inv_range:
255 mov ip, #0
256 #ifndef CONFIG_CPU_DCACHE_DISABLE
257 tst r0, #CACHE_DLINESIZE - 1
258 bic r0, r0, #CACHE_DLINESIZE - 1
259 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
260 tst r1, #CACHE_DLINESIZE - 1
261 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
262 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
263 add r0, r0, #CACHE_DLINESIZE
264 cmp r0, r1
265 blo 1b
266 #endif
267 mcr p15, 0, ip, c7, c10, 4 @ drain WB
268 mov pc, lr
270 /*
271 * dma_clean_range(start, end)
272 *
273 * Clean the specified virtual address range.
274 *
275 * - start - virtual start address
276 * - end - virtual end address
277 *
278 * (same as v4wb)
279 */
280 arm1026_dma_clean_range:
281 mov ip, #0
282 #ifndef CONFIG_CPU_DCACHE_DISABLE
283 bic r0, r0, #CACHE_DLINESIZE - 1
284 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
285 add r0, r0, #CACHE_DLINESIZE
286 cmp r0, r1
287 blo 1b
288 #endif
289 mcr p15, 0, ip, c7, c10, 4 @ drain WB
290 mov pc, lr
292 /*
293 * dma_flush_range(start, end)
294 *
295 * Clean and invalidate the specified virtual address range.
296 *
297 * - start - virtual start address
298 * - end - virtual end address
299 */
300 ENTRY(arm1026_dma_flush_range)
301 mov ip, #0
302 #ifndef CONFIG_CPU_DCACHE_DISABLE
303 bic r0, r0, #CACHE_DLINESIZE - 1
304 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
305 add r0, r0, #CACHE_DLINESIZE
306 cmp r0, r1
307 blo 1b
308 #endif
309 mcr p15, 0, ip, c7, c10, 4 @ drain WB
310 mov pc, lr
312 /*
313 * dma_map_area(start, size, dir)
314 * - start - kernel virtual start address
315 * - size - size of region
316 * - dir - DMA direction
317 */
318 ENTRY(arm1026_dma_map_area)
319 add r1, r1, r0
320 cmp r2, #DMA_TO_DEVICE
321 beq arm1026_dma_clean_range
322 bcs arm1026_dma_inv_range
323 b arm1026_dma_flush_range
324 ENDPROC(arm1026_dma_map_area)
326 /*
327 * dma_unmap_area(start, size, dir)
328 * - start - kernel virtual start address
329 * - size - size of region
330 * - dir - DMA direction
331 */
332 ENTRY(arm1026_dma_unmap_area)
333 mov pc, lr
334 ENDPROC(arm1026_dma_unmap_area)
336 ENTRY(arm1026_cache_fns)
337 .long arm1026_flush_icache_all
338 .long arm1026_flush_kern_cache_all
339 .long arm1026_flush_user_cache_all
340 .long arm1026_flush_user_cache_range
341 .long arm1026_coherent_kern_range
342 .long arm1026_coherent_user_range
343 .long arm1026_flush_kern_dcache_area
344 .long arm1026_dma_map_area
345 .long arm1026_dma_unmap_area
346 .long arm1026_dma_flush_range
348 .align 5
349 ENTRY(cpu_arm1026_dcache_clean_area)
350 #ifndef CONFIG_CPU_DCACHE_DISABLE
351 mov ip, #0
352 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 add r0, r0, #CACHE_DLINESIZE
354 subs r1, r1, #CACHE_DLINESIZE
355 bhi 1b
356 #endif
357 mov pc, lr
359 /* =============================== PageTable ============================== */
361 /*
362 * cpu_arm1026_switch_mm(pgd)
363 *
364 * Set the translation base pointer to be as described by pgd.
365 *
366 * pgd: new page tables
367 */
368 .align 5
369 ENTRY(cpu_arm1026_switch_mm)
370 #ifdef CONFIG_MMU
371 mov r1, #0
372 #ifndef CONFIG_CPU_DCACHE_DISABLE
373 1: mrc p15, 0, r15, c7, c14, 3 @ test, clean, invalidate
374 bne 1b
375 #endif
376 #ifndef CONFIG_CPU_ICACHE_DISABLE
377 mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
378 #endif
379 mcr p15, 0, r1, c7, c10, 4 @ drain WB
380 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
381 mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
382 #endif
383 mov pc, lr
385 /*
386 * cpu_arm1026_set_pte_ext(ptep, pte, ext)
387 *
388 * Set a PTE and flush it out
389 */
390 .align 5
391 ENTRY(cpu_arm1026_set_pte_ext)
392 #ifdef CONFIG_MMU
393 armv3_set_pte_ext
394 mov r0, r0
395 #ifndef CONFIG_CPU_DCACHE_DISABLE
396 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
397 #endif
398 #endif /* CONFIG_MMU */
399 mov pc, lr
402 __CPUINIT
404 .type __arm1026_setup, #function
405 __arm1026_setup:
406 mov r0, #0
407 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
408 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
409 #ifdef CONFIG_MMU
410 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
411 mcr p15, 0, r4, c2, c0 @ load page table pointer
412 #endif
413 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
414 mov r0, #4 @ explicitly disable writeback
415 mcr p15, 7, r0, c15, c0, 0
416 #endif
417 adr r5, arm1026_crval
418 ldmia r5, {r5, r6}
419 mrc p15, 0, r0, c1, c0 @ get control register v4
420 bic r0, r0, r5
421 orr r0, r0, r6
422 #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
423 orr r0, r0, #0x4000 @ .R.. .... .... ....
424 #endif
425 mov pc, lr
426 .size __arm1026_setup, . - __arm1026_setup
428 /*
429 * R
430 * .RVI ZFRS BLDP WCAM
431 * .011 1001 ..11 0101
432 *
433 */
434 .type arm1026_crval, #object
435 arm1026_crval:
436 crval clear=0x00007f3f, mmuset=0x00003935, ucset=0x00001934
438 __INITDATA
440 /*
441 * Purpose : Function pointers used to access above functions - all calls
442 * come through these
443 */
444 .type arm1026_processor_functions, #object
445 arm1026_processor_functions:
446 .word v5t_early_abort
447 .word legacy_pabort
448 .word cpu_arm1026_proc_init
449 .word cpu_arm1026_proc_fin
450 .word cpu_arm1026_reset
451 .word cpu_arm1026_do_idle
452 .word cpu_arm1026_dcache_clean_area
453 .word cpu_arm1026_switch_mm
454 .word cpu_arm1026_set_pte_ext
455 .word 0
456 .word 0
457 .word 0
458 .size arm1026_processor_functions, . - arm1026_processor_functions
460 .section .rodata
462 .type cpu_arch_name, #object
463 cpu_arch_name:
464 .asciz "armv5tej"
465 .size cpu_arch_name, . - cpu_arch_name
467 .type cpu_elf_name, #object
468 cpu_elf_name:
469 .asciz "v5"
470 .size cpu_elf_name, . - cpu_elf_name
471 .align
473 .type cpu_arm1026_name, #object
474 cpu_arm1026_name:
475 .asciz "ARM1026EJ-S"
476 .size cpu_arm1026_name, . - cpu_arm1026_name
478 .align
480 .section ".proc.info.init", #alloc, #execinstr
482 .type __arm1026_proc_info,#object
483 __arm1026_proc_info:
484 .long 0x4106a260 @ ARM 1026EJ-S (v5TEJ)
485 .long 0xff0ffff0
486 .long PMD_TYPE_SECT | \
487 PMD_BIT4 | \
488 PMD_SECT_AP_WRITE | \
489 PMD_SECT_AP_READ
490 .long PMD_TYPE_SECT | \
491 PMD_BIT4 | \
492 PMD_SECT_AP_WRITE | \
493 PMD_SECT_AP_READ
494 b __arm1026_setup
495 .long cpu_arch_name
496 .long cpu_elf_name
497 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
498 .long cpu_arm1026_name
499 .long arm1026_processor_functions
500 .long v4wbi_tlb_fns
501 .long v4wb_user_fns
502 .long arm1026_cache_fns
503 .size __arm1026_proc_info, . - __arm1026_proc_info