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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / arch / xtensa / variants / s6000 / include / variant / tie-asm.h
blobf02d0a3a2e20d7640cf1a3f56d124e5ef0a0f427
1 /*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13 #ifndef _XTENSA_CORE_TIE_ASM_H
14 #define _XTENSA_CORE_TIE_ASM_H
15
16 /* Selection parameter values for save-area save/restore macros: */
17 /* Option vs. TIE: */
18 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20 /* Whether used automatically by compiler: */
21 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23 /* ABI handling across function calls: */
24 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27 /* Misc */
28 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (16 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
40 xchal_sa_align \ptr, 0, 1024-4, 4, 4
41 rsr \at1, BR // boolean option
42 s32i \at1, \ptr, .Lxchal_ofs_ + 0
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44 .endif
45 .endm // xchal_ncp_store
46
47 /* Macro to save all non-coprocessor (extra) custom TIE and optional state
48 * (not including zero-overhead loop registers).
49 * Save area ptr (clobbered): ptr (16 byte aligned)
50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51 */
52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53 xchal_sa_start \continue, \ofs
54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
55 xchal_sa_align \ptr, 0, 1024-4, 4, 4
56 l32i \at1, \ptr, .Lxchal_ofs_ + 0
57 wsr \at1, BR // boolean option
58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59 .endif
60 .endm // xchal_ncp_load
61
62
63
64 #define XCHAL_NCP_NUM_ATMPS 1
65
66
67
68 /* Macro to save the state of TIE coprocessor FPU.
69 * Save area ptr (clobbered): ptr (16 byte aligned)
70 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
71 */
72 #define xchal_cp_FPU_store xchal_cp0_store
73 /* #define xchal_cp_FPU_store_a2 xchal_cp0_store a2 a3 a4 a5 a6 */
74 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
75 xchal_sa_start \continue, \ofs
76 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
77 xchal_sa_align \ptr, 0, 0, 1, 16
78 rur232 \at1 // FCR
79 s32i \at1, \ptr, 0
80 rur233 \at1 // FSR
81 s32i \at1, \ptr, 4
82 SSI f0, \ptr, 8
83 SSI f1, \ptr, 12
84 SSI f2, \ptr, 16
85 SSI f3, \ptr, 20
86 SSI f4, \ptr, 24
87 SSI f5, \ptr, 28
88 SSI f6, \ptr, 32
89 SSI f7, \ptr, 36
90 SSI f8, \ptr, 40
91 SSI f9, \ptr, 44
92 SSI f10, \ptr, 48
93 SSI f11, \ptr, 52
94 SSI f12, \ptr, 56
95 SSI f13, \ptr, 60
96 SSI f14, \ptr, 64
97 SSI f15, \ptr, 68
98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
99 .endif
100 .endm // xchal_cp0_store
101
102 /* Macro to restore the state of TIE coprocessor FPU.
103 * Save area ptr (clobbered): ptr (16 byte aligned)
104 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
105 */
106 #define xchal_cp_FPU_load xchal_cp0_load
107 /* #define xchal_cp_FPU_load_a2 xchal_cp0_load a2 a3 a4 a5 a6 */
108 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
109 xchal_sa_start \continue, \ofs
110 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
111 xchal_sa_align \ptr, 0, 0, 1, 16
112 l32i \at1, \ptr, 0
113 wur232 \at1 // FCR
114 l32i \at1, \ptr, 4
115 wur233 \at1 // FSR
116 LSI f0, \ptr, 8
117 LSI f1, \ptr, 12
118 LSI f2, \ptr, 16
119 LSI f3, \ptr, 20
120 LSI f4, \ptr, 24
121 LSI f5, \ptr, 28
122 LSI f6, \ptr, 32
123 LSI f7, \ptr, 36
124 LSI f8, \ptr, 40
125 LSI f9, \ptr, 44
126 LSI f10, \ptr, 48
127 LSI f11, \ptr, 52
128 LSI f12, \ptr, 56
129 LSI f13, \ptr, 60
130 LSI f14, \ptr, 64
131 LSI f15, \ptr, 68
132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
133 .endif
134 .endm // xchal_cp0_load
135
136 #define XCHAL_CP0_NUM_ATMPS 1
137
138 /* Macro to save the state of TIE coprocessor XAD.
139 * Save area ptr (clobbered): ptr (16 byte aligned)
140 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
141 */
142 #define xchal_cp_XAD_store xchal_cp6_store
143 /* #define xchal_cp_XAD_store_a2 xchal_cp6_store a2 a3 a4 a5 a6 */
144 .macro xchal_cp6_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
145 xchal_sa_start \continue, \ofs
146 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
147 xchal_sa_align \ptr, 0, 0, 1, 16
148 rur0 \at1 // LDCBHI
149 s32i \at1, \ptr, 0
150 rur1 \at1 // LDCBLO
151 s32i \at1, \ptr, 4
152 rur2 \at1 // STCBHI
153 s32i \at1, \ptr, 8
154 rur3 \at1 // STCBLO
155 s32i \at1, \ptr, 12
156 rur8 \at1 // LDBRBASE
157 s32i \at1, \ptr, 16
158 rur9 \at1 // LDBROFF
159 s32i \at1, \ptr, 20
160 rur10 \at1 // LDBRINC
161 s32i \at1, \ptr, 24
162 rur11 \at1 // STBRBASE
163 s32i \at1, \ptr, 28
164 rur12 \at1 // STBROFF
165 s32i \at1, \ptr, 32
166 rur13 \at1 // STBRINC
167 s32i \at1, \ptr, 36
168 rur24 \at1 // SCRATCH0
169 s32i \at1, \ptr, 40
170 rur25 \at1 // SCRATCH1
171 s32i \at1, \ptr, 44
172 rur26 \at1 // SCRATCH2
173 s32i \at1, \ptr, 48
174 rur27 \at1 // SCRATCH3
175 s32i \at1, \ptr, 52
176 WRAS128I wra0, \ptr, 64
177 WRAS128I wra1, \ptr, 80
178 WRAS128I wra2, \ptr, 96
179 WRAS128I wra3, \ptr, 112
180 WRAS128I wra4, \ptr, 128
181 WRAS128I wra5, \ptr, 144
182 WRAS128I wra6, \ptr, 160
183 WRAS128I wra7, \ptr, 176
184 WRAS128I wra8, \ptr, 192
185 WRAS128I wra9, \ptr, 208
186 WRAS128I wra10, \ptr, 224
187 WRAS128I wra11, \ptr, 240
188 WRAS128I wra12, \ptr, 256
189 WRAS128I wra13, \ptr, 272
190 WRAS128I wra14, \ptr, 288
191 WRAS128I wra15, \ptr, 304
192 WRBS128I wrb0, \ptr, 320
193 WRBS128I wrb1, \ptr, 336
194 WRBS128I wrb2, \ptr, 352
195 WRBS128I wrb3, \ptr, 368
196 WRBS128I wrb4, \ptr, 384
197 WRBS128I wrb5, \ptr, 400
198 WRBS128I wrb6, \ptr, 416
199 WRBS128I wrb7, \ptr, 432
200 WRBS128I wrb8, \ptr, 448
201 WRBS128I wrb9, \ptr, 464
202 WRBS128I wrb10, \ptr, 480
203 WRBS128I wrb11, \ptr, 496
204 WRBS128I wrb12, \ptr, 512
205 WRBS128I wrb13, \ptr, 528
206 WRBS128I wrb14, \ptr, 544
207 WRBS128I wrb15, \ptr, 560
208 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
209 .endif
210 .endm // xchal_cp6_store
211
212 /* Macro to restore the state of TIE coprocessor XAD.
213 * Save area ptr (clobbered): ptr (16 byte aligned)
214 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
215 */
216 #define xchal_cp_XAD_load xchal_cp6_load
217 /* #define xchal_cp_XAD_load_a2 xchal_cp6_load a2 a3 a4 a5 a6 */
218 .macro xchal_cp6_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
219 xchal_sa_start \continue, \ofs
220 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
221 xchal_sa_align \ptr, 0, 0, 1, 16
222 l32i \at1, \ptr, 0
223 wur0 \at1 // LDCBHI
224 l32i \at1, \ptr, 4
225 wur1 \at1 // LDCBLO
226 l32i \at1, \ptr, 8
227 wur2 \at1 // STCBHI
228 l32i \at1, \ptr, 12
229 wur3 \at1 // STCBLO
230 l32i \at1, \ptr, 16
231 wur8 \at1 // LDBRBASE
232 l32i \at1, \ptr, 20
233 wur9 \at1 // LDBROFF
234 l32i \at1, \ptr, 24
235 wur10 \at1 // LDBRINC
236 l32i \at1, \ptr, 28
237 wur11 \at1 // STBRBASE
238 l32i \at1, \ptr, 32
239 wur12 \at1 // STBROFF
240 l32i \at1, \ptr, 36
241 wur13 \at1 // STBRINC
242 l32i \at1, \ptr, 40
243 wur24 \at1 // SCRATCH0
244 l32i \at1, \ptr, 44
245 wur25 \at1 // SCRATCH1
246 l32i \at1, \ptr, 48
247 wur26 \at1 // SCRATCH2
248 l32i \at1, \ptr, 52
249 wur27 \at1 // SCRATCH3
250 WRBL128I wrb0, \ptr, 320
251 WRBL128I wrb1, \ptr, 336
252 WRBL128I wrb2, \ptr, 352
253 WRBL128I wrb3, \ptr, 368
254 WRBL128I wrb4, \ptr, 384
255 WRBL128I wrb5, \ptr, 400
256 WRBL128I wrb6, \ptr, 416
257 WRBL128I wrb7, \ptr, 432
258 WRBL128I wrb8, \ptr, 448
259 WRBL128I wrb9, \ptr, 464
260 WRBL128I wrb10, \ptr, 480
261 WRBL128I wrb11, \ptr, 496
262 WRBL128I wrb12, \ptr, 512
263 WRBL128I wrb13, \ptr, 528
264 WRBL128I wrb14, \ptr, 544
265 WRBL128I wrb15, \ptr, 560
266 WRAL128I wra0, \ptr, 64
267 WRAL128I wra1, \ptr, 80
268 WRAL128I wra2, \ptr, 96
269 WRAL128I wra3, \ptr, 112
270 WRAL128I wra4, \ptr, 128
271 WRAL128I wra5, \ptr, 144
272 WRAL128I wra6, \ptr, 160
273 WRAL128I wra7, \ptr, 176
274 WRAL128I wra8, \ptr, 192
275 WRAL128I wra9, \ptr, 208
276 WRAL128I wra10, \ptr, 224
277 WRAL128I wra11, \ptr, 240
278 WRAL128I wra12, \ptr, 256
279 WRAL128I wra13, \ptr, 272
280 WRAL128I wra14, \ptr, 288
281 WRAL128I wra15, \ptr, 304
282 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
283 .endif
284 .endm // xchal_cp6_load
285
286 #define XCHAL_CP6_NUM_ATMPS 1
287 #define XCHAL_SA_NUM_ATMPS 1
288
289 /* Empty macros for unconfigured coprocessors: */
290 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
291 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
292 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
293 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
294 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
295 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
296 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
297 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
298 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
299 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
300 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
301 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
302
303 #endif /*_XTENSA_CORE_TIE_ASM_H*/
304
Linux with added FPC-III support