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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / ata / sata_dwc_460ex.c
blobdc88a39e7db8b04c9a2ec3e85ed888ee90194e69
1 /*
2 * drivers/ata/sata_dwc_460ex.c
3 *
4 * Synopsys DesignWare Cores (DWC) SATA host driver
5 *
6 * Author: Mark Miesfeld <mmiesfeld@amcc.com>
7 *
8 * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
9 * Copyright 2008 DENX Software Engineering
10 *
11 * Based on versions provided by AMCC and Synopsys which are:
12 * Copyright 2006 Applied Micro Circuits Corporation
13 * COPYRIGHT (C) 2005 SYNOPSYS, INC. ALL RIGHTS RESERVED
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20
21 #ifdef CONFIG_SATA_DWC_DEBUG
22 #define DEBUG
23 #endif
24
25 #ifdef CONFIG_SATA_DWC_VDEBUG
26 #define VERBOSE_DEBUG
27 #define DEBUG_NCQ
28 #endif
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/device.h>
34 #include <linux/of_platform.h>
35 #include <linux/platform_device.h>
36 #include <linux/libata.h>
37 #include <linux/slab.h>
38 #include "libata.h"
39
40 #include <scsi/scsi_host.h>
41 #include <scsi/scsi_cmnd.h>
42
43 /* These two are defined in "libata.h" */
44 #undef DRV_NAME
45 #undef DRV_VERSION
46 #define DRV_NAME "sata-dwc"
47 #define DRV_VERSION "1.3"
48
49 /* SATA DMA driver Globals */
50 #define DMA_NUM_CHANS 1
51 #define DMA_NUM_CHAN_REGS 8
52
53 /* SATA DMA Register definitions */
54 #define AHB_DMA_BRST_DFLT 64 /* 16 data items burst length*/
55
56 struct dmareg {
57 u32 low; /* Low bits 0-31 */
58 u32 high; /* High bits 32-63 */
59 };
60
61 /* DMA Per Channel registers */
62 struct dma_chan_regs {
63 struct dmareg sar; /* Source Address */
64 struct dmareg dar; /* Destination address */
65 struct dmareg llp; /* Linked List Pointer */
66 struct dmareg ctl; /* Control */
67 struct dmareg sstat; /* Source Status not implemented in core */
68 struct dmareg dstat; /* Destination Status not implemented in core*/
69 struct dmareg sstatar; /* Source Status Address not impl in core */
70 struct dmareg dstatar; /* Destination Status Address not implemente */
71 struct dmareg cfg; /* Config */
72 struct dmareg sgr; /* Source Gather */
73 struct dmareg dsr; /* Destination Scatter */
74 };
75
76 /* Generic Interrupt Registers */
77 struct dma_interrupt_regs {
78 struct dmareg tfr; /* Transfer Interrupt */
79 struct dmareg block; /* Block Interrupt */
80 struct dmareg srctran; /* Source Transfer Interrupt */
81 struct dmareg dsttran; /* Dest Transfer Interrupt */
82 struct dmareg error; /* Error */
83 };
84
85 struct ahb_dma_regs {
86 struct dma_chan_regs chan_regs[DMA_NUM_CHAN_REGS];
87 struct dma_interrupt_regs interrupt_raw; /* Raw Interrupt */
88 struct dma_interrupt_regs interrupt_status; /* Interrupt Status */
89 struct dma_interrupt_regs interrupt_mask; /* Interrupt Mask */
90 struct dma_interrupt_regs interrupt_clear; /* Interrupt Clear */
91 struct dmareg statusInt; /* Interrupt combined*/
92 struct dmareg rq_srcreg; /* Src Trans Req */
93 struct dmareg rq_dstreg; /* Dst Trans Req */
94 struct dmareg rq_sgl_srcreg; /* Sngl Src Trans Req*/
95 struct dmareg rq_sgl_dstreg; /* Sngl Dst Trans Req*/
96 struct dmareg rq_lst_srcreg; /* Last Src Trans Req*/
97 struct dmareg rq_lst_dstreg; /* Last Dst Trans Req*/
98 struct dmareg dma_cfg; /* DMA Config */
99 struct dmareg dma_chan_en; /* DMA Channel Enable*/
100 struct dmareg dma_id; /* DMA ID */
101 struct dmareg dma_test; /* DMA Test */
102 struct dmareg res1; /* reserved */
103 struct dmareg res2; /* reserved */
104 /*
105 * DMA Comp Params
106 * Param 6 = dma_param[0], Param 5 = dma_param[1],
107 * Param 4 = dma_param[2] ...
108 */
109 struct dmareg dma_params[6];
110 };
111
112 /* Data structure for linked list item */
113 struct lli {
114 u32 sar; /* Source Address */
115 u32 dar; /* Destination address */
116 u32 llp; /* Linked List Pointer */
117 struct dmareg ctl; /* Control */
118 struct dmareg dstat; /* Destination Status */
119 };
120
121 enum {
122 SATA_DWC_DMAC_LLI_SZ = (sizeof(struct lli)),
123 SATA_DWC_DMAC_LLI_NUM = 256,
124 SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
125 SATA_DWC_DMAC_LLI_NUM),
126 SATA_DWC_DMAC_TWIDTH_BYTES = 4,
127 SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
128 SATA_DWC_DMAC_TWIDTH_BYTES),
129 };
130
131 /* DMA Register Operation Bits */
132 enum {
133 DMA_EN = 0x00000001, /* Enable AHB DMA */
134 DMA_CTL_LLP_SRCEN = 0x10000000, /* Blk chain enable Src */
135 DMA_CTL_LLP_DSTEN = 0x08000000, /* Blk chain enable Dst */
136 };
137
138 #define DMA_CTL_BLK_TS(size) ((size) & 0x000000FFF) /* Blk Transfer size */
139 #define DMA_CHANNEL(ch) (0x00000001 << (ch)) /* Select channel */
140 /* Enable channel */
141 #define DMA_ENABLE_CHAN(ch) ((0x00000001 << (ch)) | \
142 ((0x000000001 << (ch)) << 8))
143 /* Disable channel */
144 #define DMA_DISABLE_CHAN(ch) (0x00000000 | ((0x000000001 << (ch)) << 8))
145 /* Transfer Type & Flow Controller */
146 #define DMA_CTL_TTFC(type) (((type) & 0x7) << 20)
147 #define DMA_CTL_SMS(num) (((num) & 0x3) << 25) /* Src Master Select */
148 #define DMA_CTL_DMS(num) (((num) & 0x3) << 23)/* Dst Master Select */
149 /* Src Burst Transaction Length */
150 #define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
151 /* Dst Burst Transaction Length */
152 #define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
153 /* Source Transfer Width */
154 #define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
155 /* Destination Transfer Width */
156 #define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
157
158 /* Assign HW handshaking interface (x) to destination / source peripheral */
159 #define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
160 #define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
161 #define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
162
163 /*
164 * This define is used to set block chaining disabled in the control low
165 * register. It is already in little endian format so it can be &'d dirctly.
166 * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
167 */
168 enum {
169 DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
170 DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
171 DMA_CTL_TTFC_M2P_PER = 0x00000003, /* Mem to per, peripheral cntr */
172 DMA_CTL_SINC_INC = 0x00000000, /* Source Address Increment */
173 DMA_CTL_SINC_DEC = 0x00000200,
174 DMA_CTL_SINC_NOCHANGE = 0x00000400,
175 DMA_CTL_DINC_INC = 0x00000000, /* Destination Address Increment */
176 DMA_CTL_DINC_DEC = 0x00000080,
177 DMA_CTL_DINC_NOCHANGE = 0x00000100,
178 DMA_CTL_INT_EN = 0x00000001, /* Interrupt Enable */
179
180 /* Channel Configuration Register high bits */
181 DMA_CFG_FCMOD_REQ = 0x00000001, /* Flow Control - request based */
182 DMA_CFG_PROTCTL = (0x00000003 << 2),/* Protection Control */
183
184 /* Channel Configuration Register low bits */
185 DMA_CFG_RELD_DST = 0x80000000, /* Reload Dest / Src Addr */
186 DMA_CFG_RELD_SRC = 0x40000000,
187 DMA_CFG_HS_SELSRC = 0x00000800, /* Software handshake Src/ Dest */
188 DMA_CFG_HS_SELDST = 0x00000400,
189 DMA_CFG_FIFOEMPTY = (0x00000001 << 9), /* FIFO Empty bit */
190
191 /* Channel Linked List Pointer Register */
192 DMA_LLP_AHBMASTER1 = 0, /* List Master Select */
193 DMA_LLP_AHBMASTER2 = 1,
194
195 SATA_DWC_MAX_PORTS = 1,
196
197 SATA_DWC_SCR_OFFSET = 0x24,
198 SATA_DWC_REG_OFFSET = 0x64,
199 };
200
201 /* DWC SATA Registers */
202 struct sata_dwc_regs {
203 u32 fptagr; /* 1st party DMA tag */
204 u32 fpbor; /* 1st party DMA buffer offset */
205 u32 fptcr; /* 1st party DMA Xfr count */
206 u32 dmacr; /* DMA Control */
207 u32 dbtsr; /* DMA Burst Transac size */
208 u32 intpr; /* Interrupt Pending */
209 u32 intmr; /* Interrupt Mask */
210 u32 errmr; /* Error Mask */
211 u32 llcr; /* Link Layer Control */
212 u32 phycr; /* PHY Control */
213 u32 physr; /* PHY Status */
214 u32 rxbistpd; /* Recvd BIST pattern def register */
215 u32 rxbistpd1; /* Recvd BIST data dword1 */
216 u32 rxbistpd2; /* Recvd BIST pattern data dword2 */
217 u32 txbistpd; /* Trans BIST pattern def register */
218 u32 txbistpd1; /* Trans BIST data dword1 */
219 u32 txbistpd2; /* Trans BIST data dword2 */
220 u32 bistcr; /* BIST Control Register */
221 u32 bistfctr; /* BIST FIS Count Register */
222 u32 bistsr; /* BIST Status Register */
223 u32 bistdecr; /* BIST Dword Error count register */
224 u32 res[15]; /* Reserved locations */
225 u32 testr; /* Test Register */
226 u32 versionr; /* Version Register */
227 u32 idr; /* ID Register */
228 u32 unimpl[192]; /* Unimplemented */
229 u32 dmadr[256]; /* FIFO Locations in DMA Mode */
230 };
231
232 enum {
233 SCR_SCONTROL_DET_ENABLE = 0x00000001,
234 SCR_SSTATUS_DET_PRESENT = 0x00000001,
235 SCR_SERROR_DIAG_X = 0x04000000,
236 /* DWC SATA Register Operations */
237 SATA_DWC_TXFIFO_DEPTH = 0x01FF,
238 SATA_DWC_RXFIFO_DEPTH = 0x01FF,
239 SATA_DWC_DMACR_TMOD_TXCHEN = 0x00000004,
240 SATA_DWC_DMACR_TXCHEN = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
241 SATA_DWC_DMACR_RXCHEN = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
242 SATA_DWC_DMACR_TXRXCH_CLEAR = SATA_DWC_DMACR_TMOD_TXCHEN,
243 SATA_DWC_INTPR_DMAT = 0x00000001,
244 SATA_DWC_INTPR_NEWFP = 0x00000002,
245 SATA_DWC_INTPR_PMABRT = 0x00000004,
246 SATA_DWC_INTPR_ERR = 0x00000008,
247 SATA_DWC_INTPR_NEWBIST = 0x00000010,
248 SATA_DWC_INTPR_IPF = 0x10000000,
249 SATA_DWC_INTMR_DMATM = 0x00000001,
250 SATA_DWC_INTMR_NEWFPM = 0x00000002,
251 SATA_DWC_INTMR_PMABRTM = 0x00000004,
252 SATA_DWC_INTMR_ERRM = 0x00000008,
253 SATA_DWC_INTMR_NEWBISTM = 0x00000010,
254 SATA_DWC_LLCR_SCRAMEN = 0x00000001,
255 SATA_DWC_LLCR_DESCRAMEN = 0x00000002,
256 SATA_DWC_LLCR_RPDEN = 0x00000004,
257 /* This is all error bits, zero's are reserved fields. */
258 SATA_DWC_SERROR_ERR_BITS = 0x0FFF0F03
259 };
260
261 #define SATA_DWC_SCR0_SPD_GET(v) (((v) >> 4) & 0x0000000F)
262 #define SATA_DWC_DMACR_TX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
263 SATA_DWC_DMACR_TMOD_TXCHEN)
264 #define SATA_DWC_DMACR_RX_CLEAR(v) (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
265 SATA_DWC_DMACR_TMOD_TXCHEN)
266 #define SATA_DWC_DBTSR_MWR(size) (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
267 #define SATA_DWC_DBTSR_MRD(size) ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
268 << 16)
269 struct sata_dwc_device {
270 struct device *dev; /* generic device struct */
271 struct ata_probe_ent *pe; /* ptr to probe-ent */
272 struct ata_host *host;
273 u8 *reg_base;
274 struct sata_dwc_regs *sata_dwc_regs; /* DW Synopsys SATA specific */
275 int irq_dma;
276 };
277
278 #define SATA_DWC_QCMD_MAX 32
279
280 struct sata_dwc_device_port {
281 struct sata_dwc_device *hsdev;
282 int cmd_issued[SATA_DWC_QCMD_MAX];
283 struct lli *llit[SATA_DWC_QCMD_MAX]; /* DMA LLI table */
284 dma_addr_t llit_dma[SATA_DWC_QCMD_MAX];
285 u32 dma_chan[SATA_DWC_QCMD_MAX];
286 int dma_pending[SATA_DWC_QCMD_MAX];
287 };
288
289 /*
290 * Commonly used DWC SATA driver Macros
291 */
292 #define HSDEV_FROM_HOST(host) ((struct sata_dwc_device *)\
293 (host)->private_data)
294 #define HSDEV_FROM_AP(ap) ((struct sata_dwc_device *)\
295 (ap)->host->private_data)
296 #define HSDEVP_FROM_AP(ap) ((struct sata_dwc_device_port *)\
297 (ap)->private_data)
298 #define HSDEV_FROM_QC(qc) ((struct sata_dwc_device *)\
299 (qc)->ap->host->private_data)
300 #define HSDEV_FROM_HSDEVP(p) ((struct sata_dwc_device *)\
301 (hsdevp)->hsdev)
302
303 enum {
304 SATA_DWC_CMD_ISSUED_NOT = 0,
305 SATA_DWC_CMD_ISSUED_PEND = 1,
306 SATA_DWC_CMD_ISSUED_EXEC = 2,
307 SATA_DWC_CMD_ISSUED_NODATA = 3,
308
309 SATA_DWC_DMA_PENDING_NONE = 0,
310 SATA_DWC_DMA_PENDING_TX = 1,
311 SATA_DWC_DMA_PENDING_RX = 2,
312 };
313
314 struct sata_dwc_host_priv {
315 void __iomem *scr_addr_sstatus;
316 u32 sata_dwc_sactive_issued ;
317 u32 sata_dwc_sactive_queued ;
318 u32 dma_interrupt_count;
319 struct ahb_dma_regs *sata_dma_regs;
320 struct device *dwc_dev;
321 };
322 struct sata_dwc_host_priv host_pvt;
323 /*
324 * Prototypes
325 */
326 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
327 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
328 u32 check_status);
329 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
330 static void sata_dwc_port_stop(struct ata_port *ap);
331 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
332 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
333 static void dma_dwc_exit(struct sata_dwc_device *hsdev);
334 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
335 struct lli *lli, dma_addr_t dma_lli,
336 void __iomem *addr, int dir);
337 static void dma_dwc_xfer_start(int dma_ch);
338
339 static const char *get_prot_descript(u8 protocol)
340 {
341 switch ((enum ata_tf_protocols)protocol) {
342 case ATA_PROT_NODATA:
343 return "ATA no data";
344 case ATA_PROT_PIO:
345 return "ATA PIO";
346 case ATA_PROT_DMA:
347 return "ATA DMA";
348 case ATA_PROT_NCQ:
349 return "ATA NCQ";
350 case ATAPI_PROT_NODATA:
351 return "ATAPI no data";
352 case ATAPI_PROT_PIO:
353 return "ATAPI PIO";
354 case ATAPI_PROT_DMA:
355 return "ATAPI DMA";
356 default:
357 return "unknown";
358 }
359 }
360
361 static const char *get_dma_dir_descript(int dma_dir)
362 {
363 switch ((enum dma_data_direction)dma_dir) {
364 case DMA_BIDIRECTIONAL:
365 return "bidirectional";
366 case DMA_TO_DEVICE:
367 return "to device";
368 case DMA_FROM_DEVICE:
369 return "from device";
370 default:
371 return "none";
372 }
373 }
374
375 static void sata_dwc_tf_dump(struct ata_taskfile *tf)
376 {
377 dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
378 "0x%lx device: %x\n", tf->command,
379 get_prot_descript(tf->protocol), tf->flags, tf->device);
380 dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
381 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
382 tf->lbam, tf->lbah);
383 dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
384 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
385 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
386 tf->hob_lbah);
387 }
388
389 /*
390 * Function: get_burst_length_encode
391 * arguments: datalength: length in bytes of data
392 * returns value to be programmed in register corresponding to data length
393 * This value is effectively the log(base 2) of the length
394 */
395 static int get_burst_length_encode(int datalength)
396 {
397 int items = datalength >> 2; /* div by 4 to get lword count */
398
399 if (items >= 64)
400 return 5;
401
402 if (items >= 32)
403 return 4;
404
405 if (items >= 16)
406 return 3;
407
408 if (items >= 8)
409 return 2;
410
411 if (items >= 4)
412 return 1;
413
414 return 0;
415 }
416
417 static void clear_chan_interrupts(int c)
418 {
419 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
420 DMA_CHANNEL(c));
421 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
422 DMA_CHANNEL(c));
423 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
424 DMA_CHANNEL(c));
425 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
426 DMA_CHANNEL(c));
427 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
428 DMA_CHANNEL(c));
429 }
430
431 /*
432 * Function: dma_request_channel
433 * arguments: None
434 * returns channel number if available else -1
435 * This function assigns the next available DMA channel from the list to the
436 * requester
437 */
438 static int dma_request_channel(void)
439 {
440 int i;
441
442 for (i = 0; i < DMA_NUM_CHANS; i++) {
443 if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &\
444 DMA_CHANNEL(i)))
445 return i;
446 }
447 dev_err(host_pvt.dwc_dev, "%s NO channel chan_en: 0x%08x\n", __func__,
448 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)));
449 return -1;
450 }
451
452 /*
453 * Function: dma_dwc_interrupt
454 * arguments: irq, dev_id, pt_regs
455 * returns channel number if available else -1
456 * Interrupt Handler for DW AHB SATA DMA
457 */
458 static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
459 {
460 int chan;
461 u32 tfr_reg, err_reg;
462 unsigned long flags;
463 struct sata_dwc_device *hsdev =
464 (struct sata_dwc_device *)hsdev_instance;
465 struct ata_host *host = (struct ata_host *)hsdev->host;
466 struct ata_port *ap;
467 struct sata_dwc_device_port *hsdevp;
468 u8 tag = 0;
469 unsigned int port = 0;
470
471 spin_lock_irqsave(&host->lock, flags);
472 ap = host->ports[port];
473 hsdevp = HSDEVP_FROM_AP(ap);
474 tag = ap->link.active_tag;
475
476 tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
477 .low));
478 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
479 .low));
480
481 dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
482 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
483
484 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
485 /* Check for end-of-transfer interrupt. */
486 if (tfr_reg & DMA_CHANNEL(chan)) {
487 /*
488 * Each DMA command produces 2 interrupts. Only
489 * complete the command after both interrupts have been
490 * seen. (See sata_dwc_isr())
491 */
492 host_pvt.dma_interrupt_count++;
493 sata_dwc_clear_dmacr(hsdevp, tag);
494
495 if (hsdevp->dma_pending[tag] ==
496 SATA_DWC_DMA_PENDING_NONE) {
497 dev_err(ap->dev, "DMA not pending eot=0x%08x "
498 "err=0x%08x tag=0x%02x pending=%d\n",
499 tfr_reg, err_reg, tag,
500 hsdevp->dma_pending[tag]);
501 }
502
503 if ((host_pvt.dma_interrupt_count % 2) == 0)
504 sata_dwc_dma_xfer_complete(ap, 1);
505
506 /* Clear the interrupt */
507 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
508 .tfr.low),
509 DMA_CHANNEL(chan));
510 }
511
512 /* Check for error interrupt. */
513 if (err_reg & DMA_CHANNEL(chan)) {
514 /* TODO Need error handler ! */
515 dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
516 err_reg);
517
518 /* Clear the interrupt. */
519 out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
520 .error.low),
521 DMA_CHANNEL(chan));
522 }
523 }
524 spin_unlock_irqrestore(&host->lock, flags);
525 return IRQ_HANDLED;
526 }
527
528 /*
529 * Function: dma_request_interrupts
530 * arguments: hsdev
531 * returns status
532 * This function registers ISR for a particular DMA channel interrupt
533 */
534 static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
535 {
536 int retval = 0;
537 int chan;
538
539 for (chan = 0; chan < DMA_NUM_CHANS; chan++) {
540 /* Unmask error interrupt */
541 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
542 DMA_ENABLE_CHAN(chan));
543
544 /* Unmask end-of-transfer interrupt */
545 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
546 DMA_ENABLE_CHAN(chan));
547 }
548
549 retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
550 if (retval) {
551 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
552 __func__, irq);
553 return -ENODEV;
554 }
555
556 /* Mark this interrupt as requested */
557 hsdev->irq_dma = irq;
558 return 0;
559 }
560
561 /*
562 * Function: map_sg_to_lli
563 * The Synopsis driver has a comment proposing that better performance
564 * is possible by only enabling interrupts on the last item in the linked list.
565 * However, it seems that could be a problem if an error happened on one of the
566 * first items. The transfer would halt, but no error interrupt would occur.
567 * Currently this function sets interrupts enabled for each linked list item:
568 * DMA_CTL_INT_EN.
569 */
570 static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
571 struct lli *lli, dma_addr_t dma_lli,
572 void __iomem *dmadr_addr, int dir)
573 {
574 int i, idx = 0;
575 int fis_len = 0;
576 dma_addr_t next_llp;
577 int bl;
578
579 dev_dbg(host_pvt.dwc_dev, "%s: sg=%p nelem=%d lli=%p dma_lli=0x%08x"
580 " dmadr=0x%08x\n", __func__, sg, num_elems, lli, (u32)dma_lli,
581 (u32)dmadr_addr);
582
583 bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
584
585 for (i = 0; i < num_elems; i++, sg++) {
586 u32 addr, offset;
587 u32 sg_len, len;
588
589 addr = (u32) sg_dma_address(sg);
590 sg_len = sg_dma_len(sg);
591
592 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
593 "=%d\n", __func__, i, addr, sg_len);
594
595 while (sg_len) {
596 if (idx >= SATA_DWC_DMAC_LLI_NUM) {
597 /* The LLI table is not large enough. */
598 dev_err(host_pvt.dwc_dev, "LLI table overrun "
599 "(idx=%d)\n", idx);
600 break;
601 }
602 len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
603 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
604
605 offset = addr & 0xffff;
606 if ((offset + sg_len) > 0x10000)
607 len = 0x10000 - offset;
608
609 /*
610 * Make sure a LLI block is not created that will span
611 * 8K max FIS boundary. If the block spans such a FIS
612 * boundary, there is a chance that a DMA burst will
613 * cross that boundary -- this results in an error in
614 * the host controller.
615 */
616 if (fis_len + len > 8192) {
617 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
618 "%d(0x%x) len=%d(0x%x)\n", fis_len,
619 fis_len, len, len);
620 len = 8192 - fis_len;
621 fis_len = 0;
622 } else {
623 fis_len += len;
624 }
625 if (fis_len == 8192)
626 fis_len = 0;
627
628 /*
629 * Set DMA addresses and lower half of control register
630 * based on direction.
631 */
632 if (dir == DMA_FROM_DEVICE) {
633 lli[idx].dar = cpu_to_le32(addr);
634 lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
635
636 lli[idx].ctl.low = cpu_to_le32(
637 DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
638 DMA_CTL_SMS(0) |
639 DMA_CTL_DMS(1) |
640 DMA_CTL_SRC_MSIZE(bl) |
641 DMA_CTL_DST_MSIZE(bl) |
642 DMA_CTL_SINC_NOCHANGE |
643 DMA_CTL_SRC_TRWID(2) |
644 DMA_CTL_DST_TRWID(2) |
645 DMA_CTL_INT_EN |
646 DMA_CTL_LLP_SRCEN |
647 DMA_CTL_LLP_DSTEN);
648 } else { /* DMA_TO_DEVICE */
649 lli[idx].sar = cpu_to_le32(addr);
650 lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
651
652 lli[idx].ctl.low = cpu_to_le32(
653 DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
654 DMA_CTL_SMS(1) |
655 DMA_CTL_DMS(0) |
656 DMA_CTL_SRC_MSIZE(bl) |
657 DMA_CTL_DST_MSIZE(bl) |
658 DMA_CTL_DINC_NOCHANGE |
659 DMA_CTL_SRC_TRWID(2) |
660 DMA_CTL_DST_TRWID(2) |
661 DMA_CTL_INT_EN |
662 DMA_CTL_LLP_SRCEN |
663 DMA_CTL_LLP_DSTEN);
664 }
665
666 dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
667 "0x%08x val: 0x%08x\n", __func__,
668 len, DMA_CTL_BLK_TS(len / 4));
669
670 /* Program the LLI CTL high register */
671 lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
672 (len / 4));
673
674 /* Program the next pointer. The next pointer must be
675 * the physical address, not the virtual address.
676 */
677 next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
678 lli)));
679
680 /* The last 2 bits encode the list master select. */
681 next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
682
683 lli[idx].llp = cpu_to_le32(next_llp);
684 idx++;
685 sg_len -= len;
686 addr += len;
687 }
688 }
689
690 /*
691 * The last next ptr has to be zero and the last control low register
692 * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
693 * and destination enable) set back to 0 (disabled.) This is what tells
694 * the core that this is the last item in the linked list.
695 */
696 if (idx) {
697 lli[idx-1].llp = 0x00000000;
698 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
699
700 /* Flush cache to memory */
701 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
702 DMA_BIDIRECTIONAL);
703 }
704
705 return idx;
706 }
707
708 /*
709 * Function: dma_dwc_xfer_start
710 * arguments: Channel number
711 * Return : None
712 * Enables the DMA channel
713 */
714 static void dma_dwc_xfer_start(int dma_ch)
715 {
716 /* Enable the DMA channel */
717 out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
718 in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
719 DMA_ENABLE_CHAN(dma_ch));
720 }
721
722 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
723 struct lli *lli, dma_addr_t dma_lli,
724 void __iomem *addr, int dir)
725 {
726 int dma_ch;
727 int num_lli;
728 /* Acquire DMA channel */
729 dma_ch = dma_request_channel();
730 if (dma_ch == -1) {
731 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
732 __func__);
733 return -EAGAIN;
734 }
735
736 /* Convert SG list to linked list of items (LLIs) for AHB DMA */
737 num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
738
739 dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
740 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
741 lli, (u32)dma_lli, addr, num_lli);
742
743 clear_chan_interrupts(dma_ch);
744
745 /* Program the CFG register. */
746 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
747 DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
748 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low), 0);
749
750 /* Program the address of the linked list */
751 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
752 DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
753
754 /* Program the CTL register with src enable / dst enable */
755 out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
756 DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
757 return dma_ch;
758 }
759
760 /*
761 * Function: dma_dwc_exit
762 * arguments: None
763 * returns status
764 * This function exits the SATA DMA driver
765 */
766 static void dma_dwc_exit(struct sata_dwc_device *hsdev)
767 {
768 dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
769 if (host_pvt.sata_dma_regs)
770 iounmap(host_pvt.sata_dma_regs);
771
772 if (hsdev->irq_dma)
773 free_irq(hsdev->irq_dma, hsdev);
774 }
775
776 /*
777 * Function: dma_dwc_init
778 * arguments: hsdev
779 * returns status
780 * This function initializes the SATA DMA driver
781 */
782 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
783 {
784 int err;
785
786 err = dma_request_interrupts(hsdev, irq);
787 if (err) {
788 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
789 " %d\n", __func__, err);
790 goto error_out;
791 }
792
793 /* Enabe DMA */
794 out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
795
796 dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
797 dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
798 sata_dma_regs);
799
800 return 0;
801
802 error_out:
803 dma_dwc_exit(hsdev);
804
805 return err;
806 }
807
808 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
809 {
810 if (scr > SCR_NOTIFICATION) {
811 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
812 __func__, scr);
813 return -EINVAL;
814 }
815
816 *val = in_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4));
817 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
818 __func__, link->ap->print_id, scr, *val);
819
820 return 0;
821 }
822
823 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
824 {
825 dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
826 __func__, link->ap->print_id, scr, val);
827 if (scr > SCR_NOTIFICATION) {
828 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
829 __func__, scr);
830 return -EINVAL;
831 }
832 out_le32((void *)link->ap->ioaddr.scr_addr + (scr * 4), val);
833
834 return 0;
835 }
836
837 static u32 core_scr_read(unsigned int scr)
838 {
839 return in_le32((void __iomem *)(host_pvt.scr_addr_sstatus) +\
840 (scr * 4));
841 }
842
843 static void core_scr_write(unsigned int scr, u32 val)
844 {
845 out_le32((void __iomem *)(host_pvt.scr_addr_sstatus) + (scr * 4),
846 val);
847 }
848
849 static void clear_serror(void)
850 {
851 u32 val;
852 val = core_scr_read(SCR_ERROR);
853 core_scr_write(SCR_ERROR, val);
854
855 }
856
857 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
858 {
859 out_le32(&hsdev->sata_dwc_regs->intpr,
860 in_le32(&hsdev->sata_dwc_regs->intpr));
861 }
862
863 static u32 qcmd_tag_to_mask(u8 tag)
864 {
865 return 0x00000001 << (tag & 0x1f);
866 }
867
868 /* See ahci.c */
869 static void sata_dwc_error_intr(struct ata_port *ap,
870 struct sata_dwc_device *hsdev, uint intpr)
871 {
872 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
873 struct ata_eh_info *ehi = &ap->link.eh_info;
874 unsigned int err_mask = 0, action = 0;
875 struct ata_queued_cmd *qc;
876 u32 serror;
877 u8 status, tag;
878 u32 err_reg;
879
880 ata_ehi_clear_desc(ehi);
881
882 serror = core_scr_read(SCR_ERROR);
883 status = ap->ops->sff_check_status(ap);
884
885 err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
886 low));
887 tag = ap->link.active_tag;
888
889 dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
890 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
891 __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
892 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
893
894 /* Clear error register and interrupt bit */
895 clear_serror();
896 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
897
898 /* This is the only error happening now. TODO check for exact error */
899
900 err_mask |= AC_ERR_HOST_BUS;
901 action |= ATA_EH_RESET;
902
903 /* Pass this on to EH */
904 ehi->serror |= serror;
905 ehi->action |= action;
906
907 qc = ata_qc_from_tag(ap, tag);
908 if (qc)
909 qc->err_mask |= err_mask;
910 else
911 ehi->err_mask |= err_mask;
912
913 ata_port_abort(ap);
914 }
915
916 /*
917 * Function : sata_dwc_isr
918 * arguments : irq, void *dev_instance, struct pt_regs *regs
919 * Return value : irqreturn_t - status of IRQ
920 * This Interrupt handler called via port ops registered function.
921 * .irq_handler = sata_dwc_isr
922 */
923 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
924 {
925 struct ata_host *host = (struct ata_host *)dev_instance;
926 struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
927 struct ata_port *ap;
928 struct ata_queued_cmd *qc;
929 unsigned long flags;
930 u8 status, tag;
931 int handled, num_processed, port = 0;
932 uint intpr, sactive, sactive2, tag_mask;
933 struct sata_dwc_device_port *hsdevp;
934 host_pvt.sata_dwc_sactive_issued = 0;
935
936 spin_lock_irqsave(&host->lock, flags);
937
938 /* Read the interrupt register */
939 intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
940
941 ap = host->ports[port];
942 hsdevp = HSDEVP_FROM_AP(ap);
943
944 dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
945 ap->link.active_tag);
946
947 /* Check for error interrupt */
948 if (intpr & SATA_DWC_INTPR_ERR) {
949 sata_dwc_error_intr(ap, hsdev, intpr);
950 handled = 1;
951 goto DONE;
952 }
953
954 /* Check for DMA SETUP FIS (FP DMA) interrupt */
955 if (intpr & SATA_DWC_INTPR_NEWFP) {
956 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
957
958 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
959 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
960 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
961 dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
962
963 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
964
965 qc = ata_qc_from_tag(ap, tag);
966 /*
967 * Start FP DMA for NCQ command. At this point the tag is the
968 * active tag. It is the tag that matches the command about to
969 * be completed.
970 */
971 qc->ap->link.active_tag = tag;
972 sata_dwc_bmdma_start_by_tag(qc, tag);
973
974 handled = 1;
975 goto DONE;
976 }
977 sactive = core_scr_read(SCR_ACTIVE);
978 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
979
980 /* If no sactive issued and tag_mask is zero then this is not NCQ */
981 if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
982 if (ap->link.active_tag == ATA_TAG_POISON)
983 tag = 0;
984 else
985 tag = ap->link.active_tag;
986 qc = ata_qc_from_tag(ap, tag);
987
988 /* DEV interrupt w/ no active qc? */
989 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
990 dev_err(ap->dev, "%s interrupt with no active qc "
991 "qc=%p\n", __func__, qc);
992 ap->ops->sff_check_status(ap);
993 handled = 1;
994 goto DONE;
995 }
996 status = ap->ops->sff_check_status(ap);
997
998 qc->ap->link.active_tag = tag;
999 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1000
1001 if (status & ATA_ERR) {
1002 dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
1003 sata_dwc_qc_complete(ap, qc, 1);
1004 handled = 1;
1005 goto DONE;
1006 }
1007
1008 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
1009 __func__, get_prot_descript(qc->tf.protocol));
1010 DRVSTILLBUSY:
1011 if (ata_is_dma(qc->tf.protocol)) {
1012 /*
1013 * Each DMA transaction produces 2 interrupts. The DMAC
1014 * transfer complete interrupt and the SATA controller
1015 * operation done interrupt. The command should be
1016 * completed only after both interrupts are seen.
1017 */
1018 host_pvt.dma_interrupt_count++;
1019 if (hsdevp->dma_pending[tag] == \
1020 SATA_DWC_DMA_PENDING_NONE) {
1021 dev_err(ap->dev, "%s: DMA not pending "
1022 "intpr=0x%08x status=0x%08x pending"
1023 "=%d\n", __func__, intpr, status,
1024 hsdevp->dma_pending[tag]);
1025 }
1026
1027 if ((host_pvt.dma_interrupt_count % 2) == 0)
1028 sata_dwc_dma_xfer_complete(ap, 1);
1029 } else if (ata_is_pio(qc->tf.protocol)) {
1030 ata_sff_hsm_move(ap, qc, status, 0);
1031 handled = 1;
1032 goto DONE;
1033 } else {
1034 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1035 goto DRVSTILLBUSY;
1036 }
1037
1038 handled = 1;
1039 goto DONE;
1040 }
1041
1042 /*
1043 * This is a NCQ command. At this point we need to figure out for which
1044 * tags we have gotten a completion interrupt. One interrupt may serve
1045 * as completion for more than one operation when commands are queued
1046 * (NCQ). We need to process each completed command.
1047 */
1048
1049 /* process completed commands */
1050 sactive = core_scr_read(SCR_ACTIVE);
1051 tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1052
1053 if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1054 tag_mask > 1) {
1055 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x sactive_issued=0x%08x"
1056 "tag_mask=0x%08x\n", __func__, sactive,
1057 host_pvt.sata_dwc_sactive_issued, tag_mask);
1058 }
1059
1060 if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1061 (host_pvt.sata_dwc_sactive_issued)) {
1062 dev_warn(ap->dev, "Bad tag mask? sactive=0x%08x "
1063 "(host_pvt.sata_dwc_sactive_issued)=0x%08x tag_mask"
1064 "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1065 tag_mask);
1066 }
1067
1068 /* read just to clear ... not bad if currently still busy */
1069 status = ap->ops->sff_check_status(ap);
1070 dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1071
1072 tag = 0;
1073 num_processed = 0;
1074 while (tag_mask) {
1075 num_processed++;
1076 while (!(tag_mask & 0x00000001)) {
1077 tag++;
1078 tag_mask <<= 1;
1079 }
1080
1081 tag_mask &= (~0x00000001);
1082 qc = ata_qc_from_tag(ap, tag);
1083
1084 /* To be picked up by completion functions */
1085 qc->ap->link.active_tag = tag;
1086 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1087
1088 /* Let libata/scsi layers handle error */
1089 if (status & ATA_ERR) {
1090 dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1091 status);
1092 sata_dwc_qc_complete(ap, qc, 1);
1093 handled = 1;
1094 goto DONE;
1095 }
1096
1097 /* Process completed command */
1098 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
1099 get_prot_descript(qc->tf.protocol));
1100 if (ata_is_dma(qc->tf.protocol)) {
1101 host_pvt.dma_interrupt_count++;
1102 if (hsdevp->dma_pending[tag] == \
1103 SATA_DWC_DMA_PENDING_NONE)
1104 dev_warn(ap->dev, "%s: DMA not pending?\n",
1105 __func__);
1106 if ((host_pvt.dma_interrupt_count % 2) == 0)
1107 sata_dwc_dma_xfer_complete(ap, 1);
1108 } else {
1109 if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1110 goto STILLBUSY;
1111 }
1112 continue;
1113
1114 STILLBUSY:
1115 ap->stats.idle_irq++;
1116 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1117 ap->print_id);
1118 } /* while tag_mask */
1119
1120 /*
1121 * Check to see if any commands completed while we were processing our
1122 * initial set of completed commands (read status clears interrupts,
1123 * so we might miss a completed command interrupt if one came in while
1124 * we were processing --we read status as part of processing a completed
1125 * command).
1126 */
1127 sactive2 = core_scr_read(SCR_ACTIVE);
1128 if (sactive2 != sactive) {
1129 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1130 "=0x%x\n", sactive, sactive2);
1131 }
1132 handled = 1;
1133
1134 DONE:
1135 spin_unlock_irqrestore(&host->lock, flags);
1136 return IRQ_RETVAL(handled);
1137 }
1138
1139 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1140 {
1141 struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1142
1143 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1144 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1145 SATA_DWC_DMACR_RX_CLEAR(
1146 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1147 } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1148 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1149 SATA_DWC_DMACR_TX_CLEAR(
1150 in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1151 } else {
1152 /*
1153 * This should not happen, it indicates the driver is out of
1154 * sync. If it does happen, clear dmacr anyway.
1155 */
1156 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1157 "TX DMA not pending tag=0x%02x pending=%d"
1158 " dmacr: 0x%08x\n", __func__, tag,
1159 hsdevp->dma_pending[tag],
1160 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1161 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1162 SATA_DWC_DMACR_TXRXCH_CLEAR);
1163 }
1164 }
1165
1166 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1167 {
1168 struct ata_queued_cmd *qc;
1169 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1170 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1171 u8 tag = 0;
1172
1173 tag = ap->link.active_tag;
1174 qc = ata_qc_from_tag(ap, tag);
1175 if (!qc) {
1176 dev_err(ap->dev, "failed to get qc");
1177 return;
1178 }
1179
1180 #ifdef DEBUG_NCQ
1181 if (tag > 0) {
1182 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1183 "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
1184 get_dma_dir_descript(qc->dma_dir),
1185 get_prot_descript(qc->tf.protocol),
1186 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1187 }
1188 #endif
1189
1190 if (ata_is_dma(qc->tf.protocol)) {
1191 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1192 dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1193 "pending dmacr: 0x%08x\n", __func__,
1194 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1195 }
1196
1197 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1198 sata_dwc_qc_complete(ap, qc, check_status);
1199 ap->link.active_tag = ATA_TAG_POISON;
1200 } else {
1201 sata_dwc_qc_complete(ap, qc, check_status);
1202 }
1203 }
1204
1205 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1206 u32 check_status)
1207 {
1208 u8 status = 0;
1209 u32 mask = 0x0;
1210 u8 tag = qc->tag;
1211 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1212 host_pvt.sata_dwc_sactive_queued = 0;
1213 dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1214
1215 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1216 dev_err(ap->dev, "TX DMA PENDING\n");
1217 else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1218 dev_err(ap->dev, "RX DMA PENDING\n");
1219 dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1220 " protocol=%d\n", qc->tf.command, status, ap->print_id,
1221 qc->tf.protocol);
1222
1223 /* clear active bit */
1224 mask = (~(qcmd_tag_to_mask(tag)));
1225 host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1226 & mask;
1227 host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1228 & mask;
1229 ata_qc_complete(qc);
1230 return 0;
1231 }
1232
1233 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1234 {
1235 /* Enable selective interrupts by setting the interrupt maskregister*/
1236 out_le32(&hsdev->sata_dwc_regs->intmr,
1237 SATA_DWC_INTMR_ERRM |
1238 SATA_DWC_INTMR_NEWFPM |
1239 SATA_DWC_INTMR_PMABRTM |
1240 SATA_DWC_INTMR_DMATM);
1241 /*
1242 * Unmask the error bits that should trigger an error interrupt by
1243 * setting the error mask register.
1244 */
1245 out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1246
1247 dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1248 __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1249 in_le32(&hsdev->sata_dwc_regs->errmr));
1250 }
1251
1252 static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1253 {
1254 port->cmd_addr = (void *)base + 0x00;
1255 port->data_addr = (void *)base + 0x00;
1256
1257 port->error_addr = (void *)base + 0x04;
1258 port->feature_addr = (void *)base + 0x04;
1259
1260 port->nsect_addr = (void *)base + 0x08;
1261
1262 port->lbal_addr = (void *)base + 0x0c;
1263 port->lbam_addr = (void *)base + 0x10;
1264 port->lbah_addr = (void *)base + 0x14;
1265
1266 port->device_addr = (void *)base + 0x18;
1267 port->command_addr = (void *)base + 0x1c;
1268 port->status_addr = (void *)base + 0x1c;
1269
1270 port->altstatus_addr = (void *)base + 0x20;
1271 port->ctl_addr = (void *)base + 0x20;
1272 }
1273
1274 /*
1275 * Function : sata_dwc_port_start
1276 * arguments : struct ata_ioports *port
1277 * Return value : returns 0 if success, error code otherwise
1278 * This function allocates the scatter gather LLI table for AHB DMA
1279 */
1280 static int sata_dwc_port_start(struct ata_port *ap)
1281 {
1282 int err = 0;
1283 struct sata_dwc_device *hsdev;
1284 struct sata_dwc_device_port *hsdevp = NULL;
1285 struct device *pdev;
1286 int i;
1287
1288 hsdev = HSDEV_FROM_AP(ap);
1289
1290 dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1291
1292 hsdev->host = ap->host;
1293 pdev = ap->host->dev;
1294 if (!pdev) {
1295 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1296 err = -ENODEV;
1297 goto CLEANUP;
1298 }
1299
1300 /* Allocate Port Struct */
1301 hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1302 if (!hsdevp) {
1303 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1304 err = -ENOMEM;
1305 goto CLEANUP;
1306 }
1307 hsdevp->hsdev = hsdev;
1308
1309 for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1310 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1311
1312 ap->bmdma_prd = 0; /* set these so libata doesn't use them */
1313 ap->bmdma_prd_dma = 0;
1314
1315 /*
1316 * DMA - Assign scatter gather LLI table. We can't use the libata
1317 * version since it's PRD is IDE PCI specific.
1318 */
1319 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1320 hsdevp->llit[i] = dma_alloc_coherent(pdev,
1321 SATA_DWC_DMAC_LLI_TBL_SZ,
1322 &(hsdevp->llit_dma[i]),
1323 GFP_ATOMIC);
1324 if (!hsdevp->llit[i]) {
1325 dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1326 __func__);
1327 err = -ENOMEM;
1328 goto CLEANUP;
1329 }
1330 }
1331
1332 if (ap->port_no == 0) {
1333 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1334 __func__);
1335 out_le32(&hsdev->sata_dwc_regs->dmacr,
1336 SATA_DWC_DMACR_TXRXCH_CLEAR);
1337
1338 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1339 __func__);
1340 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1341 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1342 SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1343 }
1344
1345 /* Clear any error bits before libata starts issuing commands */
1346 clear_serror();
1347 ap->private_data = hsdevp;
1348
1349 CLEANUP:
1350 if (err) {
1351 sata_dwc_port_stop(ap);
1352 dev_dbg(ap->dev, "%s: fail\n", __func__);
1353 } else {
1354 dev_dbg(ap->dev, "%s: done\n", __func__);
1355 }
1356
1357 return err;
1358 }
1359
1360 static void sata_dwc_port_stop(struct ata_port *ap)
1361 {
1362 int i;
1363 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1364 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1365
1366 dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1367
1368 if (hsdevp && hsdev) {
1369 /* deallocate LLI table */
1370 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1371 dma_free_coherent(ap->host->dev,
1372 SATA_DWC_DMAC_LLI_TBL_SZ,
1373 hsdevp->llit[i], hsdevp->llit_dma[i]);
1374 }
1375
1376 kfree(hsdevp);
1377 }
1378 ap->private_data = NULL;
1379 }
1380
1381 /*
1382 * Function : sata_dwc_exec_command_by_tag
1383 * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1384 * Return value : None
1385 * This function keeps track of individual command tag ids and calls
1386 * ata_exec_command in libata
1387 */
1388 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1389 struct ata_taskfile *tf,
1390 u8 tag, u32 cmd_issued)
1391 {
1392 unsigned long flags;
1393 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1394
1395 dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
1396 ata_get_cmd_descript(tf->command), tag);
1397
1398 spin_lock_irqsave(&ap->host->lock, flags);
1399 hsdevp->cmd_issued[tag] = cmd_issued;
1400 spin_unlock_irqrestore(&ap->host->lock, flags);
1401 /*
1402 * Clear SError before executing a new command.
1403 * sata_dwc_scr_write and read can not be used here. Clearing the PM
1404 * managed SError register for the disk needs to be done before the
1405 * task file is loaded.
1406 */
1407 clear_serror();
1408 ata_sff_exec_command(ap, tf);
1409 }
1410
1411 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1412 {
1413 sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1414 SATA_DWC_CMD_ISSUED_PEND);
1415 }
1416
1417 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1418 {
1419 u8 tag = qc->tag;
1420
1421 if (ata_is_ncq(qc->tf.protocol)) {
1422 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1423 __func__, qc->ap->link.sactive, tag);
1424 } else {
1425 tag = 0;
1426 }
1427 sata_dwc_bmdma_setup_by_tag(qc, tag);
1428 }
1429
1430 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1431 {
1432 int start_dma;
1433 u32 reg, dma_chan;
1434 struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1435 struct ata_port *ap = qc->ap;
1436 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1437 int dir = qc->dma_dir;
1438 dma_chan = hsdevp->dma_chan[tag];
1439
1440 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1441 start_dma = 1;
1442 if (dir == DMA_TO_DEVICE)
1443 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1444 else
1445 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1446 } else {
1447 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1448 "(tag=%d) DMA NOT started\n", __func__,
1449 hsdevp->cmd_issued[tag], tag);
1450 start_dma = 0;
1451 }
1452
1453 dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1454 "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
1455 get_dma_dir_descript(qc->dma_dir), start_dma);
1456 sata_dwc_tf_dump(&(qc->tf));
1457
1458 if (start_dma) {
1459 reg = core_scr_read(SCR_ERROR);
1460 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1461 dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1462 __func__, reg);
1463 }
1464
1465 if (dir == DMA_TO_DEVICE)
1466 out_le32(&hsdev->sata_dwc_regs->dmacr,
1467 SATA_DWC_DMACR_TXCHEN);
1468 else
1469 out_le32(&hsdev->sata_dwc_regs->dmacr,
1470 SATA_DWC_DMACR_RXCHEN);
1471
1472 /* Enable AHB DMA transfer on the specified channel */
1473 dma_dwc_xfer_start(dma_chan);
1474 }
1475 }
1476
1477 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1478 {
1479 u8 tag = qc->tag;
1480
1481 if (ata_is_ncq(qc->tf.protocol)) {
1482 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1483 __func__, qc->ap->link.sactive, tag);
1484 } else {
1485 tag = 0;
1486 }
1487 dev_dbg(qc->ap->dev, "%s\n", __func__);
1488 sata_dwc_bmdma_start_by_tag(qc, tag);
1489 }
1490
1491 /*
1492 * Function : sata_dwc_qc_prep_by_tag
1493 * arguments : ata_queued_cmd *qc, u8 tag
1494 * Return value : None
1495 * qc_prep for a particular queued command based on tag
1496 */
1497 static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1498 {
1499 struct scatterlist *sg = qc->sg;
1500 struct ata_port *ap = qc->ap;
1501 int dma_chan;
1502 struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1503 struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1504
1505 dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
1506 __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
1507 qc->n_elem);
1508
1509 dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1510 hsdevp->llit_dma[tag],
1511 (void *__iomem)(&hsdev->sata_dwc_regs->\
1512 dmadr), qc->dma_dir);
1513 if (dma_chan < 0) {
1514 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
1515 __func__, dma_chan);
1516 return;
1517 }
1518 hsdevp->dma_chan[tag] = dma_chan;
1519 }
1520
1521 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1522 {
1523 u32 sactive;
1524 u8 tag = qc->tag;
1525 struct ata_port *ap = qc->ap;
1526
1527 #ifdef DEBUG_NCQ
1528 if (qc->tag > 0 || ap->link.sactive > 1)
1529 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1530 "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1531 __func__, ap->print_id, qc->tf.command,
1532 ata_get_cmd_descript(qc->tf.command),
1533 qc->tag, get_prot_descript(qc->tf.protocol),
1534 ap->link.active_tag, ap->link.sactive);
1535 #endif
1536
1537 if (!ata_is_ncq(qc->tf.protocol))
1538 tag = 0;
1539 sata_dwc_qc_prep_by_tag(qc, tag);
1540
1541 if (ata_is_ncq(qc->tf.protocol)) {
1542 sactive = core_scr_read(SCR_ACTIVE);
1543 sactive |= (0x00000001 << tag);
1544 core_scr_write(SCR_ACTIVE, sactive);
1545
1546 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1547 "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1548 sactive);
1549
1550 ap->ops->sff_tf_load(ap, &qc->tf);
1551 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1552 SATA_DWC_CMD_ISSUED_PEND);
1553 } else {
1554 ata_sff_qc_issue(qc);
1555 }
1556 return 0;
1557 }
1558
1559 /*
1560 * Function : sata_dwc_qc_prep
1561 * arguments : ata_queued_cmd *qc
1562 * Return value : None
1563 * qc_prep for a particular queued command
1564 */
1565
1566 static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1567 {
1568 if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1569 return;
1570
1571 #ifdef DEBUG_NCQ
1572 if (qc->tag > 0)
1573 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
1574 __func__, qc->tag, qc->ap->link.active_tag);
1575
1576 return ;
1577 #endif
1578 }
1579
1580 static void sata_dwc_error_handler(struct ata_port *ap)
1581 {
1582 ap->link.flags |= ATA_LFLAG_NO_HRST;
1583 ata_sff_error_handler(ap);
1584 }
1585
1586 /*
1587 * scsi mid-layer and libata interface structures
1588 */
1589 static struct scsi_host_template sata_dwc_sht = {
1590 ATA_NCQ_SHT(DRV_NAME),
1591 /*
1592 * test-only: Currently this driver doesn't handle NCQ
1593 * correctly. We enable NCQ but set the queue depth to a
1594 * max of 1. This will get fixed in in a future release.
1595 */
1596 .sg_tablesize = LIBATA_MAX_PRD,
1597 .can_queue = ATA_DEF_QUEUE, /* ATA_MAX_QUEUE */
1598 .dma_boundary = ATA_DMA_BOUNDARY,
1599 };
1600
1601 static struct ata_port_operations sata_dwc_ops = {
1602 .inherits = &ata_sff_port_ops,
1603
1604 .error_handler = sata_dwc_error_handler,
1605
1606 .qc_prep = sata_dwc_qc_prep,
1607 .qc_issue = sata_dwc_qc_issue,
1608
1609 .scr_read = sata_dwc_scr_read,
1610 .scr_write = sata_dwc_scr_write,
1611
1612 .port_start = sata_dwc_port_start,
1613 .port_stop = sata_dwc_port_stop,
1614
1615 .bmdma_setup = sata_dwc_bmdma_setup,
1616 .bmdma_start = sata_dwc_bmdma_start,
1617 };
1618
1619 static const struct ata_port_info sata_dwc_port_info[] = {
1620 {
1621 .flags = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1622 .pio_mask = ATA_PIO4,
1623 .udma_mask = ATA_UDMA6,
1624 .port_ops = &sata_dwc_ops,
1625 },
1626 };
1627
1628 static int sata_dwc_probe(struct platform_device *ofdev)
1629 {
1630 struct sata_dwc_device *hsdev;
1631 u32 idr, versionr;
1632 char *ver = (char *)&versionr;
1633 u8 *base = NULL;
1634 int err = 0;
1635 int irq, rc;
1636 struct ata_host *host;
1637 struct ata_port_info pi = sata_dwc_port_info[0];
1638 const struct ata_port_info *ppi[] = { &pi, NULL };
1639
1640 /* Allocate DWC SATA device */
1641 hsdev = kmalloc(sizeof(*hsdev), GFP_KERNEL);
1642 if (hsdev == NULL) {
1643 dev_err(&ofdev->dev, "kmalloc failed for hsdev\n");
1644 err = -ENOMEM;
1645 goto error_out;
1646 }
1647 memset(hsdev, 0, sizeof(*hsdev));
1648
1649 /* Ioremap SATA registers */
1650 base = of_iomap(ofdev->dev.of_node, 0);
1651 if (!base) {
1652 dev_err(&ofdev->dev, "ioremap failed for SATA register"
1653 " address\n");
1654 err = -ENODEV;
1655 goto error_out;
1656 }
1657 hsdev->reg_base = base;
1658 dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1659
1660 /* Synopsys DWC SATA specific Registers */
1661 hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1662
1663 /* Allocate and fill host */
1664 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1665 if (!host) {
1666 dev_err(&ofdev->dev, "ata_host_alloc_pinfo failed\n");
1667 err = -ENOMEM;
1668 goto error_out;
1669 }
1670
1671 host->private_data = hsdev;
1672
1673 /* Setup port */
1674 host->ports[0]->ioaddr.cmd_addr = base;
1675 host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1676 host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1677 sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1678
1679 /* Read the ID and Version Registers */
1680 idr = in_le32(&hsdev->sata_dwc_regs->idr);
1681 versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1682 dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1683 idr, ver[0], ver[1], ver[2]);
1684
1685 /* Get SATA DMA interrupt number */
1686 irq = irq_of_parse_and_map(ofdev->dev.of_node, 1);
1687 if (irq == NO_IRQ) {
1688 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1689 err = -ENODEV;
1690 goto error_out;
1691 }
1692
1693 /* Get physical SATA DMA register base address */
1694 host_pvt.sata_dma_regs = of_iomap(ofdev->dev.of_node, 1);
1695 if (!(host_pvt.sata_dma_regs)) {
1696 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1697 " address\n");
1698 err = -ENODEV;
1699 goto error_out;
1700 }
1701
1702 /* Save dev for later use in dev_xxx() routines */
1703 host_pvt.dwc_dev = &ofdev->dev;
1704
1705 /* Initialize AHB DMAC */
1706 dma_dwc_init(hsdev, irq);
1707
1708 /* Enable SATA Interrupts */
1709 sata_dwc_enable_interrupts(hsdev);
1710
1711 /* Get SATA interrupt number */
1712 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1713 if (irq == NO_IRQ) {
1714 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1715 err = -ENODEV;
1716 goto error_out;
1717 }
1718
1719 /*
1720 * Now, register with libATA core, this will also initiate the
1721 * device discovery process, invoking our port_start() handler &
1722 * error_handler() to execute a dummy Softreset EH session
1723 */
1724 rc = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1725
1726 if (rc != 0)
1727 dev_err(&ofdev->dev, "failed to activate host");
1728
1729 dev_set_drvdata(&ofdev->dev, host);
1730 return 0;
1731
1732 error_out:
1733 /* Free SATA DMA resources */
1734 dma_dwc_exit(hsdev);
1735
1736 if (base)
1737 iounmap(base);
1738 return err;
1739 }
1740
1741 static int sata_dwc_remove(struct platform_device *ofdev)
1742 {
1743 struct device *dev = &ofdev->dev;
1744 struct ata_host *host = dev_get_drvdata(dev);
1745 struct sata_dwc_device *hsdev = host->private_data;
1746
1747 ata_host_detach(host);
1748 dev_set_drvdata(dev, NULL);
1749
1750 /* Free SATA DMA resources */
1751 dma_dwc_exit(hsdev);
1752
1753 iounmap(hsdev->reg_base);
1754 kfree(hsdev);
1755 kfree(host);
1756 dev_dbg(&ofdev->dev, "done\n");
1757 return 0;
1758 }
1759
1760 static const struct of_device_id sata_dwc_match[] = {
1761 { .compatible = "amcc,sata-460ex", },
1762 {}
1763 };
1764 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1765
1766 static struct platform_driver sata_dwc_driver = {
1767 .driver = {
1768 .name = DRV_NAME,
1769 .owner = THIS_MODULE,
1770 .of_match_table = sata_dwc_match,
1771 },
1772 .probe = sata_dwc_probe,
1773 .remove = sata_dwc_remove,
1774 };
1775
1776 static int __init sata_dwc_init(void)
1777 {
1778 return platform_driver_register(&sata_dwc_driver);
1779 }
1780
1781 static void __exit sata_dwc_exit(void)
1782 {
1783 platform_driver_unregister(&sata_dwc_driver);
1784 }
1785
1786 module_init(sata_dwc_init);
1787 module_exit(sata_dwc_exit);
1788
1789 MODULE_LICENSE("GPL");
1790 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1791 MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1792 MODULE_VERSION(DRV_VERSION);
Linux with added FPC-III support