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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / crypto / mv_cesa.c
blobf53dd83438bcab6af17001ec540b8174eec77a6f
1 /*
2 * Support for Marvell's crypto engine which can be found on some Orion5X
3 * boards.
4 *
5 * Author: Sebastian Andrzej Siewior < sebastian at breakpoint dot cc >
6 * License: GPLv2
7 *
8 */
9 #include <crypto/aes.h>
10 #include <crypto/algapi.h>
11 #include <linux/crypto.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/kthread.h>
15 #include <linux/platform_device.h>
16 #include <linux/scatterlist.h>
17 #include <linux/slab.h>
18 #include <crypto/internal/hash.h>
19 #include <crypto/sha.h>
20
21 #include "mv_cesa.h"
22
23 #define MV_CESA "MV-CESA:"
24 #define MAX_HW_HASH_SIZE 0xFFFF
25
26 /*
27 * STM:
28 * /---------------------------------------\
29 * | | request complete
30 * \./ |
31 * IDLE -> new request -> BUSY -> done -> DEQUEUE
32 * /°\ |
33 * | | more scatter entries
34 * \________________/
35 */
36 enum engine_status {
37 ENGINE_IDLE,
38 ENGINE_BUSY,
39 ENGINE_W_DEQUEUE,
40 };
41
42 /**
43 * struct req_progress - used for every crypt request
44 * @src_sg_it: sg iterator for src
45 * @dst_sg_it: sg iterator for dst
46 * @sg_src_left: bytes left in src to process (scatter list)
47 * @src_start: offset to add to src start position (scatter list)
48 * @crypt_len: length of current hw crypt/hash process
49 * @hw_nbytes: total bytes to process in hw for this request
50 * @copy_back: whether to copy data back (crypt) or not (hash)
51 * @sg_dst_left: bytes left dst to process in this scatter list
52 * @dst_start: offset to add to dst start position (scatter list)
53 * @hw_processed_bytes: number of bytes processed by hw (request).
54 *
55 * sg helper are used to iterate over the scatterlist. Since the size of the
56 * SRAM may be less than the scatter size, this struct struct is used to keep
57 * track of progress within current scatterlist.
58 */
59 struct req_progress {
60 struct sg_mapping_iter src_sg_it;
61 struct sg_mapping_iter dst_sg_it;
62 void (*complete) (void);
63 void (*process) (int is_first);
64
65 /* src mostly */
66 int sg_src_left;
67 int src_start;
68 int crypt_len;
69 int hw_nbytes;
70 /* dst mostly */
71 int copy_back;
72 int sg_dst_left;
73 int dst_start;
74 int hw_processed_bytes;
75 };
76
77 struct crypto_priv {
78 void __iomem *reg;
79 void __iomem *sram;
80 int irq;
81 struct task_struct *queue_th;
82
83 /* the lock protects queue and eng_st */
84 spinlock_t lock;
85 struct crypto_queue queue;
86 enum engine_status eng_st;
87 struct crypto_async_request *cur_req;
88 struct req_progress p;
89 int max_req_size;
90 int sram_size;
91 int has_sha1;
92 int has_hmac_sha1;
93 };
94
95 static struct crypto_priv *cpg;
96
97 struct mv_ctx {
98 u8 aes_enc_key[AES_KEY_LEN];
99 u32 aes_dec_key[8];
100 int key_len;
101 u32 need_calc_aes_dkey;
102 };
103
104 enum crypto_op {
105 COP_AES_ECB,
106 COP_AES_CBC,
107 };
108
109 struct mv_req_ctx {
110 enum crypto_op op;
111 int decrypt;
112 };
113
114 enum hash_op {
115 COP_SHA1,
116 COP_HMAC_SHA1
117 };
118
119 struct mv_tfm_hash_ctx {
120 struct crypto_shash *fallback;
121 struct crypto_shash *base_hash;
122 u32 ivs[2 * SHA1_DIGEST_SIZE / 4];
123 int count_add;
124 enum hash_op op;
125 };
126
127 struct mv_req_hash_ctx {
128 u64 count;
129 u32 state[SHA1_DIGEST_SIZE / 4];
130 u8 buffer[SHA1_BLOCK_SIZE];
131 int first_hash; /* marks that we don't have previous state */
132 int last_chunk; /* marks that this is the 'final' request */
133 int extra_bytes; /* unprocessed bytes in buffer */
134 enum hash_op op;
135 int count_add;
136 };
137
138 static void compute_aes_dec_key(struct mv_ctx *ctx)
139 {
140 struct crypto_aes_ctx gen_aes_key;
141 int key_pos;
142
143 if (!ctx->need_calc_aes_dkey)
144 return;
145
146 crypto_aes_expand_key(&gen_aes_key, ctx->aes_enc_key, ctx->key_len);
147
148 key_pos = ctx->key_len + 24;
149 memcpy(ctx->aes_dec_key, &gen_aes_key.key_enc[key_pos], 4 * 4);
150 switch (ctx->key_len) {
151 case AES_KEYSIZE_256:
152 key_pos -= 2;
153 /* fall */
154 case AES_KEYSIZE_192:
155 key_pos -= 2;
156 memcpy(&ctx->aes_dec_key[4], &gen_aes_key.key_enc[key_pos],
157 4 * 4);
158 break;
159 }
160 ctx->need_calc_aes_dkey = 0;
161 }
162
163 static int mv_setkey_aes(struct crypto_ablkcipher *cipher, const u8 *key,
164 unsigned int len)
165 {
166 struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
167 struct mv_ctx *ctx = crypto_tfm_ctx(tfm);
168
169 switch (len) {
170 case AES_KEYSIZE_128:
171 case AES_KEYSIZE_192:
172 case AES_KEYSIZE_256:
173 break;
174 default:
175 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
176 return -EINVAL;
177 }
178 ctx->key_len = len;
179 ctx->need_calc_aes_dkey = 1;
180
181 memcpy(ctx->aes_enc_key, key, AES_KEY_LEN);
182 return 0;
183 }
184
185 static void copy_src_to_buf(struct req_progress *p, char *dbuf, int len)
186 {
187 int ret;
188 void *sbuf;
189 int copy_len;
190
191 while (len) {
192 if (!p->sg_src_left) {
193 ret = sg_miter_next(&p->src_sg_it);
194 BUG_ON(!ret);
195 p->sg_src_left = p->src_sg_it.length;
196 p->src_start = 0;
197 }
198
199 sbuf = p->src_sg_it.addr + p->src_start;
200
201 copy_len = min(p->sg_src_left, len);
202 memcpy(dbuf, sbuf, copy_len);
203
204 p->src_start += copy_len;
205 p->sg_src_left -= copy_len;
206
207 len -= copy_len;
208 dbuf += copy_len;
209 }
210 }
211
212 static void setup_data_in(void)
213 {
214 struct req_progress *p = &cpg->p;
215 int data_in_sram =
216 min(p->hw_nbytes - p->hw_processed_bytes, cpg->max_req_size);
217 copy_src_to_buf(p, cpg->sram + SRAM_DATA_IN_START + p->crypt_len,
218 data_in_sram - p->crypt_len);
219 p->crypt_len = data_in_sram;
220 }
221
222 static void mv_process_current_q(int first_block)
223 {
224 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
225 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
226 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
227 struct sec_accel_config op;
228
229 switch (req_ctx->op) {
230 case COP_AES_ECB:
231 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_ECB;
232 break;
233 case COP_AES_CBC:
234 default:
235 op.config = CFG_OP_CRYPT_ONLY | CFG_ENCM_AES | CFG_ENC_MODE_CBC;
236 op.enc_iv = ENC_IV_POINT(SRAM_DATA_IV) |
237 ENC_IV_BUF_POINT(SRAM_DATA_IV_BUF);
238 if (first_block)
239 memcpy(cpg->sram + SRAM_DATA_IV, req->info, 16);
240 break;
241 }
242 if (req_ctx->decrypt) {
243 op.config |= CFG_DIR_DEC;
244 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_dec_key,
245 AES_KEY_LEN);
246 } else {
247 op.config |= CFG_DIR_ENC;
248 memcpy(cpg->sram + SRAM_DATA_KEY_P, ctx->aes_enc_key,
249 AES_KEY_LEN);
250 }
251
252 switch (ctx->key_len) {
253 case AES_KEYSIZE_128:
254 op.config |= CFG_AES_LEN_128;
255 break;
256 case AES_KEYSIZE_192:
257 op.config |= CFG_AES_LEN_192;
258 break;
259 case AES_KEYSIZE_256:
260 op.config |= CFG_AES_LEN_256;
261 break;
262 }
263 op.enc_p = ENC_P_SRC(SRAM_DATA_IN_START) |
264 ENC_P_DST(SRAM_DATA_OUT_START);
265 op.enc_key_p = SRAM_DATA_KEY_P;
266
267 setup_data_in();
268 op.enc_len = cpg->p.crypt_len;
269 memcpy(cpg->sram + SRAM_CONFIG, &op,
270 sizeof(struct sec_accel_config));
271
272 /* GO */
273 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
274
275 /*
276 * XXX: add timer if the interrupt does not occur for some mystery
277 * reason
278 */
279 }
280
281 static void mv_crypto_algo_completion(void)
282 {
283 struct ablkcipher_request *req = ablkcipher_request_cast(cpg->cur_req);
284 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
285
286 sg_miter_stop(&cpg->p.src_sg_it);
287 sg_miter_stop(&cpg->p.dst_sg_it);
288
289 if (req_ctx->op != COP_AES_CBC)
290 return ;
291
292 memcpy(req->info, cpg->sram + SRAM_DATA_IV_BUF, 16);
293 }
294
295 static void mv_process_hash_current(int first_block)
296 {
297 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
298 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
299 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
300 struct req_progress *p = &cpg->p;
301 struct sec_accel_config op = { 0 };
302 int is_last;
303
304 switch (req_ctx->op) {
305 case COP_SHA1:
306 default:
307 op.config = CFG_OP_MAC_ONLY | CFG_MACM_SHA1;
308 break;
309 case COP_HMAC_SHA1:
310 op.config = CFG_OP_MAC_ONLY | CFG_MACM_HMAC_SHA1;
311 memcpy(cpg->sram + SRAM_HMAC_IV_IN,
312 tfm_ctx->ivs, sizeof(tfm_ctx->ivs));
313 break;
314 }
315
316 op.mac_src_p =
317 MAC_SRC_DATA_P(SRAM_DATA_IN_START) | MAC_SRC_TOTAL_LEN((u32)
318 req_ctx->
319 count);
320
321 setup_data_in();
322
323 op.mac_digest =
324 MAC_DIGEST_P(SRAM_DIGEST_BUF) | MAC_FRAG_LEN(p->crypt_len);
325 op.mac_iv =
326 MAC_INNER_IV_P(SRAM_HMAC_IV_IN) |
327 MAC_OUTER_IV_P(SRAM_HMAC_IV_OUT);
328
329 is_last = req_ctx->last_chunk
330 && (p->hw_processed_bytes + p->crypt_len >= p->hw_nbytes)
331 && (req_ctx->count <= MAX_HW_HASH_SIZE);
332 if (req_ctx->first_hash) {
333 if (is_last)
334 op.config |= CFG_NOT_FRAG;
335 else
336 op.config |= CFG_FIRST_FRAG;
337
338 req_ctx->first_hash = 0;
339 } else {
340 if (is_last)
341 op.config |= CFG_LAST_FRAG;
342 else
343 op.config |= CFG_MID_FRAG;
344
345 if (first_block) {
346 writel(req_ctx->state[0], cpg->reg + DIGEST_INITIAL_VAL_A);
347 writel(req_ctx->state[1], cpg->reg + DIGEST_INITIAL_VAL_B);
348 writel(req_ctx->state[2], cpg->reg + DIGEST_INITIAL_VAL_C);
349 writel(req_ctx->state[3], cpg->reg + DIGEST_INITIAL_VAL_D);
350 writel(req_ctx->state[4], cpg->reg + DIGEST_INITIAL_VAL_E);
351 }
352 }
353
354 memcpy(cpg->sram + SRAM_CONFIG, &op, sizeof(struct sec_accel_config));
355
356 /* GO */
357 writel(SEC_CMD_EN_SEC_ACCL0, cpg->reg + SEC_ACCEL_CMD);
358
359 /*
360 * XXX: add timer if the interrupt does not occur for some mystery
361 * reason
362 */
363 }
364
365 static inline int mv_hash_import_sha1_ctx(const struct mv_req_hash_ctx *ctx,
366 struct shash_desc *desc)
367 {
368 int i;
369 struct sha1_state shash_state;
370
371 shash_state.count = ctx->count + ctx->count_add;
372 for (i = 0; i < 5; i++)
373 shash_state.state[i] = ctx->state[i];
374 memcpy(shash_state.buffer, ctx->buffer, sizeof(shash_state.buffer));
375 return crypto_shash_import(desc, &shash_state);
376 }
377
378 static int mv_hash_final_fallback(struct ahash_request *req)
379 {
380 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
381 struct mv_req_hash_ctx *req_ctx = ahash_request_ctx(req);
382 struct {
383 struct shash_desc shash;
384 char ctx[crypto_shash_descsize(tfm_ctx->fallback)];
385 } desc;
386 int rc;
387
388 desc.shash.tfm = tfm_ctx->fallback;
389 desc.shash.flags = CRYPTO_TFM_REQ_MAY_SLEEP;
390 if (unlikely(req_ctx->first_hash)) {
391 crypto_shash_init(&desc.shash);
392 crypto_shash_update(&desc.shash, req_ctx->buffer,
393 req_ctx->extra_bytes);
394 } else {
395 /* only SHA1 for now....
396 */
397 rc = mv_hash_import_sha1_ctx(req_ctx, &desc.shash);
398 if (rc)
399 goto out;
400 }
401 rc = crypto_shash_final(&desc.shash, req->result);
402 out:
403 return rc;
404 }
405
406 static void mv_hash_algo_completion(void)
407 {
408 struct ahash_request *req = ahash_request_cast(cpg->cur_req);
409 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
410
411 if (ctx->extra_bytes)
412 copy_src_to_buf(&cpg->p, ctx->buffer, ctx->extra_bytes);
413 sg_miter_stop(&cpg->p.src_sg_it);
414
415 if (likely(ctx->last_chunk)) {
416 if (likely(ctx->count <= MAX_HW_HASH_SIZE)) {
417 memcpy(req->result, cpg->sram + SRAM_DIGEST_BUF,
418 crypto_ahash_digestsize(crypto_ahash_reqtfm
419 (req)));
420 } else
421 mv_hash_final_fallback(req);
422 } else {
423 ctx->state[0] = readl(cpg->reg + DIGEST_INITIAL_VAL_A);
424 ctx->state[1] = readl(cpg->reg + DIGEST_INITIAL_VAL_B);
425 ctx->state[2] = readl(cpg->reg + DIGEST_INITIAL_VAL_C);
426 ctx->state[3] = readl(cpg->reg + DIGEST_INITIAL_VAL_D);
427 ctx->state[4] = readl(cpg->reg + DIGEST_INITIAL_VAL_E);
428 }
429 }
430
431 static void dequeue_complete_req(void)
432 {
433 struct crypto_async_request *req = cpg->cur_req;
434 void *buf;
435 int ret;
436 cpg->p.hw_processed_bytes += cpg->p.crypt_len;
437 if (cpg->p.copy_back) {
438 int need_copy_len = cpg->p.crypt_len;
439 int sram_offset = 0;
440 do {
441 int dst_copy;
442
443 if (!cpg->p.sg_dst_left) {
444 ret = sg_miter_next(&cpg->p.dst_sg_it);
445 BUG_ON(!ret);
446 cpg->p.sg_dst_left = cpg->p.dst_sg_it.length;
447 cpg->p.dst_start = 0;
448 }
449
450 buf = cpg->p.dst_sg_it.addr;
451 buf += cpg->p.dst_start;
452
453 dst_copy = min(need_copy_len, cpg->p.sg_dst_left);
454
455 memcpy(buf,
456 cpg->sram + SRAM_DATA_OUT_START + sram_offset,
457 dst_copy);
458 sram_offset += dst_copy;
459 cpg->p.sg_dst_left -= dst_copy;
460 need_copy_len -= dst_copy;
461 cpg->p.dst_start += dst_copy;
462 } while (need_copy_len > 0);
463 }
464
465 cpg->p.crypt_len = 0;
466
467 BUG_ON(cpg->eng_st != ENGINE_W_DEQUEUE);
468 if (cpg->p.hw_processed_bytes < cpg->p.hw_nbytes) {
469 /* process next scatter list entry */
470 cpg->eng_st = ENGINE_BUSY;
471 cpg->p.process(0);
472 } else {
473 cpg->p.complete();
474 cpg->eng_st = ENGINE_IDLE;
475 local_bh_disable();
476 req->complete(req, 0);
477 local_bh_enable();
478 }
479 }
480
481 static int count_sgs(struct scatterlist *sl, unsigned int total_bytes)
482 {
483 int i = 0;
484 size_t cur_len;
485
486 while (sl) {
487 cur_len = sl[i].length;
488 ++i;
489 if (total_bytes > cur_len)
490 total_bytes -= cur_len;
491 else
492 break;
493 }
494
495 return i;
496 }
497
498 static void mv_start_new_crypt_req(struct ablkcipher_request *req)
499 {
500 struct req_progress *p = &cpg->p;
501 int num_sgs;
502
503 cpg->cur_req = &req->base;
504 memset(p, 0, sizeof(struct req_progress));
505 p->hw_nbytes = req->nbytes;
506 p->complete = mv_crypto_algo_completion;
507 p->process = mv_process_current_q;
508 p->copy_back = 1;
509
510 num_sgs = count_sgs(req->src, req->nbytes);
511 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
512
513 num_sgs = count_sgs(req->dst, req->nbytes);
514 sg_miter_start(&p->dst_sg_it, req->dst, num_sgs, SG_MITER_TO_SG);
515
516 mv_process_current_q(1);
517 }
518
519 static void mv_start_new_hash_req(struct ahash_request *req)
520 {
521 struct req_progress *p = &cpg->p;
522 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
523 int num_sgs, hw_bytes, old_extra_bytes, rc;
524 cpg->cur_req = &req->base;
525 memset(p, 0, sizeof(struct req_progress));
526 hw_bytes = req->nbytes + ctx->extra_bytes;
527 old_extra_bytes = ctx->extra_bytes;
528
529 ctx->extra_bytes = hw_bytes % SHA1_BLOCK_SIZE;
530 if (ctx->extra_bytes != 0
531 && (!ctx->last_chunk || ctx->count > MAX_HW_HASH_SIZE))
532 hw_bytes -= ctx->extra_bytes;
533 else
534 ctx->extra_bytes = 0;
535
536 num_sgs = count_sgs(req->src, req->nbytes);
537 sg_miter_start(&p->src_sg_it, req->src, num_sgs, SG_MITER_FROM_SG);
538
539 if (hw_bytes) {
540 p->hw_nbytes = hw_bytes;
541 p->complete = mv_hash_algo_completion;
542 p->process = mv_process_hash_current;
543
544 if (unlikely(old_extra_bytes)) {
545 memcpy(cpg->sram + SRAM_DATA_IN_START, ctx->buffer,
546 old_extra_bytes);
547 p->crypt_len = old_extra_bytes;
548 }
549
550 mv_process_hash_current(1);
551 } else {
552 copy_src_to_buf(p, ctx->buffer + old_extra_bytes,
553 ctx->extra_bytes - old_extra_bytes);
554 sg_miter_stop(&p->src_sg_it);
555 if (ctx->last_chunk)
556 rc = mv_hash_final_fallback(req);
557 else
558 rc = 0;
559 cpg->eng_st = ENGINE_IDLE;
560 local_bh_disable();
561 req->base.complete(&req->base, rc);
562 local_bh_enable();
563 }
564 }
565
566 static int queue_manag(void *data)
567 {
568 cpg->eng_st = ENGINE_IDLE;
569 do {
570 struct crypto_async_request *async_req = NULL;
571 struct crypto_async_request *backlog;
572
573 __set_current_state(TASK_INTERRUPTIBLE);
574
575 if (cpg->eng_st == ENGINE_W_DEQUEUE)
576 dequeue_complete_req();
577
578 spin_lock_irq(&cpg->lock);
579 if (cpg->eng_st == ENGINE_IDLE) {
580 backlog = crypto_get_backlog(&cpg->queue);
581 async_req = crypto_dequeue_request(&cpg->queue);
582 if (async_req) {
583 BUG_ON(cpg->eng_st != ENGINE_IDLE);
584 cpg->eng_st = ENGINE_BUSY;
585 }
586 }
587 spin_unlock_irq(&cpg->lock);
588
589 if (backlog) {
590 backlog->complete(backlog, -EINPROGRESS);
591 backlog = NULL;
592 }
593
594 if (async_req) {
595 if (async_req->tfm->__crt_alg->cra_type !=
596 &crypto_ahash_type) {
597 struct ablkcipher_request *req =
598 ablkcipher_request_cast(async_req);
599 mv_start_new_crypt_req(req);
600 } else {
601 struct ahash_request *req =
602 ahash_request_cast(async_req);
603 mv_start_new_hash_req(req);
604 }
605 async_req = NULL;
606 }
607
608 schedule();
609
610 } while (!kthread_should_stop());
611 return 0;
612 }
613
614 static int mv_handle_req(struct crypto_async_request *req)
615 {
616 unsigned long flags;
617 int ret;
618
619 spin_lock_irqsave(&cpg->lock, flags);
620 ret = crypto_enqueue_request(&cpg->queue, req);
621 spin_unlock_irqrestore(&cpg->lock, flags);
622 wake_up_process(cpg->queue_th);
623 return ret;
624 }
625
626 static int mv_enc_aes_ecb(struct ablkcipher_request *req)
627 {
628 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
629
630 req_ctx->op = COP_AES_ECB;
631 req_ctx->decrypt = 0;
632
633 return mv_handle_req(&req->base);
634 }
635
636 static int mv_dec_aes_ecb(struct ablkcipher_request *req)
637 {
638 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
639 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
640
641 req_ctx->op = COP_AES_ECB;
642 req_ctx->decrypt = 1;
643
644 compute_aes_dec_key(ctx);
645 return mv_handle_req(&req->base);
646 }
647
648 static int mv_enc_aes_cbc(struct ablkcipher_request *req)
649 {
650 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
651
652 req_ctx->op = COP_AES_CBC;
653 req_ctx->decrypt = 0;
654
655 return mv_handle_req(&req->base);
656 }
657
658 static int mv_dec_aes_cbc(struct ablkcipher_request *req)
659 {
660 struct mv_ctx *ctx = crypto_tfm_ctx(req->base.tfm);
661 struct mv_req_ctx *req_ctx = ablkcipher_request_ctx(req);
662
663 req_ctx->op = COP_AES_CBC;
664 req_ctx->decrypt = 1;
665
666 compute_aes_dec_key(ctx);
667 return mv_handle_req(&req->base);
668 }
669
670 static int mv_cra_init(struct crypto_tfm *tfm)
671 {
672 tfm->crt_ablkcipher.reqsize = sizeof(struct mv_req_ctx);
673 return 0;
674 }
675
676 static void mv_init_hash_req_ctx(struct mv_req_hash_ctx *ctx, int op,
677 int is_last, unsigned int req_len,
678 int count_add)
679 {
680 memset(ctx, 0, sizeof(*ctx));
681 ctx->op = op;
682 ctx->count = req_len;
683 ctx->first_hash = 1;
684 ctx->last_chunk = is_last;
685 ctx->count_add = count_add;
686 }
687
688 static void mv_update_hash_req_ctx(struct mv_req_hash_ctx *ctx, int is_last,
689 unsigned req_len)
690 {
691 ctx->last_chunk = is_last;
692 ctx->count += req_len;
693 }
694
695 static int mv_hash_init(struct ahash_request *req)
696 {
697 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
698 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 0, 0,
699 tfm_ctx->count_add);
700 return 0;
701 }
702
703 static int mv_hash_update(struct ahash_request *req)
704 {
705 if (!req->nbytes)
706 return 0;
707
708 mv_update_hash_req_ctx(ahash_request_ctx(req), 0, req->nbytes);
709 return mv_handle_req(&req->base);
710 }
711
712 static int mv_hash_final(struct ahash_request *req)
713 {
714 struct mv_req_hash_ctx *ctx = ahash_request_ctx(req);
715
716 ahash_request_set_crypt(req, NULL, req->result, 0);
717 mv_update_hash_req_ctx(ctx, 1, 0);
718 return mv_handle_req(&req->base);
719 }
720
721 static int mv_hash_finup(struct ahash_request *req)
722 {
723 mv_update_hash_req_ctx(ahash_request_ctx(req), 1, req->nbytes);
724 return mv_handle_req(&req->base);
725 }
726
727 static int mv_hash_digest(struct ahash_request *req)
728 {
729 const struct mv_tfm_hash_ctx *tfm_ctx = crypto_tfm_ctx(req->base.tfm);
730 mv_init_hash_req_ctx(ahash_request_ctx(req), tfm_ctx->op, 1,
731 req->nbytes, tfm_ctx->count_add);
732 return mv_handle_req(&req->base);
733 }
734
735 static void mv_hash_init_ivs(struct mv_tfm_hash_ctx *ctx, const void *istate,
736 const void *ostate)
737 {
738 const struct sha1_state *isha1_state = istate, *osha1_state = ostate;
739 int i;
740 for (i = 0; i < 5; i++) {
741 ctx->ivs[i] = cpu_to_be32(isha1_state->state[i]);
742 ctx->ivs[i + 5] = cpu_to_be32(osha1_state->state[i]);
743 }
744 }
745
746 static int mv_hash_setkey(struct crypto_ahash *tfm, const u8 * key,
747 unsigned int keylen)
748 {
749 int rc;
750 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(&tfm->base);
751 int bs, ds, ss;
752
753 if (!ctx->base_hash)
754 return 0;
755
756 rc = crypto_shash_setkey(ctx->fallback, key, keylen);
757 if (rc)
758 return rc;
759
760 /* Can't see a way to extract the ipad/opad from the fallback tfm
761 so I'm basically copying code from the hmac module */
762 bs = crypto_shash_blocksize(ctx->base_hash);
763 ds = crypto_shash_digestsize(ctx->base_hash);
764 ss = crypto_shash_statesize(ctx->base_hash);
765
766 {
767 struct {
768 struct shash_desc shash;
769 char ctx[crypto_shash_descsize(ctx->base_hash)];
770 } desc;
771 unsigned int i;
772 char ipad[ss];
773 char opad[ss];
774
775 desc.shash.tfm = ctx->base_hash;
776 desc.shash.flags = crypto_shash_get_flags(ctx->base_hash) &
777 CRYPTO_TFM_REQ_MAY_SLEEP;
778
779 if (keylen > bs) {
780 int err;
781
782 err =
783 crypto_shash_digest(&desc.shash, key, keylen, ipad);
784 if (err)
785 return err;
786
787 keylen = ds;
788 } else
789 memcpy(ipad, key, keylen);
790
791 memset(ipad + keylen, 0, bs - keylen);
792 memcpy(opad, ipad, bs);
793
794 for (i = 0; i < bs; i++) {
795 ipad[i] ^= 0x36;
796 opad[i] ^= 0x5c;
797 }
798
799 rc = crypto_shash_init(&desc.shash) ? :
800 crypto_shash_update(&desc.shash, ipad, bs) ? :
801 crypto_shash_export(&desc.shash, ipad) ? :
802 crypto_shash_init(&desc.shash) ? :
803 crypto_shash_update(&desc.shash, opad, bs) ? :
804 crypto_shash_export(&desc.shash, opad);
805
806 if (rc == 0)
807 mv_hash_init_ivs(ctx, ipad, opad);
808
809 return rc;
810 }
811 }
812
813 static int mv_cra_hash_init(struct crypto_tfm *tfm, const char *base_hash_name,
814 enum hash_op op, int count_add)
815 {
816 const char *fallback_driver_name = tfm->__crt_alg->cra_name;
817 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
818 struct crypto_shash *fallback_tfm = NULL;
819 struct crypto_shash *base_hash = NULL;
820 int err = -ENOMEM;
821
822 ctx->op = op;
823 ctx->count_add = count_add;
824
825 /* Allocate a fallback and abort if it failed. */
826 fallback_tfm = crypto_alloc_shash(fallback_driver_name, 0,
827 CRYPTO_ALG_NEED_FALLBACK);
828 if (IS_ERR(fallback_tfm)) {
829 printk(KERN_WARNING MV_CESA
830 "Fallback driver '%s' could not be loaded!\n",
831 fallback_driver_name);
832 err = PTR_ERR(fallback_tfm);
833 goto out;
834 }
835 ctx->fallback = fallback_tfm;
836
837 if (base_hash_name) {
838 /* Allocate a hash to compute the ipad/opad of hmac. */
839 base_hash = crypto_alloc_shash(base_hash_name, 0,
840 CRYPTO_ALG_NEED_FALLBACK);
841 if (IS_ERR(base_hash)) {
842 printk(KERN_WARNING MV_CESA
843 "Base driver '%s' could not be loaded!\n",
844 base_hash_name);
845 err = PTR_ERR(base_hash);
846 goto err_bad_base;
847 }
848 }
849 ctx->base_hash = base_hash;
850
851 crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
852 sizeof(struct mv_req_hash_ctx) +
853 crypto_shash_descsize(ctx->fallback));
854 return 0;
855 err_bad_base:
856 crypto_free_shash(fallback_tfm);
857 out:
858 return err;
859 }
860
861 static void mv_cra_hash_exit(struct crypto_tfm *tfm)
862 {
863 struct mv_tfm_hash_ctx *ctx = crypto_tfm_ctx(tfm);
864
865 crypto_free_shash(ctx->fallback);
866 if (ctx->base_hash)
867 crypto_free_shash(ctx->base_hash);
868 }
869
870 static int mv_cra_hash_sha1_init(struct crypto_tfm *tfm)
871 {
872 return mv_cra_hash_init(tfm, NULL, COP_SHA1, 0);
873 }
874
875 static int mv_cra_hash_hmac_sha1_init(struct crypto_tfm *tfm)
876 {
877 return mv_cra_hash_init(tfm, "sha1", COP_HMAC_SHA1, SHA1_BLOCK_SIZE);
878 }
879
880 irqreturn_t crypto_int(int irq, void *priv)
881 {
882 u32 val;
883
884 val = readl(cpg->reg + SEC_ACCEL_INT_STATUS);
885 if (!(val & SEC_INT_ACCEL0_DONE))
886 return IRQ_NONE;
887
888 val &= ~SEC_INT_ACCEL0_DONE;
889 writel(val, cpg->reg + FPGA_INT_STATUS);
890 writel(val, cpg->reg + SEC_ACCEL_INT_STATUS);
891 BUG_ON(cpg->eng_st != ENGINE_BUSY);
892 cpg->eng_st = ENGINE_W_DEQUEUE;
893 wake_up_process(cpg->queue_th);
894 return IRQ_HANDLED;
895 }
896
897 struct crypto_alg mv_aes_alg_ecb = {
898 .cra_name = "ecb(aes)",
899 .cra_driver_name = "mv-ecb-aes",
900 .cra_priority = 300,
901 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
902 .cra_blocksize = 16,
903 .cra_ctxsize = sizeof(struct mv_ctx),
904 .cra_alignmask = 0,
905 .cra_type = &crypto_ablkcipher_type,
906 .cra_module = THIS_MODULE,
907 .cra_init = mv_cra_init,
908 .cra_u = {
909 .ablkcipher = {
910 .min_keysize = AES_MIN_KEY_SIZE,
911 .max_keysize = AES_MAX_KEY_SIZE,
912 .setkey = mv_setkey_aes,
913 .encrypt = mv_enc_aes_ecb,
914 .decrypt = mv_dec_aes_ecb,
915 },
916 },
917 };
918
919 struct crypto_alg mv_aes_alg_cbc = {
920 .cra_name = "cbc(aes)",
921 .cra_driver_name = "mv-cbc-aes",
922 .cra_priority = 300,
923 .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC,
924 .cra_blocksize = AES_BLOCK_SIZE,
925 .cra_ctxsize = sizeof(struct mv_ctx),
926 .cra_alignmask = 0,
927 .cra_type = &crypto_ablkcipher_type,
928 .cra_module = THIS_MODULE,
929 .cra_init = mv_cra_init,
930 .cra_u = {
931 .ablkcipher = {
932 .ivsize = AES_BLOCK_SIZE,
933 .min_keysize = AES_MIN_KEY_SIZE,
934 .max_keysize = AES_MAX_KEY_SIZE,
935 .setkey = mv_setkey_aes,
936 .encrypt = mv_enc_aes_cbc,
937 .decrypt = mv_dec_aes_cbc,
938 },
939 },
940 };
941
942 struct ahash_alg mv_sha1_alg = {
943 .init = mv_hash_init,
944 .update = mv_hash_update,
945 .final = mv_hash_final,
946 .finup = mv_hash_finup,
947 .digest = mv_hash_digest,
948 .halg = {
949 .digestsize = SHA1_DIGEST_SIZE,
950 .base = {
951 .cra_name = "sha1",
952 .cra_driver_name = "mv-sha1",
953 .cra_priority = 300,
954 .cra_flags =
955 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
956 .cra_blocksize = SHA1_BLOCK_SIZE,
957 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
958 .cra_init = mv_cra_hash_sha1_init,
959 .cra_exit = mv_cra_hash_exit,
960 .cra_module = THIS_MODULE,
961 }
962 }
963 };
964
965 struct ahash_alg mv_hmac_sha1_alg = {
966 .init = mv_hash_init,
967 .update = mv_hash_update,
968 .final = mv_hash_final,
969 .finup = mv_hash_finup,
970 .digest = mv_hash_digest,
971 .setkey = mv_hash_setkey,
972 .halg = {
973 .digestsize = SHA1_DIGEST_SIZE,
974 .base = {
975 .cra_name = "hmac(sha1)",
976 .cra_driver_name = "mv-hmac-sha1",
977 .cra_priority = 300,
978 .cra_flags =
979 CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
980 .cra_blocksize = SHA1_BLOCK_SIZE,
981 .cra_ctxsize = sizeof(struct mv_tfm_hash_ctx),
982 .cra_init = mv_cra_hash_hmac_sha1_init,
983 .cra_exit = mv_cra_hash_exit,
984 .cra_module = THIS_MODULE,
985 }
986 }
987 };
988
989 static int mv_probe(struct platform_device *pdev)
990 {
991 struct crypto_priv *cp;
992 struct resource *res;
993 int irq;
994 int ret;
995
996 if (cpg) {
997 printk(KERN_ERR MV_CESA "Second crypto dev?\n");
998 return -EEXIST;
999 }
1000
1001 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1002 if (!res)
1003 return -ENXIO;
1004
1005 cp = kzalloc(sizeof(*cp), GFP_KERNEL);
1006 if (!cp)
1007 return -ENOMEM;
1008
1009 spin_lock_init(&cp->lock);
1010 crypto_init_queue(&cp->queue, 50);
1011 cp->reg = ioremap(res->start, resource_size(res));
1012 if (!cp->reg) {
1013 ret = -ENOMEM;
1014 goto err;
1015 }
1016
1017 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
1018 if (!res) {
1019 ret = -ENXIO;
1020 goto err_unmap_reg;
1021 }
1022 cp->sram_size = resource_size(res);
1023 cp->max_req_size = cp->sram_size - SRAM_CFG_SPACE;
1024 cp->sram = ioremap(res->start, cp->sram_size);
1025 if (!cp->sram) {
1026 ret = -ENOMEM;
1027 goto err_unmap_reg;
1028 }
1029
1030 irq = platform_get_irq(pdev, 0);
1031 if (irq < 0 || irq == NO_IRQ) {
1032 ret = irq;
1033 goto err_unmap_sram;
1034 }
1035 cp->irq = irq;
1036
1037 platform_set_drvdata(pdev, cp);
1038 cpg = cp;
1039
1040 cp->queue_th = kthread_run(queue_manag, cp, "mv_crypto");
1041 if (IS_ERR(cp->queue_th)) {
1042 ret = PTR_ERR(cp->queue_th);
1043 goto err_unmap_sram;
1044 }
1045
1046 ret = request_irq(irq, crypto_int, IRQF_DISABLED, dev_name(&pdev->dev),
1047 cp);
1048 if (ret)
1049 goto err_thread;
1050
1051 writel(SEC_INT_ACCEL0_DONE, cpg->reg + SEC_ACCEL_INT_MASK);
1052 writel(SEC_CFG_STOP_DIG_ERR, cpg->reg + SEC_ACCEL_CFG);
1053 writel(SRAM_CONFIG, cpg->reg + SEC_ACCEL_DESC_P0);
1054
1055 ret = crypto_register_alg(&mv_aes_alg_ecb);
1056 if (ret) {
1057 printk(KERN_WARNING MV_CESA
1058 "Could not register aes-ecb driver\n");
1059 goto err_irq;
1060 }
1061
1062 ret = crypto_register_alg(&mv_aes_alg_cbc);
1063 if (ret) {
1064 printk(KERN_WARNING MV_CESA
1065 "Could not register aes-cbc driver\n");
1066 goto err_unreg_ecb;
1067 }
1068
1069 ret = crypto_register_ahash(&mv_sha1_alg);
1070 if (ret == 0)
1071 cpg->has_sha1 = 1;
1072 else
1073 printk(KERN_WARNING MV_CESA "Could not register sha1 driver\n");
1074
1075 ret = crypto_register_ahash(&mv_hmac_sha1_alg);
1076 if (ret == 0) {
1077 cpg->has_hmac_sha1 = 1;
1078 } else {
1079 printk(KERN_WARNING MV_CESA
1080 "Could not register hmac-sha1 driver\n");
1081 }
1082
1083 return 0;
1084 err_unreg_ecb:
1085 crypto_unregister_alg(&mv_aes_alg_ecb);
1086 err_irq:
1087 free_irq(irq, cp);
1088 err_thread:
1089 kthread_stop(cp->queue_th);
1090 err_unmap_sram:
1091 iounmap(cp->sram);
1092 err_unmap_reg:
1093 iounmap(cp->reg);
1094 err:
1095 kfree(cp);
1096 cpg = NULL;
1097 platform_set_drvdata(pdev, NULL);
1098 return ret;
1099 }
1100
1101 static int mv_remove(struct platform_device *pdev)
1102 {
1103 struct crypto_priv *cp = platform_get_drvdata(pdev);
1104
1105 crypto_unregister_alg(&mv_aes_alg_ecb);
1106 crypto_unregister_alg(&mv_aes_alg_cbc);
1107 if (cp->has_sha1)
1108 crypto_unregister_ahash(&mv_sha1_alg);
1109 if (cp->has_hmac_sha1)
1110 crypto_unregister_ahash(&mv_hmac_sha1_alg);
1111 kthread_stop(cp->queue_th);
1112 free_irq(cp->irq, cp);
1113 memset(cp->sram, 0, cp->sram_size);
1114 iounmap(cp->sram);
1115 iounmap(cp->reg);
1116 kfree(cp);
1117 cpg = NULL;
1118 return 0;
1119 }
1120
1121 static struct platform_driver marvell_crypto = {
1122 .probe = mv_probe,
1123 .remove = mv_remove,
1124 .driver = {
1125 .owner = THIS_MODULE,
1126 .name = "mv_crypto",
1127 },
1128 };
1129 MODULE_ALIAS("platform:mv_crypto");
1130
1131 static int __init mv_crypto_init(void)
1132 {
1133 return platform_driver_register(&marvell_crypto);
1134 }
1135 module_init(mv_crypto_init);
1136
1137 static void __exit mv_crypto_exit(void)
1138 {
1139 platform_driver_unregister(&marvell_crypto);
1140 }
1141 module_exit(mv_crypto_exit);
1142
1143 MODULE_AUTHOR("Sebastian Andrzej Siewior <sebastian@breakpoint.cc>");
1144 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");
1145 MODULE_LICENSE("GPL");
Linux with added FPC-III support