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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / firewire / ohci.c
blob271fc518dec5329e769359e194b804305ecd2602
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bitops.h>
22 #include <linux/bug.h>
23 #include <linux/compiler.h>
24 #include <linux/delay.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/firewire.h>
28 #include <linux/firewire-constants.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42 #include <linux/string.h>
43 #include <linux/time.h>
44 #include <linux/vmalloc.h>
45
46 #include <asm/byteorder.h>
47 #include <asm/page.h>
48 #include <asm/system.h>
49
50 #ifdef CONFIG_PPC_PMAC
51 #include <asm/pmac_feature.h>
52 #endif
53
54 #include "core.h"
55 #include "ohci.h"
56
57 #define DESCRIPTOR_OUTPUT_MORE 0
58 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
59 #define DESCRIPTOR_INPUT_MORE (2 << 12)
60 #define DESCRIPTOR_INPUT_LAST (3 << 12)
61 #define DESCRIPTOR_STATUS (1 << 11)
62 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
63 #define DESCRIPTOR_PING (1 << 7)
64 #define DESCRIPTOR_YY (1 << 6)
65 #define DESCRIPTOR_NO_IRQ (0 << 4)
66 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
67 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
68 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
69 #define DESCRIPTOR_WAIT (3 << 0)
70
71 struct descriptor {
72 __le16 req_count;
73 __le16 control;
74 __le32 data_address;
75 __le32 branch_address;
76 __le16 res_count;
77 __le16 transfer_status;
78 } __attribute__((aligned(16)));
79
80 #define CONTROL_SET(regs) (regs)
81 #define CONTROL_CLEAR(regs) ((regs) + 4)
82 #define COMMAND_PTR(regs) ((regs) + 12)
83 #define CONTEXT_MATCH(regs) ((regs) + 16)
84
85 #define AR_BUFFER_SIZE (32*1024)
86 #define AR_BUFFERS_MIN DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
87 /* we need at least two pages for proper list management */
88 #define AR_BUFFERS (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
89
90 #define MAX_ASYNC_PAYLOAD 4096
91 #define MAX_AR_PACKET_SIZE (16 + MAX_ASYNC_PAYLOAD + 4)
92 #define AR_WRAPAROUND_PAGES DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
93
94 struct ar_context {
95 struct fw_ohci *ohci;
96 struct page *pages[AR_BUFFERS];
97 void *buffer;
98 struct descriptor *descriptors;
99 dma_addr_t descriptors_bus;
100 void *pointer;
101 unsigned int last_buffer_index;
102 u32 regs;
103 struct tasklet_struct tasklet;
104 };
105
106 struct context;
107
108 typedef int (*descriptor_callback_t)(struct context *ctx,
109 struct descriptor *d,
110 struct descriptor *last);
111
112 /*
113 * A buffer that contains a block of DMA-able coherent memory used for
114 * storing a portion of a DMA descriptor program.
115 */
116 struct descriptor_buffer {
117 struct list_head list;
118 dma_addr_t buffer_bus;
119 size_t buffer_size;
120 size_t used;
121 struct descriptor buffer[0];
122 };
123
124 struct context {
125 struct fw_ohci *ohci;
126 u32 regs;
127 int total_allocation;
128 bool running;
129 bool flushing;
130
131 /*
132 * List of page-sized buffers for storing DMA descriptors.
133 * Head of list contains buffers in use and tail of list contains
134 * free buffers.
135 */
136 struct list_head buffer_list;
137
138 /*
139 * Pointer to a buffer inside buffer_list that contains the tail
140 * end of the current DMA program.
141 */
142 struct descriptor_buffer *buffer_tail;
143
144 /*
145 * The descriptor containing the branch address of the first
146 * descriptor that has not yet been filled by the device.
147 */
148 struct descriptor *last;
149
150 /*
151 * The last descriptor in the DMA program. It contains the branch
152 * address that must be updated upon appending a new descriptor.
153 */
154 struct descriptor *prev;
155
156 descriptor_callback_t callback;
157
158 struct tasklet_struct tasklet;
159 };
160
161 #define IT_HEADER_SY(v) ((v) << 0)
162 #define IT_HEADER_TCODE(v) ((v) << 4)
163 #define IT_HEADER_CHANNEL(v) ((v) << 8)
164 #define IT_HEADER_TAG(v) ((v) << 14)
165 #define IT_HEADER_SPEED(v) ((v) << 16)
166 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
167
168 struct iso_context {
169 struct fw_iso_context base;
170 struct context context;
171 int excess_bytes;
172 void *header;
173 size_t header_length;
174
175 u8 sync;
176 u8 tags;
177 };
178
179 #define CONFIG_ROM_SIZE 1024
180
181 struct fw_ohci {
182 struct fw_card card;
183
184 __iomem char *registers;
185 int node_id;
186 int generation;
187 int request_generation; /* for timestamping incoming requests */
188 unsigned quirks;
189 unsigned int pri_req_max;
190 u32 bus_time;
191 bool is_root;
192 bool csr_state_setclear_abdicate;
193 int n_ir;
194 int n_it;
195 /*
196 * Spinlock for accessing fw_ohci data. Never call out of
197 * this driver with this lock held.
198 */
199 spinlock_t lock;
200
201 struct mutex phy_reg_mutex;
202
203 void *misc_buffer;
204 dma_addr_t misc_buffer_bus;
205
206 struct ar_context ar_request_ctx;
207 struct ar_context ar_response_ctx;
208 struct context at_request_ctx;
209 struct context at_response_ctx;
210
211 u32 it_context_support;
212 u32 it_context_mask; /* unoccupied IT contexts */
213 struct iso_context *it_context_list;
214 u64 ir_context_channels; /* unoccupied channels */
215 u32 ir_context_support;
216 u32 ir_context_mask; /* unoccupied IR contexts */
217 struct iso_context *ir_context_list;
218 u64 mc_channels; /* channels in use by the multichannel IR context */
219 bool mc_allocated;
220
221 __be32 *config_rom;
222 dma_addr_t config_rom_bus;
223 __be32 *next_config_rom;
224 dma_addr_t next_config_rom_bus;
225 __be32 next_header;
226
227 __le32 *self_id_cpu;
228 dma_addr_t self_id_bus;
229 struct tasklet_struct bus_reset_tasklet;
230
231 u32 self_id_buffer[512];
232 };
233
234 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
235 {
236 return container_of(card, struct fw_ohci, card);
237 }
238
239 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
240 #define IR_CONTEXT_BUFFER_FILL 0x80000000
241 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
242 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
243 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
244 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
245
246 #define CONTEXT_RUN 0x8000
247 #define CONTEXT_WAKE 0x1000
248 #define CONTEXT_DEAD 0x0800
249 #define CONTEXT_ACTIVE 0x0400
250
251 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
252 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
253 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
254
255 #define OHCI1394_REGISTER_SIZE 0x800
256 #define OHCI_LOOP_COUNT 500
257 #define OHCI1394_PCI_HCI_Control 0x40
258 #define SELF_ID_BUF_SIZE 0x800
259 #define OHCI_TCODE_PHY_PACKET 0x0e
260 #define OHCI_VERSION_1_1 0x010010
261
262 static char ohci_driver_name[] = KBUILD_MODNAME;
263
264 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
265 #define PCI_DEVICE_ID_CREATIVE_SB1394 0x4001
266 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
267 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
268 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS 0x11bd
269
270 #define QUIRK_CYCLE_TIMER 1
271 #define QUIRK_RESET_PACKET 2
272 #define QUIRK_BE_HEADERS 4
273 #define QUIRK_NO_1394A 8
274 #define QUIRK_NO_MSI 16
275
276 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
277 static const struct {
278 unsigned short vendor, device, revision, flags;
279 } ohci_quirks[] = {
280 {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
281 QUIRK_CYCLE_TIMER},
282
283 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
284 QUIRK_BE_HEADERS},
285
286 {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
287 QUIRK_NO_MSI},
288
289 {PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_SB1394, PCI_ANY_ID,
290 QUIRK_RESET_PACKET},
291
292 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
293 QUIRK_NO_MSI},
294
295 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
296 QUIRK_CYCLE_TIMER},
297
298 {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
299 QUIRK_NO_MSI},
300
301 {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
302 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
303
304 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
305 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
306
307 {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
308 QUIRK_RESET_PACKET},
309
310 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
311 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
312 };
313
314 /* This overrides anything that was found in ohci_quirks[]. */
315 static int param_quirks;
316 module_param_named(quirks, param_quirks, int, 0644);
317 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
318 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
319 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
320 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
321 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
322 ", disable MSI = " __stringify(QUIRK_NO_MSI)
323 ")");
324
325 #define OHCI_PARAM_DEBUG_AT_AR 1
326 #define OHCI_PARAM_DEBUG_SELFIDS 2
327 #define OHCI_PARAM_DEBUG_IRQS 4
328 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
329
330 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
331
332 static int param_debug;
333 module_param_named(debug, param_debug, int, 0644);
334 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
335 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
336 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
337 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
338 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
339 ", or a combination, or all = -1)");
340
341 static void log_irqs(u32 evt)
342 {
343 if (likely(!(param_debug &
344 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
345 return;
346
347 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
348 !(evt & OHCI1394_busReset))
349 return;
350
351 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
352 evt & OHCI1394_selfIDComplete ? " selfID" : "",
353 evt & OHCI1394_RQPkt ? " AR_req" : "",
354 evt & OHCI1394_RSPkt ? " AR_resp" : "",
355 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
356 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
357 evt & OHCI1394_isochRx ? " IR" : "",
358 evt & OHCI1394_isochTx ? " IT" : "",
359 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
360 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
361 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
362 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
363 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
364 evt & OHCI1394_unrecoverableError ? " unrecoverableError" : "",
365 evt & OHCI1394_busReset ? " busReset" : "",
366 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
367 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
368 OHCI1394_respTxComplete | OHCI1394_isochRx |
369 OHCI1394_isochTx | OHCI1394_postedWriteErr |
370 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
371 OHCI1394_cycleInconsistent |
372 OHCI1394_regAccessFail | OHCI1394_busReset)
373 ? " ?" : "");
374 }
375
376 static const char *speed[] = {
377 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
378 };
379 static const char *power[] = {
380 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
381 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
382 };
383 static const char port[] = { '.', '-', 'p', 'c', };
384
385 static char _p(u32 *s, int shift)
386 {
387 return port[*s >> shift & 3];
388 }
389
390 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
391 {
392 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
393 return;
394
395 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
396 self_id_count, generation, node_id);
397
398 for (; self_id_count--; ++s)
399 if ((*s & 1 << 23) == 0)
400 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
401 "%s gc=%d %s %s%s%s\n",
402 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
403 speed[*s >> 14 & 3], *s >> 16 & 63,
404 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
405 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
406 else
407 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
408 *s, *s >> 24 & 63,
409 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
410 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
411 }
412
413 static const char *evts[] = {
414 [0x00] = "evt_no_status", [0x01] = "-reserved-",
415 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
416 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
417 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
418 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
419 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
420 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
421 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
422 [0x10] = "-reserved-", [0x11] = "ack_complete",
423 [0x12] = "ack_pending ", [0x13] = "-reserved-",
424 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
425 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
426 [0x18] = "-reserved-", [0x19] = "-reserved-",
427 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
428 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
429 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
430 [0x20] = "pending/cancelled",
431 };
432 static const char *tcodes[] = {
433 [0x0] = "QW req", [0x1] = "BW req",
434 [0x2] = "W resp", [0x3] = "-reserved-",
435 [0x4] = "QR req", [0x5] = "BR req",
436 [0x6] = "QR resp", [0x7] = "BR resp",
437 [0x8] = "cycle start", [0x9] = "Lk req",
438 [0xa] = "async stream packet", [0xb] = "Lk resp",
439 [0xc] = "-reserved-", [0xd] = "-reserved-",
440 [0xe] = "link internal", [0xf] = "-reserved-",
441 };
442
443 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
444 {
445 int tcode = header[0] >> 4 & 0xf;
446 char specific[12];
447
448 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
449 return;
450
451 if (unlikely(evt >= ARRAY_SIZE(evts)))
452 evt = 0x1f;
453
454 if (evt == OHCI1394_evt_bus_reset) {
455 fw_notify("A%c evt_bus_reset, generation %d\n",
456 dir, (header[2] >> 16) & 0xff);
457 return;
458 }
459
460 switch (tcode) {
461 case 0x0: case 0x6: case 0x8:
462 snprintf(specific, sizeof(specific), " = %08x",
463 be32_to_cpu((__force __be32)header[3]));
464 break;
465 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
466 snprintf(specific, sizeof(specific), " %x,%x",
467 header[3] >> 16, header[3] & 0xffff);
468 break;
469 default:
470 specific[0] = '\0';
471 }
472
473 switch (tcode) {
474 case 0xa:
475 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
476 break;
477 case 0xe:
478 fw_notify("A%c %s, PHY %08x %08x\n",
479 dir, evts[evt], header[1], header[2]);
480 break;
481 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
482 fw_notify("A%c spd %x tl %02x, "
483 "%04x -> %04x, %s, "
484 "%s, %04x%08x%s\n",
485 dir, speed, header[0] >> 10 & 0x3f,
486 header[1] >> 16, header[0] >> 16, evts[evt],
487 tcodes[tcode], header[1] & 0xffff, header[2], specific);
488 break;
489 default:
490 fw_notify("A%c spd %x tl %02x, "
491 "%04x -> %04x, %s, "
492 "%s%s\n",
493 dir, speed, header[0] >> 10 & 0x3f,
494 header[1] >> 16, header[0] >> 16, evts[evt],
495 tcodes[tcode], specific);
496 }
497 }
498
499 #else
500
501 #define param_debug 0
502 static inline void log_irqs(u32 evt) {}
503 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
504 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
505
506 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
507
508 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
509 {
510 writel(data, ohci->registers + offset);
511 }
512
513 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
514 {
515 return readl(ohci->registers + offset);
516 }
517
518 static inline void flush_writes(const struct fw_ohci *ohci)
519 {
520 /* Do a dummy read to flush writes. */
521 reg_read(ohci, OHCI1394_Version);
522 }
523
524 static int read_phy_reg(struct fw_ohci *ohci, int addr)
525 {
526 u32 val;
527 int i;
528
529 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
530 for (i = 0; i < 3 + 100; i++) {
531 val = reg_read(ohci, OHCI1394_PhyControl);
532 if (val & OHCI1394_PhyControl_ReadDone)
533 return OHCI1394_PhyControl_ReadData(val);
534
535 /*
536 * Try a few times without waiting. Sleeping is necessary
537 * only when the link/PHY interface is busy.
538 */
539 if (i >= 3)
540 msleep(1);
541 }
542 fw_error("failed to read phy reg\n");
543
544 return -EBUSY;
545 }
546
547 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
548 {
549 int i;
550
551 reg_write(ohci, OHCI1394_PhyControl,
552 OHCI1394_PhyControl_Write(addr, val));
553 for (i = 0; i < 3 + 100; i++) {
554 val = reg_read(ohci, OHCI1394_PhyControl);
555 if (!(val & OHCI1394_PhyControl_WritePending))
556 return 0;
557
558 if (i >= 3)
559 msleep(1);
560 }
561 fw_error("failed to write phy reg\n");
562
563 return -EBUSY;
564 }
565
566 static int update_phy_reg(struct fw_ohci *ohci, int addr,
567 int clear_bits, int set_bits)
568 {
569 int ret = read_phy_reg(ohci, addr);
570 if (ret < 0)
571 return ret;
572
573 /*
574 * The interrupt status bits are cleared by writing a one bit.
575 * Avoid clearing them unless explicitly requested in set_bits.
576 */
577 if (addr == 5)
578 clear_bits |= PHY_INT_STATUS_BITS;
579
580 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
581 }
582
583 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
584 {
585 int ret;
586
587 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
588 if (ret < 0)
589 return ret;
590
591 return read_phy_reg(ohci, addr);
592 }
593
594 static int ohci_read_phy_reg(struct fw_card *card, int addr)
595 {
596 struct fw_ohci *ohci = fw_ohci(card);
597 int ret;
598
599 mutex_lock(&ohci->phy_reg_mutex);
600 ret = read_phy_reg(ohci, addr);
601 mutex_unlock(&ohci->phy_reg_mutex);
602
603 return ret;
604 }
605
606 static int ohci_update_phy_reg(struct fw_card *card, int addr,
607 int clear_bits, int set_bits)
608 {
609 struct fw_ohci *ohci = fw_ohci(card);
610 int ret;
611
612 mutex_lock(&ohci->phy_reg_mutex);
613 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
614 mutex_unlock(&ohci->phy_reg_mutex);
615
616 return ret;
617 }
618
619 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
620 {
621 return page_private(ctx->pages[i]);
622 }
623
624 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
625 {
626 struct descriptor *d;
627
628 d = &ctx->descriptors[index];
629 d->branch_address &= cpu_to_le32(~0xf);
630 d->res_count = cpu_to_le16(PAGE_SIZE);
631 d->transfer_status = 0;
632
633 wmb(); /* finish init of new descriptors before branch_address update */
634 d = &ctx->descriptors[ctx->last_buffer_index];
635 d->branch_address |= cpu_to_le32(1);
636
637 ctx->last_buffer_index = index;
638
639 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
640 flush_writes(ctx->ohci);
641 }
642
643 static void ar_context_release(struct ar_context *ctx)
644 {
645 unsigned int i;
646
647 if (ctx->buffer)
648 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
649
650 for (i = 0; i < AR_BUFFERS; i++)
651 if (ctx->pages[i]) {
652 dma_unmap_page(ctx->ohci->card.device,
653 ar_buffer_bus(ctx, i),
654 PAGE_SIZE, DMA_FROM_DEVICE);
655 __free_page(ctx->pages[i]);
656 }
657 }
658
659 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
660 {
661 if (reg_read(ctx->ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
662 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
663 flush_writes(ctx->ohci);
664
665 fw_error("AR error: %s; DMA stopped\n", error_msg);
666 }
667 /* FIXME: restart? */
668 }
669
670 static inline unsigned int ar_next_buffer_index(unsigned int index)
671 {
672 return (index + 1) % AR_BUFFERS;
673 }
674
675 static inline unsigned int ar_prev_buffer_index(unsigned int index)
676 {
677 return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
678 }
679
680 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
681 {
682 return ar_next_buffer_index(ctx->last_buffer_index);
683 }
684
685 /*
686 * We search for the buffer that contains the last AR packet DMA data written
687 * by the controller.
688 */
689 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
690 unsigned int *buffer_offset)
691 {
692 unsigned int i, next_i, last = ctx->last_buffer_index;
693 __le16 res_count, next_res_count;
694
695 i = ar_first_buffer_index(ctx);
696 res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
697
698 /* A buffer that is not yet completely filled must be the last one. */
699 while (i != last && res_count == 0) {
700
701 /* Peek at the next descriptor. */
702 next_i = ar_next_buffer_index(i);
703 rmb(); /* read descriptors in order */
704 next_res_count = ACCESS_ONCE(
705 ctx->descriptors[next_i].res_count);
706 /*
707 * If the next descriptor is still empty, we must stop at this
708 * descriptor.
709 */
710 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
711 /*
712 * The exception is when the DMA data for one packet is
713 * split over three buffers; in this case, the middle
714 * buffer's descriptor might be never updated by the
715 * controller and look still empty, and we have to peek
716 * at the third one.
717 */
718 if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
719 next_i = ar_next_buffer_index(next_i);
720 rmb();
721 next_res_count = ACCESS_ONCE(
722 ctx->descriptors[next_i].res_count);
723 if (next_res_count != cpu_to_le16(PAGE_SIZE))
724 goto next_buffer_is_active;
725 }
726
727 break;
728 }
729
730 next_buffer_is_active:
731 i = next_i;
732 res_count = next_res_count;
733 }
734
735 rmb(); /* read res_count before the DMA data */
736
737 *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
738 if (*buffer_offset > PAGE_SIZE) {
739 *buffer_offset = 0;
740 ar_context_abort(ctx, "corrupted descriptor");
741 }
742
743 return i;
744 }
745
746 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
747 unsigned int end_buffer_index,
748 unsigned int end_buffer_offset)
749 {
750 unsigned int i;
751
752 i = ar_first_buffer_index(ctx);
753 while (i != end_buffer_index) {
754 dma_sync_single_for_cpu(ctx->ohci->card.device,
755 ar_buffer_bus(ctx, i),
756 PAGE_SIZE, DMA_FROM_DEVICE);
757 i = ar_next_buffer_index(i);
758 }
759 if (end_buffer_offset > 0)
760 dma_sync_single_for_cpu(ctx->ohci->card.device,
761 ar_buffer_bus(ctx, i),
762 end_buffer_offset, DMA_FROM_DEVICE);
763 }
764
765 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
766 #define cond_le32_to_cpu(v) \
767 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
768 #else
769 #define cond_le32_to_cpu(v) le32_to_cpu(v)
770 #endif
771
772 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
773 {
774 struct fw_ohci *ohci = ctx->ohci;
775 struct fw_packet p;
776 u32 status, length, tcode;
777 int evt;
778
779 p.header[0] = cond_le32_to_cpu(buffer[0]);
780 p.header[1] = cond_le32_to_cpu(buffer[1]);
781 p.header[2] = cond_le32_to_cpu(buffer[2]);
782
783 tcode = (p.header[0] >> 4) & 0x0f;
784 switch (tcode) {
785 case TCODE_WRITE_QUADLET_REQUEST:
786 case TCODE_READ_QUADLET_RESPONSE:
787 p.header[3] = (__force __u32) buffer[3];
788 p.header_length = 16;
789 p.payload_length = 0;
790 break;
791
792 case TCODE_READ_BLOCK_REQUEST :
793 p.header[3] = cond_le32_to_cpu(buffer[3]);
794 p.header_length = 16;
795 p.payload_length = 0;
796 break;
797
798 case TCODE_WRITE_BLOCK_REQUEST:
799 case TCODE_READ_BLOCK_RESPONSE:
800 case TCODE_LOCK_REQUEST:
801 case TCODE_LOCK_RESPONSE:
802 p.header[3] = cond_le32_to_cpu(buffer[3]);
803 p.header_length = 16;
804 p.payload_length = p.header[3] >> 16;
805 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
806 ar_context_abort(ctx, "invalid packet length");
807 return NULL;
808 }
809 break;
810
811 case TCODE_WRITE_RESPONSE:
812 case TCODE_READ_QUADLET_REQUEST:
813 case OHCI_TCODE_PHY_PACKET:
814 p.header_length = 12;
815 p.payload_length = 0;
816 break;
817
818 default:
819 ar_context_abort(ctx, "invalid tcode");
820 return NULL;
821 }
822
823 p.payload = (void *) buffer + p.header_length;
824
825 /* FIXME: What to do about evt_* errors? */
826 length = (p.header_length + p.payload_length + 3) / 4;
827 status = cond_le32_to_cpu(buffer[length]);
828 evt = (status >> 16) & 0x1f;
829
830 p.ack = evt - 16;
831 p.speed = (status >> 21) & 0x7;
832 p.timestamp = status & 0xffff;
833 p.generation = ohci->request_generation;
834
835 log_ar_at_event('R', p.speed, p.header, evt);
836
837 /*
838 * Several controllers, notably from NEC and VIA, forget to
839 * write ack_complete status at PHY packet reception.
840 */
841 if (evt == OHCI1394_evt_no_status &&
842 (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
843 p.ack = ACK_COMPLETE;
844
845 /*
846 * The OHCI bus reset handler synthesizes a PHY packet with
847 * the new generation number when a bus reset happens (see
848 * section 8.4.2.3). This helps us determine when a request
849 * was received and make sure we send the response in the same
850 * generation. We only need this for requests; for responses
851 * we use the unique tlabel for finding the matching
852 * request.
853 *
854 * Alas some chips sometimes emit bus reset packets with a
855 * wrong generation. We set the correct generation for these
856 * at a slightly incorrect time (in bus_reset_tasklet).
857 */
858 if (evt == OHCI1394_evt_bus_reset) {
859 if (!(ohci->quirks & QUIRK_RESET_PACKET))
860 ohci->request_generation = (p.header[2] >> 16) & 0xff;
861 } else if (ctx == &ohci->ar_request_ctx) {
862 fw_core_handle_request(&ohci->card, &p);
863 } else {
864 fw_core_handle_response(&ohci->card, &p);
865 }
866
867 return buffer + length + 1;
868 }
869
870 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
871 {
872 void *next;
873
874 while (p < end) {
875 next = handle_ar_packet(ctx, p);
876 if (!next)
877 return p;
878 p = next;
879 }
880
881 return p;
882 }
883
884 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
885 {
886 unsigned int i;
887
888 i = ar_first_buffer_index(ctx);
889 while (i != end_buffer) {
890 dma_sync_single_for_device(ctx->ohci->card.device,
891 ar_buffer_bus(ctx, i),
892 PAGE_SIZE, DMA_FROM_DEVICE);
893 ar_context_link_page(ctx, i);
894 i = ar_next_buffer_index(i);
895 }
896 }
897
898 static void ar_context_tasklet(unsigned long data)
899 {
900 struct ar_context *ctx = (struct ar_context *)data;
901 unsigned int end_buffer_index, end_buffer_offset;
902 void *p, *end;
903
904 p = ctx->pointer;
905 if (!p)
906 return;
907
908 end_buffer_index = ar_search_last_active_buffer(ctx,
909 &end_buffer_offset);
910 ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
911 end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
912
913 if (end_buffer_index < ar_first_buffer_index(ctx)) {
914 /*
915 * The filled part of the overall buffer wraps around; handle
916 * all packets up to the buffer end here. If the last packet
917 * wraps around, its tail will be visible after the buffer end
918 * because the buffer start pages are mapped there again.
919 */
920 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
921 p = handle_ar_packets(ctx, p, buffer_end);
922 if (p < buffer_end)
923 goto error;
924 /* adjust p to point back into the actual buffer */
925 p -= AR_BUFFERS * PAGE_SIZE;
926 }
927
928 p = handle_ar_packets(ctx, p, end);
929 if (p != end) {
930 if (p > end)
931 ar_context_abort(ctx, "inconsistent descriptor");
932 goto error;
933 }
934
935 ctx->pointer = p;
936 ar_recycle_buffers(ctx, end_buffer_index);
937
938 return;
939
940 error:
941 ctx->pointer = NULL;
942 }
943
944 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
945 unsigned int descriptors_offset, u32 regs)
946 {
947 unsigned int i;
948 dma_addr_t dma_addr;
949 struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
950 struct descriptor *d;
951
952 ctx->regs = regs;
953 ctx->ohci = ohci;
954 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
955
956 for (i = 0; i < AR_BUFFERS; i++) {
957 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
958 if (!ctx->pages[i])
959 goto out_of_memory;
960 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
961 0, PAGE_SIZE, DMA_FROM_DEVICE);
962 if (dma_mapping_error(ohci->card.device, dma_addr)) {
963 __free_page(ctx->pages[i]);
964 ctx->pages[i] = NULL;
965 goto out_of_memory;
966 }
967 set_page_private(ctx->pages[i], dma_addr);
968 }
969
970 for (i = 0; i < AR_BUFFERS; i++)
971 pages[i] = ctx->pages[i];
972 for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
973 pages[AR_BUFFERS + i] = ctx->pages[i];
974 ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
975 -1, PAGE_KERNEL);
976 if (!ctx->buffer)
977 goto out_of_memory;
978
979 ctx->descriptors = ohci->misc_buffer + descriptors_offset;
980 ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
981
982 for (i = 0; i < AR_BUFFERS; i++) {
983 d = &ctx->descriptors[i];
984 d->req_count = cpu_to_le16(PAGE_SIZE);
985 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
986 DESCRIPTOR_STATUS |
987 DESCRIPTOR_BRANCH_ALWAYS);
988 d->data_address = cpu_to_le32(ar_buffer_bus(ctx, i));
989 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
990 ar_next_buffer_index(i) * sizeof(struct descriptor));
991 }
992
993 return 0;
994
995 out_of_memory:
996 ar_context_release(ctx);
997
998 return -ENOMEM;
999 }
1000
1001 static void ar_context_run(struct ar_context *ctx)
1002 {
1003 unsigned int i;
1004
1005 for (i = 0; i < AR_BUFFERS; i++)
1006 ar_context_link_page(ctx, i);
1007
1008 ctx->pointer = ctx->buffer;
1009
1010 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1011 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1012 flush_writes(ctx->ohci);
1013 }
1014
1015 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1016 {
1017 __le16 branch;
1018
1019 branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1020
1021 /* figure out which descriptor the branch address goes in */
1022 if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1023 return d;
1024 else
1025 return d + z - 1;
1026 }
1027
1028 static void context_tasklet(unsigned long data)
1029 {
1030 struct context *ctx = (struct context *) data;
1031 struct descriptor *d, *last;
1032 u32 address;
1033 int z;
1034 struct descriptor_buffer *desc;
1035
1036 desc = list_entry(ctx->buffer_list.next,
1037 struct descriptor_buffer, list);
1038 last = ctx->last;
1039 while (last->branch_address != 0) {
1040 struct descriptor_buffer *old_desc = desc;
1041 address = le32_to_cpu(last->branch_address);
1042 z = address & 0xf;
1043 address &= ~0xf;
1044
1045 /* If the branch address points to a buffer outside of the
1046 * current buffer, advance to the next buffer. */
1047 if (address < desc->buffer_bus ||
1048 address >= desc->buffer_bus + desc->used)
1049 desc = list_entry(desc->list.next,
1050 struct descriptor_buffer, list);
1051 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1052 last = find_branch_descriptor(d, z);
1053
1054 if (!ctx->callback(ctx, d, last))
1055 break;
1056
1057 if (old_desc != desc) {
1058 /* If we've advanced to the next buffer, move the
1059 * previous buffer to the free list. */
1060 unsigned long flags;
1061 old_desc->used = 0;
1062 spin_lock_irqsave(&ctx->ohci->lock, flags);
1063 list_move_tail(&old_desc->list, &ctx->buffer_list);
1064 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1065 }
1066 ctx->last = last;
1067 }
1068 }
1069
1070 /*
1071 * Allocate a new buffer and add it to the list of free buffers for this
1072 * context. Must be called with ohci->lock held.
1073 */
1074 static int context_add_buffer(struct context *ctx)
1075 {
1076 struct descriptor_buffer *desc;
1077 dma_addr_t uninitialized_var(bus_addr);
1078 int offset;
1079
1080 /*
1081 * 16MB of descriptors should be far more than enough for any DMA
1082 * program. This will catch run-away userspace or DoS attacks.
1083 */
1084 if (ctx->total_allocation >= 16*1024*1024)
1085 return -ENOMEM;
1086
1087 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1088 &bus_addr, GFP_ATOMIC);
1089 if (!desc)
1090 return -ENOMEM;
1091
1092 offset = (void *)&desc->buffer - (void *)desc;
1093 desc->buffer_size = PAGE_SIZE - offset;
1094 desc->buffer_bus = bus_addr + offset;
1095 desc->used = 0;
1096
1097 list_add_tail(&desc->list, &ctx->buffer_list);
1098 ctx->total_allocation += PAGE_SIZE;
1099
1100 return 0;
1101 }
1102
1103 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1104 u32 regs, descriptor_callback_t callback)
1105 {
1106 ctx->ohci = ohci;
1107 ctx->regs = regs;
1108 ctx->total_allocation = 0;
1109
1110 INIT_LIST_HEAD(&ctx->buffer_list);
1111 if (context_add_buffer(ctx) < 0)
1112 return -ENOMEM;
1113
1114 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1115 struct descriptor_buffer, list);
1116
1117 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1118 ctx->callback = callback;
1119
1120 /*
1121 * We put a dummy descriptor in the buffer that has a NULL
1122 * branch address and looks like it's been sent. That way we
1123 * have a descriptor to append DMA programs to.
1124 */
1125 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1126 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1127 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1128 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1129 ctx->last = ctx->buffer_tail->buffer;
1130 ctx->prev = ctx->buffer_tail->buffer;
1131
1132 return 0;
1133 }
1134
1135 static void context_release(struct context *ctx)
1136 {
1137 struct fw_card *card = &ctx->ohci->card;
1138 struct descriptor_buffer *desc, *tmp;
1139
1140 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1141 dma_free_coherent(card->device, PAGE_SIZE, desc,
1142 desc->buffer_bus -
1143 ((void *)&desc->buffer - (void *)desc));
1144 }
1145
1146 /* Must be called with ohci->lock held */
1147 static struct descriptor *context_get_descriptors(struct context *ctx,
1148 int z, dma_addr_t *d_bus)
1149 {
1150 struct descriptor *d = NULL;
1151 struct descriptor_buffer *desc = ctx->buffer_tail;
1152
1153 if (z * sizeof(*d) > desc->buffer_size)
1154 return NULL;
1155
1156 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1157 /* No room for the descriptor in this buffer, so advance to the
1158 * next one. */
1159
1160 if (desc->list.next == &ctx->buffer_list) {
1161 /* If there is no free buffer next in the list,
1162 * allocate one. */
1163 if (context_add_buffer(ctx) < 0)
1164 return NULL;
1165 }
1166 desc = list_entry(desc->list.next,
1167 struct descriptor_buffer, list);
1168 ctx->buffer_tail = desc;
1169 }
1170
1171 d = desc->buffer + desc->used / sizeof(*d);
1172 memset(d, 0, z * sizeof(*d));
1173 *d_bus = desc->buffer_bus + desc->used;
1174
1175 return d;
1176 }
1177
1178 static void context_run(struct context *ctx, u32 extra)
1179 {
1180 struct fw_ohci *ohci = ctx->ohci;
1181
1182 reg_write(ohci, COMMAND_PTR(ctx->regs),
1183 le32_to_cpu(ctx->last->branch_address));
1184 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1185 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1186 ctx->running = true;
1187 flush_writes(ohci);
1188 }
1189
1190 static void context_append(struct context *ctx,
1191 struct descriptor *d, int z, int extra)
1192 {
1193 dma_addr_t d_bus;
1194 struct descriptor_buffer *desc = ctx->buffer_tail;
1195
1196 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1197
1198 desc->used += (z + extra) * sizeof(*d);
1199
1200 wmb(); /* finish init of new descriptors before branch_address update */
1201 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1202 ctx->prev = find_branch_descriptor(d, z);
1203 }
1204
1205 static void context_stop(struct context *ctx)
1206 {
1207 u32 reg;
1208 int i;
1209
1210 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1211 ctx->running = false;
1212 flush_writes(ctx->ohci);
1213
1214 for (i = 0; i < 10; i++) {
1215 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1216 if ((reg & CONTEXT_ACTIVE) == 0)
1217 return;
1218
1219 mdelay(1);
1220 }
1221 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1222 }
1223
1224 struct driver_data {
1225 u8 inline_data[8];
1226 struct fw_packet *packet;
1227 };
1228
1229 /*
1230 * This function apppends a packet to the DMA queue for transmission.
1231 * Must always be called with the ochi->lock held to ensure proper
1232 * generation handling and locking around packet queue manipulation.
1233 */
1234 static int at_context_queue_packet(struct context *ctx,
1235 struct fw_packet *packet)
1236 {
1237 struct fw_ohci *ohci = ctx->ohci;
1238 dma_addr_t d_bus, uninitialized_var(payload_bus);
1239 struct driver_data *driver_data;
1240 struct descriptor *d, *last;
1241 __le32 *header;
1242 int z, tcode;
1243
1244 d = context_get_descriptors(ctx, 4, &d_bus);
1245 if (d == NULL) {
1246 packet->ack = RCODE_SEND_ERROR;
1247 return -1;
1248 }
1249
1250 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1251 d[0].res_count = cpu_to_le16(packet->timestamp);
1252
1253 /*
1254 * The DMA format for asyncronous link packets is different
1255 * from the IEEE1394 layout, so shift the fields around
1256 * accordingly.
1257 */
1258
1259 tcode = (packet->header[0] >> 4) & 0x0f;
1260 header = (__le32 *) &d[1];
1261 switch (tcode) {
1262 case TCODE_WRITE_QUADLET_REQUEST:
1263 case TCODE_WRITE_BLOCK_REQUEST:
1264 case TCODE_WRITE_RESPONSE:
1265 case TCODE_READ_QUADLET_REQUEST:
1266 case TCODE_READ_BLOCK_REQUEST:
1267 case TCODE_READ_QUADLET_RESPONSE:
1268 case TCODE_READ_BLOCK_RESPONSE:
1269 case TCODE_LOCK_REQUEST:
1270 case TCODE_LOCK_RESPONSE:
1271 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1272 (packet->speed << 16));
1273 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1274 (packet->header[0] & 0xffff0000));
1275 header[2] = cpu_to_le32(packet->header[2]);
1276
1277 if (TCODE_IS_BLOCK_PACKET(tcode))
1278 header[3] = cpu_to_le32(packet->header[3]);
1279 else
1280 header[3] = (__force __le32) packet->header[3];
1281
1282 d[0].req_count = cpu_to_le16(packet->header_length);
1283 break;
1284
1285 case TCODE_LINK_INTERNAL:
1286 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1287 (packet->speed << 16));
1288 header[1] = cpu_to_le32(packet->header[1]);
1289 header[2] = cpu_to_le32(packet->header[2]);
1290 d[0].req_count = cpu_to_le16(12);
1291
1292 if (is_ping_packet(&packet->header[1]))
1293 d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1294 break;
1295
1296 case TCODE_STREAM_DATA:
1297 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1298 (packet->speed << 16));
1299 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1300 d[0].req_count = cpu_to_le16(8);
1301 break;
1302
1303 default:
1304 /* BUG(); */
1305 packet->ack = RCODE_SEND_ERROR;
1306 return -1;
1307 }
1308
1309 BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1310 driver_data = (struct driver_data *) &d[3];
1311 driver_data->packet = packet;
1312 packet->driver_data = driver_data;
1313
1314 if (packet->payload_length > 0) {
1315 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1316 payload_bus = dma_map_single(ohci->card.device,
1317 packet->payload,
1318 packet->payload_length,
1319 DMA_TO_DEVICE);
1320 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1321 packet->ack = RCODE_SEND_ERROR;
1322 return -1;
1323 }
1324 packet->payload_bus = payload_bus;
1325 packet->payload_mapped = true;
1326 } else {
1327 memcpy(driver_data->inline_data, packet->payload,
1328 packet->payload_length);
1329 payload_bus = d_bus + 3 * sizeof(*d);
1330 }
1331
1332 d[2].req_count = cpu_to_le16(packet->payload_length);
1333 d[2].data_address = cpu_to_le32(payload_bus);
1334 last = &d[2];
1335 z = 3;
1336 } else {
1337 last = &d[0];
1338 z = 2;
1339 }
1340
1341 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1342 DESCRIPTOR_IRQ_ALWAYS |
1343 DESCRIPTOR_BRANCH_ALWAYS);
1344
1345 /* FIXME: Document how the locking works. */
1346 if (ohci->generation != packet->generation) {
1347 if (packet->payload_mapped)
1348 dma_unmap_single(ohci->card.device, payload_bus,
1349 packet->payload_length, DMA_TO_DEVICE);
1350 packet->ack = RCODE_GENERATION;
1351 return -1;
1352 }
1353
1354 context_append(ctx, d, z, 4 - z);
1355
1356 if (ctx->running) {
1357 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1358 flush_writes(ohci);
1359 } else {
1360 context_run(ctx, 0);
1361 }
1362
1363 return 0;
1364 }
1365
1366 static void at_context_flush(struct context *ctx)
1367 {
1368 tasklet_disable(&ctx->tasklet);
1369
1370 ctx->flushing = true;
1371 context_tasklet((unsigned long)ctx);
1372 ctx->flushing = false;
1373
1374 tasklet_enable(&ctx->tasklet);
1375 }
1376
1377 static int handle_at_packet(struct context *context,
1378 struct descriptor *d,
1379 struct descriptor *last)
1380 {
1381 struct driver_data *driver_data;
1382 struct fw_packet *packet;
1383 struct fw_ohci *ohci = context->ohci;
1384 int evt;
1385
1386 if (last->transfer_status == 0 && !context->flushing)
1387 /* This descriptor isn't done yet, stop iteration. */
1388 return 0;
1389
1390 driver_data = (struct driver_data *) &d[3];
1391 packet = driver_data->packet;
1392 if (packet == NULL)
1393 /* This packet was cancelled, just continue. */
1394 return 1;
1395
1396 if (packet->payload_mapped)
1397 dma_unmap_single(ohci->card.device, packet->payload_bus,
1398 packet->payload_length, DMA_TO_DEVICE);
1399
1400 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1401 packet->timestamp = le16_to_cpu(last->res_count);
1402
1403 log_ar_at_event('T', packet->speed, packet->header, evt);
1404
1405 switch (evt) {
1406 case OHCI1394_evt_timeout:
1407 /* Async response transmit timed out. */
1408 packet->ack = RCODE_CANCELLED;
1409 break;
1410
1411 case OHCI1394_evt_flushed:
1412 /*
1413 * The packet was flushed should give same error as
1414 * when we try to use a stale generation count.
1415 */
1416 packet->ack = RCODE_GENERATION;
1417 break;
1418
1419 case OHCI1394_evt_missing_ack:
1420 if (context->flushing)
1421 packet->ack = RCODE_GENERATION;
1422 else {
1423 /*
1424 * Using a valid (current) generation count, but the
1425 * node is not on the bus or not sending acks.
1426 */
1427 packet->ack = RCODE_NO_ACK;
1428 }
1429 break;
1430
1431 case ACK_COMPLETE + 0x10:
1432 case ACK_PENDING + 0x10:
1433 case ACK_BUSY_X + 0x10:
1434 case ACK_BUSY_A + 0x10:
1435 case ACK_BUSY_B + 0x10:
1436 case ACK_DATA_ERROR + 0x10:
1437 case ACK_TYPE_ERROR + 0x10:
1438 packet->ack = evt - 0x10;
1439 break;
1440
1441 case OHCI1394_evt_no_status:
1442 if (context->flushing) {
1443 packet->ack = RCODE_GENERATION;
1444 break;
1445 }
1446 /* fall through */
1447
1448 default:
1449 packet->ack = RCODE_SEND_ERROR;
1450 break;
1451 }
1452
1453 packet->callback(packet, &ohci->card, packet->ack);
1454
1455 return 1;
1456 }
1457
1458 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1459 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1460 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1461 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1462 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1463
1464 static void handle_local_rom(struct fw_ohci *ohci,
1465 struct fw_packet *packet, u32 csr)
1466 {
1467 struct fw_packet response;
1468 int tcode, length, i;
1469
1470 tcode = HEADER_GET_TCODE(packet->header[0]);
1471 if (TCODE_IS_BLOCK_PACKET(tcode))
1472 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1473 else
1474 length = 4;
1475
1476 i = csr - CSR_CONFIG_ROM;
1477 if (i + length > CONFIG_ROM_SIZE) {
1478 fw_fill_response(&response, packet->header,
1479 RCODE_ADDRESS_ERROR, NULL, 0);
1480 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1481 fw_fill_response(&response, packet->header,
1482 RCODE_TYPE_ERROR, NULL, 0);
1483 } else {
1484 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1485 (void *) ohci->config_rom + i, length);
1486 }
1487
1488 fw_core_handle_response(&ohci->card, &response);
1489 }
1490
1491 static void handle_local_lock(struct fw_ohci *ohci,
1492 struct fw_packet *packet, u32 csr)
1493 {
1494 struct fw_packet response;
1495 int tcode, length, ext_tcode, sel, try;
1496 __be32 *payload, lock_old;
1497 u32 lock_arg, lock_data;
1498
1499 tcode = HEADER_GET_TCODE(packet->header[0]);
1500 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1501 payload = packet->payload;
1502 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1503
1504 if (tcode == TCODE_LOCK_REQUEST &&
1505 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1506 lock_arg = be32_to_cpu(payload[0]);
1507 lock_data = be32_to_cpu(payload[1]);
1508 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1509 lock_arg = 0;
1510 lock_data = 0;
1511 } else {
1512 fw_fill_response(&response, packet->header,
1513 RCODE_TYPE_ERROR, NULL, 0);
1514 goto out;
1515 }
1516
1517 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1518 reg_write(ohci, OHCI1394_CSRData, lock_data);
1519 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1520 reg_write(ohci, OHCI1394_CSRControl, sel);
1521
1522 for (try = 0; try < 20; try++)
1523 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1524 lock_old = cpu_to_be32(reg_read(ohci,
1525 OHCI1394_CSRData));
1526 fw_fill_response(&response, packet->header,
1527 RCODE_COMPLETE,
1528 &lock_old, sizeof(lock_old));
1529 goto out;
1530 }
1531
1532 fw_error("swap not done (CSR lock timeout)\n");
1533 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1534
1535 out:
1536 fw_core_handle_response(&ohci->card, &response);
1537 }
1538
1539 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1540 {
1541 u64 offset, csr;
1542
1543 if (ctx == &ctx->ohci->at_request_ctx) {
1544 packet->ack = ACK_PENDING;
1545 packet->callback(packet, &ctx->ohci->card, packet->ack);
1546 }
1547
1548 offset =
1549 ((unsigned long long)
1550 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1551 packet->header[2];
1552 csr = offset - CSR_REGISTER_BASE;
1553
1554 /* Handle config rom reads. */
1555 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1556 handle_local_rom(ctx->ohci, packet, csr);
1557 else switch (csr) {
1558 case CSR_BUS_MANAGER_ID:
1559 case CSR_BANDWIDTH_AVAILABLE:
1560 case CSR_CHANNELS_AVAILABLE_HI:
1561 case CSR_CHANNELS_AVAILABLE_LO:
1562 handle_local_lock(ctx->ohci, packet, csr);
1563 break;
1564 default:
1565 if (ctx == &ctx->ohci->at_request_ctx)
1566 fw_core_handle_request(&ctx->ohci->card, packet);
1567 else
1568 fw_core_handle_response(&ctx->ohci->card, packet);
1569 break;
1570 }
1571
1572 if (ctx == &ctx->ohci->at_response_ctx) {
1573 packet->ack = ACK_COMPLETE;
1574 packet->callback(packet, &ctx->ohci->card, packet->ack);
1575 }
1576 }
1577
1578 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1579 {
1580 unsigned long flags;
1581 int ret;
1582
1583 spin_lock_irqsave(&ctx->ohci->lock, flags);
1584
1585 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1586 ctx->ohci->generation == packet->generation) {
1587 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1588 handle_local_request(ctx, packet);
1589 return;
1590 }
1591
1592 ret = at_context_queue_packet(ctx, packet);
1593 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1594
1595 if (ret < 0)
1596 packet->callback(packet, &ctx->ohci->card, packet->ack);
1597
1598 }
1599
1600 static void detect_dead_context(struct fw_ohci *ohci,
1601 const char *name, unsigned int regs)
1602 {
1603 u32 ctl;
1604
1605 ctl = reg_read(ohci, CONTROL_SET(regs));
1606 if (ctl & CONTEXT_DEAD) {
1607 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
1608 fw_error("DMA context %s has stopped, error code: %s\n",
1609 name, evts[ctl & 0x1f]);
1610 #else
1611 fw_error("DMA context %s has stopped, error code: %#x\n",
1612 name, ctl & 0x1f);
1613 #endif
1614 }
1615 }
1616
1617 static void handle_dead_contexts(struct fw_ohci *ohci)
1618 {
1619 unsigned int i;
1620 char name[8];
1621
1622 detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1623 detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1624 detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1625 detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1626 for (i = 0; i < 32; ++i) {
1627 if (!(ohci->it_context_support & (1 << i)))
1628 continue;
1629 sprintf(name, "IT%u", i);
1630 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1631 }
1632 for (i = 0; i < 32; ++i) {
1633 if (!(ohci->ir_context_support & (1 << i)))
1634 continue;
1635 sprintf(name, "IR%u", i);
1636 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1637 }
1638 /* TODO: maybe try to flush and restart the dead contexts */
1639 }
1640
1641 static u32 cycle_timer_ticks(u32 cycle_timer)
1642 {
1643 u32 ticks;
1644
1645 ticks = cycle_timer & 0xfff;
1646 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1647 ticks += (3072 * 8000) * (cycle_timer >> 25);
1648
1649 return ticks;
1650 }
1651
1652 /*
1653 * Some controllers exhibit one or more of the following bugs when updating the
1654 * iso cycle timer register:
1655 * - When the lowest six bits are wrapping around to zero, a read that happens
1656 * at the same time will return garbage in the lowest ten bits.
1657 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1658 * not incremented for about 60 ns.
1659 * - Occasionally, the entire register reads zero.
1660 *
1661 * To catch these, we read the register three times and ensure that the
1662 * difference between each two consecutive reads is approximately the same, i.e.
1663 * less than twice the other. Furthermore, any negative difference indicates an
1664 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1665 * execute, so we have enough precision to compute the ratio of the differences.)
1666 */
1667 static u32 get_cycle_time(struct fw_ohci *ohci)
1668 {
1669 u32 c0, c1, c2;
1670 u32 t0, t1, t2;
1671 s32 diff01, diff12;
1672 int i;
1673
1674 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1675
1676 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1677 i = 0;
1678 c1 = c2;
1679 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1680 do {
1681 c0 = c1;
1682 c1 = c2;
1683 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1684 t0 = cycle_timer_ticks(c0);
1685 t1 = cycle_timer_ticks(c1);
1686 t2 = cycle_timer_ticks(c2);
1687 diff01 = t1 - t0;
1688 diff12 = t2 - t1;
1689 } while ((diff01 <= 0 || diff12 <= 0 ||
1690 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1691 && i++ < 20);
1692 }
1693
1694 return c2;
1695 }
1696
1697 /*
1698 * This function has to be called at least every 64 seconds. The bus_time
1699 * field stores not only the upper 25 bits of the BUS_TIME register but also
1700 * the most significant bit of the cycle timer in bit 6 so that we can detect
1701 * changes in this bit.
1702 */
1703 static u32 update_bus_time(struct fw_ohci *ohci)
1704 {
1705 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1706
1707 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1708 ohci->bus_time += 0x40;
1709
1710 return ohci->bus_time | cycle_time_seconds;
1711 }
1712
1713 static void bus_reset_tasklet(unsigned long data)
1714 {
1715 struct fw_ohci *ohci = (struct fw_ohci *)data;
1716 int self_id_count, i, j, reg;
1717 int generation, new_generation;
1718 unsigned long flags;
1719 void *free_rom = NULL;
1720 dma_addr_t free_rom_bus = 0;
1721 bool is_new_root;
1722
1723 reg = reg_read(ohci, OHCI1394_NodeID);
1724 if (!(reg & OHCI1394_NodeID_idValid)) {
1725 fw_notify("node ID not valid, new bus reset in progress\n");
1726 return;
1727 }
1728 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1729 fw_notify("malconfigured bus\n");
1730 return;
1731 }
1732 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1733 OHCI1394_NodeID_nodeNumber);
1734
1735 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1736 if (!(ohci->is_root && is_new_root))
1737 reg_write(ohci, OHCI1394_LinkControlSet,
1738 OHCI1394_LinkControl_cycleMaster);
1739 ohci->is_root = is_new_root;
1740
1741 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1742 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1743 fw_notify("inconsistent self IDs\n");
1744 return;
1745 }
1746 /*
1747 * The count in the SelfIDCount register is the number of
1748 * bytes in the self ID receive buffer. Since we also receive
1749 * the inverted quadlets and a header quadlet, we shift one
1750 * bit extra to get the actual number of self IDs.
1751 */
1752 self_id_count = (reg >> 3) & 0xff;
1753 if (self_id_count == 0 || self_id_count > 252) {
1754 fw_notify("inconsistent self IDs\n");
1755 return;
1756 }
1757 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1758 rmb();
1759
1760 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1761 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1762 fw_notify("inconsistent self IDs\n");
1763 return;
1764 }
1765 ohci->self_id_buffer[j] =
1766 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1767 }
1768 rmb();
1769
1770 /*
1771 * Check the consistency of the self IDs we just read. The
1772 * problem we face is that a new bus reset can start while we
1773 * read out the self IDs from the DMA buffer. If this happens,
1774 * the DMA buffer will be overwritten with new self IDs and we
1775 * will read out inconsistent data. The OHCI specification
1776 * (section 11.2) recommends a technique similar to
1777 * linux/seqlock.h, where we remember the generation of the
1778 * self IDs in the buffer before reading them out and compare
1779 * it to the current generation after reading them out. If
1780 * the two generations match we know we have a consistent set
1781 * of self IDs.
1782 */
1783
1784 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1785 if (new_generation != generation) {
1786 fw_notify("recursive bus reset detected, "
1787 "discarding self ids\n");
1788 return;
1789 }
1790
1791 /* FIXME: Document how the locking works. */
1792 spin_lock_irqsave(&ohci->lock, flags);
1793
1794 ohci->generation = -1; /* prevent AT packet queueing */
1795 context_stop(&ohci->at_request_ctx);
1796 context_stop(&ohci->at_response_ctx);
1797
1798 spin_unlock_irqrestore(&ohci->lock, flags);
1799
1800 /*
1801 * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1802 * packets in the AT queues and software needs to drain them.
1803 * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1804 */
1805 at_context_flush(&ohci->at_request_ctx);
1806 at_context_flush(&ohci->at_response_ctx);
1807
1808 spin_lock_irqsave(&ohci->lock, flags);
1809
1810 ohci->generation = generation;
1811 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1812
1813 if (ohci->quirks & QUIRK_RESET_PACKET)
1814 ohci->request_generation = generation;
1815
1816 /*
1817 * This next bit is unrelated to the AT context stuff but we
1818 * have to do it under the spinlock also. If a new config rom
1819 * was set up before this reset, the old one is now no longer
1820 * in use and we can free it. Update the config rom pointers
1821 * to point to the current config rom and clear the
1822 * next_config_rom pointer so a new update can take place.
1823 */
1824
1825 if (ohci->next_config_rom != NULL) {
1826 if (ohci->next_config_rom != ohci->config_rom) {
1827 free_rom = ohci->config_rom;
1828 free_rom_bus = ohci->config_rom_bus;
1829 }
1830 ohci->config_rom = ohci->next_config_rom;
1831 ohci->config_rom_bus = ohci->next_config_rom_bus;
1832 ohci->next_config_rom = NULL;
1833
1834 /*
1835 * Restore config_rom image and manually update
1836 * config_rom registers. Writing the header quadlet
1837 * will indicate that the config rom is ready, so we
1838 * do that last.
1839 */
1840 reg_write(ohci, OHCI1394_BusOptions,
1841 be32_to_cpu(ohci->config_rom[2]));
1842 ohci->config_rom[0] = ohci->next_header;
1843 reg_write(ohci, OHCI1394_ConfigROMhdr,
1844 be32_to_cpu(ohci->next_header));
1845 }
1846
1847 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1848 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1849 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1850 #endif
1851
1852 spin_unlock_irqrestore(&ohci->lock, flags);
1853
1854 if (free_rom)
1855 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1856 free_rom, free_rom_bus);
1857
1858 log_selfids(ohci->node_id, generation,
1859 self_id_count, ohci->self_id_buffer);
1860
1861 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1862 self_id_count, ohci->self_id_buffer,
1863 ohci->csr_state_setclear_abdicate);
1864 ohci->csr_state_setclear_abdicate = false;
1865 }
1866
1867 static irqreturn_t irq_handler(int irq, void *data)
1868 {
1869 struct fw_ohci *ohci = data;
1870 u32 event, iso_event;
1871 int i;
1872
1873 event = reg_read(ohci, OHCI1394_IntEventClear);
1874
1875 if (!event || !~event)
1876 return IRQ_NONE;
1877
1878 /*
1879 * busReset and postedWriteErr must not be cleared yet
1880 * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
1881 */
1882 reg_write(ohci, OHCI1394_IntEventClear,
1883 event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
1884 log_irqs(event);
1885
1886 if (event & OHCI1394_selfIDComplete)
1887 tasklet_schedule(&ohci->bus_reset_tasklet);
1888
1889 if (event & OHCI1394_RQPkt)
1890 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1891
1892 if (event & OHCI1394_RSPkt)
1893 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1894
1895 if (event & OHCI1394_reqTxComplete)
1896 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1897
1898 if (event & OHCI1394_respTxComplete)
1899 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1900
1901 if (event & OHCI1394_isochRx) {
1902 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1903 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1904
1905 while (iso_event) {
1906 i = ffs(iso_event) - 1;
1907 tasklet_schedule(
1908 &ohci->ir_context_list[i].context.tasklet);
1909 iso_event &= ~(1 << i);
1910 }
1911 }
1912
1913 if (event & OHCI1394_isochTx) {
1914 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1915 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1916
1917 while (iso_event) {
1918 i = ffs(iso_event) - 1;
1919 tasklet_schedule(
1920 &ohci->it_context_list[i].context.tasklet);
1921 iso_event &= ~(1 << i);
1922 }
1923 }
1924
1925 if (unlikely(event & OHCI1394_regAccessFail))
1926 fw_error("Register access failure - "
1927 "please notify linux1394-devel@lists.sf.net\n");
1928
1929 if (unlikely(event & OHCI1394_postedWriteErr)) {
1930 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
1931 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
1932 reg_write(ohci, OHCI1394_IntEventClear,
1933 OHCI1394_postedWriteErr);
1934 fw_error("PCI posted write error\n");
1935 }
1936
1937 if (unlikely(event & OHCI1394_cycleTooLong)) {
1938 if (printk_ratelimit())
1939 fw_notify("isochronous cycle too long\n");
1940 reg_write(ohci, OHCI1394_LinkControlSet,
1941 OHCI1394_LinkControl_cycleMaster);
1942 }
1943
1944 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1945 /*
1946 * We need to clear this event bit in order to make
1947 * cycleMatch isochronous I/O work. In theory we should
1948 * stop active cycleMatch iso contexts now and restart
1949 * them at least two cycles later. (FIXME?)
1950 */
1951 if (printk_ratelimit())
1952 fw_notify("isochronous cycle inconsistent\n");
1953 }
1954
1955 if (unlikely(event & OHCI1394_unrecoverableError))
1956 handle_dead_contexts(ohci);
1957
1958 if (event & OHCI1394_cycle64Seconds) {
1959 spin_lock(&ohci->lock);
1960 update_bus_time(ohci);
1961 spin_unlock(&ohci->lock);
1962 } else
1963 flush_writes(ohci);
1964
1965 return IRQ_HANDLED;
1966 }
1967
1968 static int software_reset(struct fw_ohci *ohci)
1969 {
1970 int i;
1971
1972 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1973
1974 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1975 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1976 OHCI1394_HCControl_softReset) == 0)
1977 return 0;
1978 msleep(1);
1979 }
1980
1981 return -EBUSY;
1982 }
1983
1984 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1985 {
1986 size_t size = length * 4;
1987
1988 memcpy(dest, src, size);
1989 if (size < CONFIG_ROM_SIZE)
1990 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1991 }
1992
1993 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1994 {
1995 bool enable_1394a;
1996 int ret, clear, set, offset;
1997
1998 /* Check if the driver should configure link and PHY. */
1999 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2000 OHCI1394_HCControl_programPhyEnable))
2001 return 0;
2002
2003 /* Paranoia: check whether the PHY supports 1394a, too. */
2004 enable_1394a = false;
2005 ret = read_phy_reg(ohci, 2);
2006 if (ret < 0)
2007 return ret;
2008 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2009 ret = read_paged_phy_reg(ohci, 1, 8);
2010 if (ret < 0)
2011 return ret;
2012 if (ret >= 1)
2013 enable_1394a = true;
2014 }
2015
2016 if (ohci->quirks & QUIRK_NO_1394A)
2017 enable_1394a = false;
2018
2019 /* Configure PHY and link consistently. */
2020 if (enable_1394a) {
2021 clear = 0;
2022 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2023 } else {
2024 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2025 set = 0;
2026 }
2027 ret = update_phy_reg(ohci, 5, clear, set);
2028 if (ret < 0)
2029 return ret;
2030
2031 if (enable_1394a)
2032 offset = OHCI1394_HCControlSet;
2033 else
2034 offset = OHCI1394_HCControlClear;
2035 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2036
2037 /* Clean up: configuration has been taken care of. */
2038 reg_write(ohci, OHCI1394_HCControlClear,
2039 OHCI1394_HCControl_programPhyEnable);
2040
2041 return 0;
2042 }
2043
2044 static int ohci_enable(struct fw_card *card,
2045 const __be32 *config_rom, size_t length)
2046 {
2047 struct fw_ohci *ohci = fw_ohci(card);
2048 struct pci_dev *dev = to_pci_dev(card->device);
2049 u32 lps, seconds, version, irqs;
2050 int i, ret;
2051
2052 if (software_reset(ohci)) {
2053 fw_error("Failed to reset ohci card.\n");
2054 return -EBUSY;
2055 }
2056
2057 /*
2058 * Now enable LPS, which we need in order to start accessing
2059 * most of the registers. In fact, on some cards (ALI M5251),
2060 * accessing registers in the SClk domain without LPS enabled
2061 * will lock up the machine. Wait 50msec to make sure we have
2062 * full link enabled. However, with some cards (well, at least
2063 * a JMicron PCIe card), we have to try again sometimes.
2064 */
2065 reg_write(ohci, OHCI1394_HCControlSet,
2066 OHCI1394_HCControl_LPS |
2067 OHCI1394_HCControl_postedWriteEnable);
2068 flush_writes(ohci);
2069
2070 for (lps = 0, i = 0; !lps && i < 3; i++) {
2071 msleep(50);
2072 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2073 OHCI1394_HCControl_LPS;
2074 }
2075
2076 if (!lps) {
2077 fw_error("Failed to set Link Power Status\n");
2078 return -EIO;
2079 }
2080
2081 reg_write(ohci, OHCI1394_HCControlClear,
2082 OHCI1394_HCControl_noByteSwapData);
2083
2084 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2085 reg_write(ohci, OHCI1394_LinkControlSet,
2086 OHCI1394_LinkControl_cycleTimerEnable |
2087 OHCI1394_LinkControl_cycleMaster);
2088
2089 reg_write(ohci, OHCI1394_ATRetries,
2090 OHCI1394_MAX_AT_REQ_RETRIES |
2091 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2092 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2093 (200 << 16));
2094
2095 seconds = lower_32_bits(get_seconds());
2096 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2097 ohci->bus_time = seconds & ~0x3f;
2098
2099 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2100 if (version >= OHCI_VERSION_1_1) {
2101 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2102 0xfffffffe);
2103 card->broadcast_channel_auto_allocated = true;
2104 }
2105
2106 /* Get implemented bits of the priority arbitration request counter. */
2107 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2108 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2109 reg_write(ohci, OHCI1394_FairnessControl, 0);
2110 card->priority_budget_implemented = ohci->pri_req_max != 0;
2111
2112 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2113 reg_write(ohci, OHCI1394_IntEventClear, ~0);
2114 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2115
2116 ret = configure_1394a_enhancements(ohci);
2117 if (ret < 0)
2118 return ret;
2119
2120 /* Activate link_on bit and contender bit in our self ID packets.*/
2121 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2122 if (ret < 0)
2123 return ret;
2124
2125 /*
2126 * When the link is not yet enabled, the atomic config rom
2127 * update mechanism described below in ohci_set_config_rom()
2128 * is not active. We have to update ConfigRomHeader and
2129 * BusOptions manually, and the write to ConfigROMmap takes
2130 * effect immediately. We tie this to the enabling of the
2131 * link, so we have a valid config rom before enabling - the
2132 * OHCI requires that ConfigROMhdr and BusOptions have valid
2133 * values before enabling.
2134 *
2135 * However, when the ConfigROMmap is written, some controllers
2136 * always read back quadlets 0 and 2 from the config rom to
2137 * the ConfigRomHeader and BusOptions registers on bus reset.
2138 * They shouldn't do that in this initial case where the link
2139 * isn't enabled. This means we have to use the same
2140 * workaround here, setting the bus header to 0 and then write
2141 * the right values in the bus reset tasklet.
2142 */
2143
2144 if (config_rom) {
2145 ohci->next_config_rom =
2146 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2147 &ohci->next_config_rom_bus,
2148 GFP_KERNEL);
2149 if (ohci->next_config_rom == NULL)
2150 return -ENOMEM;
2151
2152 copy_config_rom(ohci->next_config_rom, config_rom, length);
2153 } else {
2154 /*
2155 * In the suspend case, config_rom is NULL, which
2156 * means that we just reuse the old config rom.
2157 */
2158 ohci->next_config_rom = ohci->config_rom;
2159 ohci->next_config_rom_bus = ohci->config_rom_bus;
2160 }
2161
2162 ohci->next_header = ohci->next_config_rom[0];
2163 ohci->next_config_rom[0] = 0;
2164 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2165 reg_write(ohci, OHCI1394_BusOptions,
2166 be32_to_cpu(ohci->next_config_rom[2]));
2167 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2168
2169 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2170
2171 if (!(ohci->quirks & QUIRK_NO_MSI))
2172 pci_enable_msi(dev);
2173 if (request_irq(dev->irq, irq_handler,
2174 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2175 ohci_driver_name, ohci)) {
2176 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
2177 pci_disable_msi(dev);
2178 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2179 ohci->config_rom, ohci->config_rom_bus);
2180 return -EIO;
2181 }
2182
2183 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2184 OHCI1394_RQPkt | OHCI1394_RSPkt |
2185 OHCI1394_isochTx | OHCI1394_isochRx |
2186 OHCI1394_postedWriteErr |
2187 OHCI1394_selfIDComplete |
2188 OHCI1394_regAccessFail |
2189 OHCI1394_cycle64Seconds |
2190 OHCI1394_cycleInconsistent |
2191 OHCI1394_unrecoverableError |
2192 OHCI1394_cycleTooLong |
2193 OHCI1394_masterIntEnable;
2194 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2195 irqs |= OHCI1394_busReset;
2196 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2197
2198 reg_write(ohci, OHCI1394_HCControlSet,
2199 OHCI1394_HCControl_linkEnable |
2200 OHCI1394_HCControl_BIBimageValid);
2201
2202 reg_write(ohci, OHCI1394_LinkControlSet,
2203 OHCI1394_LinkControl_rcvSelfID |
2204 OHCI1394_LinkControl_rcvPhyPkt);
2205
2206 ar_context_run(&ohci->ar_request_ctx);
2207 ar_context_run(&ohci->ar_response_ctx); /* also flushes writes */
2208
2209 /* We are ready to go, reset bus to finish initialization. */
2210 fw_schedule_bus_reset(&ohci->card, false, true);
2211
2212 return 0;
2213 }
2214
2215 static int ohci_set_config_rom(struct fw_card *card,
2216 const __be32 *config_rom, size_t length)
2217 {
2218 struct fw_ohci *ohci;
2219 unsigned long flags;
2220 __be32 *next_config_rom;
2221 dma_addr_t uninitialized_var(next_config_rom_bus);
2222
2223 ohci = fw_ohci(card);
2224
2225 /*
2226 * When the OHCI controller is enabled, the config rom update
2227 * mechanism is a bit tricky, but easy enough to use. See
2228 * section 5.5.6 in the OHCI specification.
2229 *
2230 * The OHCI controller caches the new config rom address in a
2231 * shadow register (ConfigROMmapNext) and needs a bus reset
2232 * for the changes to take place. When the bus reset is
2233 * detected, the controller loads the new values for the
2234 * ConfigRomHeader and BusOptions registers from the specified
2235 * config rom and loads ConfigROMmap from the ConfigROMmapNext
2236 * shadow register. All automatically and atomically.
2237 *
2238 * Now, there's a twist to this story. The automatic load of
2239 * ConfigRomHeader and BusOptions doesn't honor the
2240 * noByteSwapData bit, so with a be32 config rom, the
2241 * controller will load be32 values in to these registers
2242 * during the atomic update, even on litte endian
2243 * architectures. The workaround we use is to put a 0 in the
2244 * header quadlet; 0 is endian agnostic and means that the
2245 * config rom isn't ready yet. In the bus reset tasklet we
2246 * then set up the real values for the two registers.
2247 *
2248 * We use ohci->lock to avoid racing with the code that sets
2249 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
2250 */
2251
2252 next_config_rom =
2253 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2254 &next_config_rom_bus, GFP_KERNEL);
2255 if (next_config_rom == NULL)
2256 return -ENOMEM;
2257
2258 spin_lock_irqsave(&ohci->lock, flags);
2259
2260 /*
2261 * If there is not an already pending config_rom update,
2262 * push our new allocation into the ohci->next_config_rom
2263 * and then mark the local variable as null so that we
2264 * won't deallocate the new buffer.
2265 *
2266 * OTOH, if there is a pending config_rom update, just
2267 * use that buffer with the new config_rom data, and
2268 * let this routine free the unused DMA allocation.
2269 */
2270
2271 if (ohci->next_config_rom == NULL) {
2272 ohci->next_config_rom = next_config_rom;
2273 ohci->next_config_rom_bus = next_config_rom_bus;
2274 next_config_rom = NULL;
2275 }
2276
2277 copy_config_rom(ohci->next_config_rom, config_rom, length);
2278
2279 ohci->next_header = config_rom[0];
2280 ohci->next_config_rom[0] = 0;
2281
2282 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2283
2284 spin_unlock_irqrestore(&ohci->lock, flags);
2285
2286 /* If we didn't use the DMA allocation, delete it. */
2287 if (next_config_rom != NULL)
2288 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2289 next_config_rom, next_config_rom_bus);
2290
2291 /*
2292 * Now initiate a bus reset to have the changes take
2293 * effect. We clean up the old config rom memory and DMA
2294 * mappings in the bus reset tasklet, since the OHCI
2295 * controller could need to access it before the bus reset
2296 * takes effect.
2297 */
2298
2299 fw_schedule_bus_reset(&ohci->card, true, true);
2300
2301 return 0;
2302 }
2303
2304 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2305 {
2306 struct fw_ohci *ohci = fw_ohci(card);
2307
2308 at_context_transmit(&ohci->at_request_ctx, packet);
2309 }
2310
2311 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2312 {
2313 struct fw_ohci *ohci = fw_ohci(card);
2314
2315 at_context_transmit(&ohci->at_response_ctx, packet);
2316 }
2317
2318 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2319 {
2320 struct fw_ohci *ohci = fw_ohci(card);
2321 struct context *ctx = &ohci->at_request_ctx;
2322 struct driver_data *driver_data = packet->driver_data;
2323 int ret = -ENOENT;
2324
2325 tasklet_disable(&ctx->tasklet);
2326
2327 if (packet->ack != 0)
2328 goto out;
2329
2330 if (packet->payload_mapped)
2331 dma_unmap_single(ohci->card.device, packet->payload_bus,
2332 packet->payload_length, DMA_TO_DEVICE);
2333
2334 log_ar_at_event('T', packet->speed, packet->header, 0x20);
2335 driver_data->packet = NULL;
2336 packet->ack = RCODE_CANCELLED;
2337 packet->callback(packet, &ohci->card, packet->ack);
2338 ret = 0;
2339 out:
2340 tasklet_enable(&ctx->tasklet);
2341
2342 return ret;
2343 }
2344
2345 static int ohci_enable_phys_dma(struct fw_card *card,
2346 int node_id, int generation)
2347 {
2348 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2349 return 0;
2350 #else
2351 struct fw_ohci *ohci = fw_ohci(card);
2352 unsigned long flags;
2353 int n, ret = 0;
2354
2355 /*
2356 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2357 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2358 */
2359
2360 spin_lock_irqsave(&ohci->lock, flags);
2361
2362 if (ohci->generation != generation) {
2363 ret = -ESTALE;
2364 goto out;
2365 }
2366
2367 /*
2368 * Note, if the node ID contains a non-local bus ID, physical DMA is
2369 * enabled for _all_ nodes on remote buses.
2370 */
2371
2372 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2373 if (n < 32)
2374 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2375 else
2376 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2377
2378 flush_writes(ohci);
2379 out:
2380 spin_unlock_irqrestore(&ohci->lock, flags);
2381
2382 return ret;
2383 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2384 }
2385
2386 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2387 {
2388 struct fw_ohci *ohci = fw_ohci(card);
2389 unsigned long flags;
2390 u32 value;
2391
2392 switch (csr_offset) {
2393 case CSR_STATE_CLEAR:
2394 case CSR_STATE_SET:
2395 if (ohci->is_root &&
2396 (reg_read(ohci, OHCI1394_LinkControlSet) &
2397 OHCI1394_LinkControl_cycleMaster))
2398 value = CSR_STATE_BIT_CMSTR;
2399 else
2400 value = 0;
2401 if (ohci->csr_state_setclear_abdicate)
2402 value |= CSR_STATE_BIT_ABDICATE;
2403
2404 return value;
2405
2406 case CSR_NODE_IDS:
2407 return reg_read(ohci, OHCI1394_NodeID) << 16;
2408
2409 case CSR_CYCLE_TIME:
2410 return get_cycle_time(ohci);
2411
2412 case CSR_BUS_TIME:
2413 /*
2414 * We might be called just after the cycle timer has wrapped
2415 * around but just before the cycle64Seconds handler, so we
2416 * better check here, too, if the bus time needs to be updated.
2417 */
2418 spin_lock_irqsave(&ohci->lock, flags);
2419 value = update_bus_time(ohci);
2420 spin_unlock_irqrestore(&ohci->lock, flags);
2421 return value;
2422
2423 case CSR_BUSY_TIMEOUT:
2424 value = reg_read(ohci, OHCI1394_ATRetries);
2425 return (value >> 4) & 0x0ffff00f;
2426
2427 case CSR_PRIORITY_BUDGET:
2428 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2429 (ohci->pri_req_max << 8);
2430
2431 default:
2432 WARN_ON(1);
2433 return 0;
2434 }
2435 }
2436
2437 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2438 {
2439 struct fw_ohci *ohci = fw_ohci(card);
2440 unsigned long flags;
2441
2442 switch (csr_offset) {
2443 case CSR_STATE_CLEAR:
2444 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2445 reg_write(ohci, OHCI1394_LinkControlClear,
2446 OHCI1394_LinkControl_cycleMaster);
2447 flush_writes(ohci);
2448 }
2449 if (value & CSR_STATE_BIT_ABDICATE)
2450 ohci->csr_state_setclear_abdicate = false;
2451 break;
2452
2453 case CSR_STATE_SET:
2454 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2455 reg_write(ohci, OHCI1394_LinkControlSet,
2456 OHCI1394_LinkControl_cycleMaster);
2457 flush_writes(ohci);
2458 }
2459 if (value & CSR_STATE_BIT_ABDICATE)
2460 ohci->csr_state_setclear_abdicate = true;
2461 break;
2462
2463 case CSR_NODE_IDS:
2464 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2465 flush_writes(ohci);
2466 break;
2467
2468 case CSR_CYCLE_TIME:
2469 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2470 reg_write(ohci, OHCI1394_IntEventSet,
2471 OHCI1394_cycleInconsistent);
2472 flush_writes(ohci);
2473 break;
2474
2475 case CSR_BUS_TIME:
2476 spin_lock_irqsave(&ohci->lock, flags);
2477 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2478 spin_unlock_irqrestore(&ohci->lock, flags);
2479 break;
2480
2481 case CSR_BUSY_TIMEOUT:
2482 value = (value & 0xf) | ((value & 0xf) << 4) |
2483 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2484 reg_write(ohci, OHCI1394_ATRetries, value);
2485 flush_writes(ohci);
2486 break;
2487
2488 case CSR_PRIORITY_BUDGET:
2489 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2490 flush_writes(ohci);
2491 break;
2492
2493 default:
2494 WARN_ON(1);
2495 break;
2496 }
2497 }
2498
2499 static void copy_iso_headers(struct iso_context *ctx, void *p)
2500 {
2501 int i = ctx->header_length;
2502
2503 if (i + ctx->base.header_size > PAGE_SIZE)
2504 return;
2505
2506 /*
2507 * The iso header is byteswapped to little endian by
2508 * the controller, but the remaining header quadlets
2509 * are big endian. We want to present all the headers
2510 * as big endian, so we have to swap the first quadlet.
2511 */
2512 if (ctx->base.header_size > 0)
2513 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2514 if (ctx->base.header_size > 4)
2515 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2516 if (ctx->base.header_size > 8)
2517 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2518 ctx->header_length += ctx->base.header_size;
2519 }
2520
2521 static int handle_ir_packet_per_buffer(struct context *context,
2522 struct descriptor *d,
2523 struct descriptor *last)
2524 {
2525 struct iso_context *ctx =
2526 container_of(context, struct iso_context, context);
2527 struct descriptor *pd;
2528 __le32 *ir_header;
2529 void *p;
2530
2531 for (pd = d; pd <= last; pd++)
2532 if (pd->transfer_status)
2533 break;
2534 if (pd > last)
2535 /* Descriptor(s) not done yet, stop iteration */
2536 return 0;
2537
2538 p = last + 1;
2539 copy_iso_headers(ctx, p);
2540
2541 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2542 ir_header = (__le32 *) p;
2543 ctx->base.callback.sc(&ctx->base,
2544 le32_to_cpu(ir_header[0]) & 0xffff,
2545 ctx->header_length, ctx->header,
2546 ctx->base.callback_data);
2547 ctx->header_length = 0;
2548 }
2549
2550 return 1;
2551 }
2552
2553 /* d == last because each descriptor block is only a single descriptor. */
2554 static int handle_ir_buffer_fill(struct context *context,
2555 struct descriptor *d,
2556 struct descriptor *last)
2557 {
2558 struct iso_context *ctx =
2559 container_of(context, struct iso_context, context);
2560
2561 if (last->res_count != 0)
2562 /* Descriptor(s) not done yet, stop iteration */
2563 return 0;
2564
2565 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
2566 ctx->base.callback.mc(&ctx->base,
2567 le32_to_cpu(last->data_address) +
2568 le16_to_cpu(last->req_count),
2569 ctx->base.callback_data);
2570
2571 return 1;
2572 }
2573
2574 static int handle_it_packet(struct context *context,
2575 struct descriptor *d,
2576 struct descriptor *last)
2577 {
2578 struct iso_context *ctx =
2579 container_of(context, struct iso_context, context);
2580 int i;
2581 struct descriptor *pd;
2582
2583 for (pd = d; pd <= last; pd++)
2584 if (pd->transfer_status)
2585 break;
2586 if (pd > last)
2587 /* Descriptor(s) not done yet, stop iteration */
2588 return 0;
2589
2590 i = ctx->header_length;
2591 if (i + 4 < PAGE_SIZE) {
2592 /* Present this value as big-endian to match the receive code */
2593 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2594 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2595 le16_to_cpu(pd->res_count));
2596 ctx->header_length += 4;
2597 }
2598 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2599 ctx->base.callback.sc(&ctx->base, le16_to_cpu(last->res_count),
2600 ctx->header_length, ctx->header,
2601 ctx->base.callback_data);
2602 ctx->header_length = 0;
2603 }
2604 return 1;
2605 }
2606
2607 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2608 {
2609 u32 hi = channels >> 32, lo = channels;
2610
2611 reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2612 reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2613 reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2614 reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2615 mmiowb();
2616 ohci->mc_channels = channels;
2617 }
2618
2619 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2620 int type, int channel, size_t header_size)
2621 {
2622 struct fw_ohci *ohci = fw_ohci(card);
2623 struct iso_context *uninitialized_var(ctx);
2624 descriptor_callback_t uninitialized_var(callback);
2625 u64 *uninitialized_var(channels);
2626 u32 *uninitialized_var(mask), uninitialized_var(regs);
2627 unsigned long flags;
2628 int index, ret = -EBUSY;
2629
2630 spin_lock_irqsave(&ohci->lock, flags);
2631
2632 switch (type) {
2633 case FW_ISO_CONTEXT_TRANSMIT:
2634 mask = &ohci->it_context_mask;
2635 callback = handle_it_packet;
2636 index = ffs(*mask) - 1;
2637 if (index >= 0) {
2638 *mask &= ~(1 << index);
2639 regs = OHCI1394_IsoXmitContextBase(index);
2640 ctx = &ohci->it_context_list[index];
2641 }
2642 break;
2643
2644 case FW_ISO_CONTEXT_RECEIVE:
2645 channels = &ohci->ir_context_channels;
2646 mask = &ohci->ir_context_mask;
2647 callback = handle_ir_packet_per_buffer;
2648 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2649 if (index >= 0) {
2650 *channels &= ~(1ULL << channel);
2651 *mask &= ~(1 << index);
2652 regs = OHCI1394_IsoRcvContextBase(index);
2653 ctx = &ohci->ir_context_list[index];
2654 }
2655 break;
2656
2657 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2658 mask = &ohci->ir_context_mask;
2659 callback = handle_ir_buffer_fill;
2660 index = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2661 if (index >= 0) {
2662 ohci->mc_allocated = true;
2663 *mask &= ~(1 << index);
2664 regs = OHCI1394_IsoRcvContextBase(index);
2665 ctx = &ohci->ir_context_list[index];
2666 }
2667 break;
2668
2669 default:
2670 index = -1;
2671 ret = -ENOSYS;
2672 }
2673
2674 spin_unlock_irqrestore(&ohci->lock, flags);
2675
2676 if (index < 0)
2677 return ERR_PTR(ret);
2678
2679 memset(ctx, 0, sizeof(*ctx));
2680 ctx->header_length = 0;
2681 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2682 if (ctx->header == NULL) {
2683 ret = -ENOMEM;
2684 goto out;
2685 }
2686 ret = context_init(&ctx->context, ohci, regs, callback);
2687 if (ret < 0)
2688 goto out_with_header;
2689
2690 if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2691 set_multichannel_mask(ohci, 0);
2692
2693 return &ctx->base;
2694
2695 out_with_header:
2696 free_page((unsigned long)ctx->header);
2697 out:
2698 spin_lock_irqsave(&ohci->lock, flags);
2699
2700 switch (type) {
2701 case FW_ISO_CONTEXT_RECEIVE:
2702 *channels |= 1ULL << channel;
2703 break;
2704
2705 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2706 ohci->mc_allocated = false;
2707 break;
2708 }
2709 *mask |= 1 << index;
2710
2711 spin_unlock_irqrestore(&ohci->lock, flags);
2712
2713 return ERR_PTR(ret);
2714 }
2715
2716 static int ohci_start_iso(struct fw_iso_context *base,
2717 s32 cycle, u32 sync, u32 tags)
2718 {
2719 struct iso_context *ctx = container_of(base, struct iso_context, base);
2720 struct fw_ohci *ohci = ctx->context.ohci;
2721 u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2722 int index;
2723
2724 /* the controller cannot start without any queued packets */
2725 if (ctx->context.last->branch_address == 0)
2726 return -ENODATA;
2727
2728 switch (ctx->base.type) {
2729 case FW_ISO_CONTEXT_TRANSMIT:
2730 index = ctx - ohci->it_context_list;
2731 match = 0;
2732 if (cycle >= 0)
2733 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2734 (cycle & 0x7fff) << 16;
2735
2736 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2737 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2738 context_run(&ctx->context, match);
2739 break;
2740
2741 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2742 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2743 /* fall through */
2744 case FW_ISO_CONTEXT_RECEIVE:
2745 index = ctx - ohci->ir_context_list;
2746 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2747 if (cycle >= 0) {
2748 match |= (cycle & 0x07fff) << 12;
2749 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2750 }
2751
2752 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2753 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2754 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2755 context_run(&ctx->context, control);
2756
2757 ctx->sync = sync;
2758 ctx->tags = tags;
2759
2760 break;
2761 }
2762
2763 return 0;
2764 }
2765
2766 static int ohci_stop_iso(struct fw_iso_context *base)
2767 {
2768 struct fw_ohci *ohci = fw_ohci(base->card);
2769 struct iso_context *ctx = container_of(base, struct iso_context, base);
2770 int index;
2771
2772 switch (ctx->base.type) {
2773 case FW_ISO_CONTEXT_TRANSMIT:
2774 index = ctx - ohci->it_context_list;
2775 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2776 break;
2777
2778 case FW_ISO_CONTEXT_RECEIVE:
2779 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2780 index = ctx - ohci->ir_context_list;
2781 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2782 break;
2783 }
2784 flush_writes(ohci);
2785 context_stop(&ctx->context);
2786 tasklet_kill(&ctx->context.tasklet);
2787
2788 return 0;
2789 }
2790
2791 static void ohci_free_iso_context(struct fw_iso_context *base)
2792 {
2793 struct fw_ohci *ohci = fw_ohci(base->card);
2794 struct iso_context *ctx = container_of(base, struct iso_context, base);
2795 unsigned long flags;
2796 int index;
2797
2798 ohci_stop_iso(base);
2799 context_release(&ctx->context);
2800 free_page((unsigned long)ctx->header);
2801
2802 spin_lock_irqsave(&ohci->lock, flags);
2803
2804 switch (base->type) {
2805 case FW_ISO_CONTEXT_TRANSMIT:
2806 index = ctx - ohci->it_context_list;
2807 ohci->it_context_mask |= 1 << index;
2808 break;
2809
2810 case FW_ISO_CONTEXT_RECEIVE:
2811 index = ctx - ohci->ir_context_list;
2812 ohci->ir_context_mask |= 1 << index;
2813 ohci->ir_context_channels |= 1ULL << base->channel;
2814 break;
2815
2816 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2817 index = ctx - ohci->ir_context_list;
2818 ohci->ir_context_mask |= 1 << index;
2819 ohci->ir_context_channels |= ohci->mc_channels;
2820 ohci->mc_channels = 0;
2821 ohci->mc_allocated = false;
2822 break;
2823 }
2824
2825 spin_unlock_irqrestore(&ohci->lock, flags);
2826 }
2827
2828 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
2829 {
2830 struct fw_ohci *ohci = fw_ohci(base->card);
2831 unsigned long flags;
2832 int ret;
2833
2834 switch (base->type) {
2835 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2836
2837 spin_lock_irqsave(&ohci->lock, flags);
2838
2839 /* Don't allow multichannel to grab other contexts' channels. */
2840 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
2841 *channels = ohci->ir_context_channels;
2842 ret = -EBUSY;
2843 } else {
2844 set_multichannel_mask(ohci, *channels);
2845 ret = 0;
2846 }
2847
2848 spin_unlock_irqrestore(&ohci->lock, flags);
2849
2850 break;
2851 default:
2852 ret = -EINVAL;
2853 }
2854
2855 return ret;
2856 }
2857
2858 #ifdef CONFIG_PM
2859 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
2860 {
2861 int i;
2862 struct iso_context *ctx;
2863
2864 for (i = 0 ; i < ohci->n_ir ; i++) {
2865 ctx = &ohci->ir_context_list[i];
2866 if (ctx->context.running)
2867 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2868 }
2869
2870 for (i = 0 ; i < ohci->n_it ; i++) {
2871 ctx = &ohci->it_context_list[i];
2872 if (ctx->context.running)
2873 ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
2874 }
2875 }
2876 #endif
2877
2878 static int queue_iso_transmit(struct iso_context *ctx,
2879 struct fw_iso_packet *packet,
2880 struct fw_iso_buffer *buffer,
2881 unsigned long payload)
2882 {
2883 struct descriptor *d, *last, *pd;
2884 struct fw_iso_packet *p;
2885 __le32 *header;
2886 dma_addr_t d_bus, page_bus;
2887 u32 z, header_z, payload_z, irq;
2888 u32 payload_index, payload_end_index, next_page_index;
2889 int page, end_page, i, length, offset;
2890
2891 p = packet;
2892 payload_index = payload;
2893
2894 if (p->skip)
2895 z = 1;
2896 else
2897 z = 2;
2898 if (p->header_length > 0)
2899 z++;
2900
2901 /* Determine the first page the payload isn't contained in. */
2902 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2903 if (p->payload_length > 0)
2904 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2905 else
2906 payload_z = 0;
2907
2908 z += payload_z;
2909
2910 /* Get header size in number of descriptors. */
2911 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2912
2913 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2914 if (d == NULL)
2915 return -ENOMEM;
2916
2917 if (!p->skip) {
2918 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2919 d[0].req_count = cpu_to_le16(8);
2920 /*
2921 * Link the skip address to this descriptor itself. This causes
2922 * a context to skip a cycle whenever lost cycles or FIFO
2923 * overruns occur, without dropping the data. The application
2924 * should then decide whether this is an error condition or not.
2925 * FIXME: Make the context's cycle-lost behaviour configurable?
2926 */
2927 d[0].branch_address = cpu_to_le32(d_bus | z);
2928
2929 header = (__le32 *) &d[1];
2930 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2931 IT_HEADER_TAG(p->tag) |
2932 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2933 IT_HEADER_CHANNEL(ctx->base.channel) |
2934 IT_HEADER_SPEED(ctx->base.speed));
2935 header[1] =
2936 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2937 p->payload_length));
2938 }
2939
2940 if (p->header_length > 0) {
2941 d[2].req_count = cpu_to_le16(p->header_length);
2942 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2943 memcpy(&d[z], p->header, p->header_length);
2944 }
2945
2946 pd = d + z - payload_z;
2947 payload_end_index = payload_index + p->payload_length;
2948 for (i = 0; i < payload_z; i++) {
2949 page = payload_index >> PAGE_SHIFT;
2950 offset = payload_index & ~PAGE_MASK;
2951 next_page_index = (page + 1) << PAGE_SHIFT;
2952 length =
2953 min(next_page_index, payload_end_index) - payload_index;
2954 pd[i].req_count = cpu_to_le16(length);
2955
2956 page_bus = page_private(buffer->pages[page]);
2957 pd[i].data_address = cpu_to_le32(page_bus + offset);
2958
2959 payload_index += length;
2960 }
2961
2962 if (p->interrupt)
2963 irq = DESCRIPTOR_IRQ_ALWAYS;
2964 else
2965 irq = DESCRIPTOR_NO_IRQ;
2966
2967 last = z == 2 ? d : d + z - 1;
2968 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2969 DESCRIPTOR_STATUS |
2970 DESCRIPTOR_BRANCH_ALWAYS |
2971 irq);
2972
2973 context_append(&ctx->context, d, z, header_z);
2974
2975 return 0;
2976 }
2977
2978 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
2979 struct fw_iso_packet *packet,
2980 struct fw_iso_buffer *buffer,
2981 unsigned long payload)
2982 {
2983 struct descriptor *d, *pd;
2984 dma_addr_t d_bus, page_bus;
2985 u32 z, header_z, rest;
2986 int i, j, length;
2987 int page, offset, packet_count, header_size, payload_per_buffer;
2988
2989 /*
2990 * The OHCI controller puts the isochronous header and trailer in the
2991 * buffer, so we need at least 8 bytes.
2992 */
2993 packet_count = packet->header_length / ctx->base.header_size;
2994 header_size = max(ctx->base.header_size, (size_t)8);
2995
2996 /* Get header size in number of descriptors. */
2997 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2998 page = payload >> PAGE_SHIFT;
2999 offset = payload & ~PAGE_MASK;
3000 payload_per_buffer = packet->payload_length / packet_count;
3001
3002 for (i = 0; i < packet_count; i++) {
3003 /* d points to the header descriptor */
3004 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3005 d = context_get_descriptors(&ctx->context,
3006 z + header_z, &d_bus);
3007 if (d == NULL)
3008 return -ENOMEM;
3009
3010 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
3011 DESCRIPTOR_INPUT_MORE);
3012 if (packet->skip && i == 0)
3013 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3014 d->req_count = cpu_to_le16(header_size);
3015 d->res_count = d->req_count;
3016 d->transfer_status = 0;
3017 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3018
3019 rest = payload_per_buffer;
3020 pd = d;
3021 for (j = 1; j < z; j++) {
3022 pd++;
3023 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3024 DESCRIPTOR_INPUT_MORE);
3025
3026 if (offset + rest < PAGE_SIZE)
3027 length = rest;
3028 else
3029 length = PAGE_SIZE - offset;
3030 pd->req_count = cpu_to_le16(length);
3031 pd->res_count = pd->req_count;
3032 pd->transfer_status = 0;
3033
3034 page_bus = page_private(buffer->pages[page]);
3035 pd->data_address = cpu_to_le32(page_bus + offset);
3036
3037 offset = (offset + length) & ~PAGE_MASK;
3038 rest -= length;
3039 if (offset == 0)
3040 page++;
3041 }
3042 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3043 DESCRIPTOR_INPUT_LAST |
3044 DESCRIPTOR_BRANCH_ALWAYS);
3045 if (packet->interrupt && i == packet_count - 1)
3046 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3047
3048 context_append(&ctx->context, d, z, header_z);
3049 }
3050
3051 return 0;
3052 }
3053
3054 static int queue_iso_buffer_fill(struct iso_context *ctx,
3055 struct fw_iso_packet *packet,
3056 struct fw_iso_buffer *buffer,
3057 unsigned long payload)
3058 {
3059 struct descriptor *d;
3060 dma_addr_t d_bus, page_bus;
3061 int page, offset, rest, z, i, length;
3062
3063 page = payload >> PAGE_SHIFT;
3064 offset = payload & ~PAGE_MASK;
3065 rest = packet->payload_length;
3066
3067 /* We need one descriptor for each page in the buffer. */
3068 z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3069
3070 if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3071 return -EFAULT;
3072
3073 for (i = 0; i < z; i++) {
3074 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3075 if (d == NULL)
3076 return -ENOMEM;
3077
3078 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3079 DESCRIPTOR_BRANCH_ALWAYS);
3080 if (packet->skip && i == 0)
3081 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3082 if (packet->interrupt && i == z - 1)
3083 d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3084
3085 if (offset + rest < PAGE_SIZE)
3086 length = rest;
3087 else
3088 length = PAGE_SIZE - offset;
3089 d->req_count = cpu_to_le16(length);
3090 d->res_count = d->req_count;
3091 d->transfer_status = 0;
3092
3093 page_bus = page_private(buffer->pages[page]);
3094 d->data_address = cpu_to_le32(page_bus + offset);
3095
3096 rest -= length;
3097 offset = 0;
3098 page++;
3099
3100 context_append(&ctx->context, d, 1, 0);
3101 }
3102
3103 return 0;
3104 }
3105
3106 static int ohci_queue_iso(struct fw_iso_context *base,
3107 struct fw_iso_packet *packet,
3108 struct fw_iso_buffer *buffer,
3109 unsigned long payload)
3110 {
3111 struct iso_context *ctx = container_of(base, struct iso_context, base);
3112 unsigned long flags;
3113 int ret = -ENOSYS;
3114
3115 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3116 switch (base->type) {
3117 case FW_ISO_CONTEXT_TRANSMIT:
3118 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3119 break;
3120 case FW_ISO_CONTEXT_RECEIVE:
3121 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3122 break;
3123 case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3124 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3125 break;
3126 }
3127 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3128
3129 return ret;
3130 }
3131
3132 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3133 {
3134 struct context *ctx =
3135 &container_of(base, struct iso_context, base)->context;
3136
3137 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3138 flush_writes(ctx->ohci);
3139 }
3140
3141 static const struct fw_card_driver ohci_driver = {
3142 .enable = ohci_enable,
3143 .read_phy_reg = ohci_read_phy_reg,
3144 .update_phy_reg = ohci_update_phy_reg,
3145 .set_config_rom = ohci_set_config_rom,
3146 .send_request = ohci_send_request,
3147 .send_response = ohci_send_response,
3148 .cancel_packet = ohci_cancel_packet,
3149 .enable_phys_dma = ohci_enable_phys_dma,
3150 .read_csr = ohci_read_csr,
3151 .write_csr = ohci_write_csr,
3152
3153 .allocate_iso_context = ohci_allocate_iso_context,
3154 .free_iso_context = ohci_free_iso_context,
3155 .set_iso_channels = ohci_set_iso_channels,
3156 .queue_iso = ohci_queue_iso,
3157 .flush_queue_iso = ohci_flush_queue_iso,
3158 .start_iso = ohci_start_iso,
3159 .stop_iso = ohci_stop_iso,
3160 };
3161
3162 #ifdef CONFIG_PPC_PMAC
3163 static void pmac_ohci_on(struct pci_dev *dev)
3164 {
3165 if (machine_is(powermac)) {
3166 struct device_node *ofn = pci_device_to_OF_node(dev);
3167
3168 if (ofn) {
3169 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3170 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3171 }
3172 }
3173 }
3174
3175 static void pmac_ohci_off(struct pci_dev *dev)
3176 {
3177 if (machine_is(powermac)) {
3178 struct device_node *ofn = pci_device_to_OF_node(dev);
3179
3180 if (ofn) {
3181 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3182 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3183 }
3184 }
3185 }
3186 #else
3187 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3188 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3189 #endif /* CONFIG_PPC_PMAC */
3190
3191 static int __devinit pci_probe(struct pci_dev *dev,
3192 const struct pci_device_id *ent)
3193 {
3194 struct fw_ohci *ohci;
3195 u32 bus_options, max_receive, link_speed, version;
3196 u64 guid;
3197 int i, err;
3198 size_t size;
3199
3200 if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3201 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3202 return -ENOSYS;
3203 }
3204
3205 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3206 if (ohci == NULL) {
3207 err = -ENOMEM;
3208 goto fail;
3209 }
3210
3211 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3212
3213 pmac_ohci_on(dev);
3214
3215 err = pci_enable_device(dev);
3216 if (err) {
3217 fw_error("Failed to enable OHCI hardware\n");
3218 goto fail_free;
3219 }
3220
3221 pci_set_master(dev);
3222 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3223 pci_set_drvdata(dev, ohci);
3224
3225 spin_lock_init(&ohci->lock);
3226 mutex_init(&ohci->phy_reg_mutex);
3227
3228 tasklet_init(&ohci->bus_reset_tasklet,
3229 bus_reset_tasklet, (unsigned long)ohci);
3230
3231 err = pci_request_region(dev, 0, ohci_driver_name);
3232 if (err) {
3233 fw_error("MMIO resource unavailable\n");
3234 goto fail_disable;
3235 }
3236
3237 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3238 if (ohci->registers == NULL) {
3239 fw_error("Failed to remap registers\n");
3240 err = -ENXIO;
3241 goto fail_iomem;
3242 }
3243
3244 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3245 if ((ohci_quirks[i].vendor == dev->vendor) &&
3246 (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3247 ohci_quirks[i].device == dev->device) &&
3248 (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3249 ohci_quirks[i].revision >= dev->revision)) {
3250 ohci->quirks = ohci_quirks[i].flags;
3251 break;
3252 }
3253 if (param_quirks)
3254 ohci->quirks = param_quirks;
3255
3256 /*
3257 * Because dma_alloc_coherent() allocates at least one page,
3258 * we save space by using a common buffer for the AR request/
3259 * response descriptors and the self IDs buffer.
3260 */
3261 BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3262 BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3263 ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3264 PAGE_SIZE,
3265 &ohci->misc_buffer_bus,
3266 GFP_KERNEL);
3267 if (!ohci->misc_buffer) {
3268 err = -ENOMEM;
3269 goto fail_iounmap;
3270 }
3271
3272 err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3273 OHCI1394_AsReqRcvContextControlSet);
3274 if (err < 0)
3275 goto fail_misc_buf;
3276
3277 err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3278 OHCI1394_AsRspRcvContextControlSet);
3279 if (err < 0)
3280 goto fail_arreq_ctx;
3281
3282 err = context_init(&ohci->at_request_ctx, ohci,
3283 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3284 if (err < 0)
3285 goto fail_arrsp_ctx;
3286
3287 err = context_init(&ohci->at_response_ctx, ohci,
3288 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3289 if (err < 0)
3290 goto fail_atreq_ctx;
3291
3292 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3293 ohci->ir_context_channels = ~0ULL;
3294 ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3295 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3296 ohci->ir_context_mask = ohci->ir_context_support;
3297 ohci->n_ir = hweight32(ohci->ir_context_mask);
3298 size = sizeof(struct iso_context) * ohci->n_ir;
3299 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3300
3301 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3302 ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3303 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3304 ohci->it_context_mask = ohci->it_context_support;
3305 ohci->n_it = hweight32(ohci->it_context_mask);
3306 size = sizeof(struct iso_context) * ohci->n_it;
3307 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3308
3309 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3310 err = -ENOMEM;
3311 goto fail_contexts;
3312 }
3313
3314 ohci->self_id_cpu = ohci->misc_buffer + PAGE_SIZE/2;
3315 ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3316
3317 bus_options = reg_read(ohci, OHCI1394_BusOptions);
3318 max_receive = (bus_options >> 12) & 0xf;
3319 link_speed = bus_options & 0x7;
3320 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3321 reg_read(ohci, OHCI1394_GUIDLo);
3322
3323 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3324 if (err)
3325 goto fail_contexts;
3326
3327 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3328 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
3329 "%d IR + %d IT contexts, quirks 0x%x\n",
3330 dev_name(&dev->dev), version >> 16, version & 0xff,
3331 ohci->n_ir, ohci->n_it, ohci->quirks);
3332
3333 return 0;
3334
3335 fail_contexts:
3336 kfree(ohci->ir_context_list);
3337 kfree(ohci->it_context_list);
3338 context_release(&ohci->at_response_ctx);
3339 fail_atreq_ctx:
3340 context_release(&ohci->at_request_ctx);
3341 fail_arrsp_ctx:
3342 ar_context_release(&ohci->ar_response_ctx);
3343 fail_arreq_ctx:
3344 ar_context_release(&ohci->ar_request_ctx);
3345 fail_misc_buf:
3346 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3347 ohci->misc_buffer, ohci->misc_buffer_bus);
3348 fail_iounmap:
3349 pci_iounmap(dev, ohci->registers);
3350 fail_iomem:
3351 pci_release_region(dev, 0);
3352 fail_disable:
3353 pci_disable_device(dev);
3354 fail_free:
3355 kfree(ohci);
3356 pmac_ohci_off(dev);
3357 fail:
3358 if (err == -ENOMEM)
3359 fw_error("Out of memory\n");
3360
3361 return err;
3362 }
3363
3364 static void pci_remove(struct pci_dev *dev)
3365 {
3366 struct fw_ohci *ohci;
3367
3368 ohci = pci_get_drvdata(dev);
3369 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3370 flush_writes(ohci);
3371 fw_core_remove_card(&ohci->card);
3372
3373 /*
3374 * FIXME: Fail all pending packets here, now that the upper
3375 * layers can't queue any more.
3376 */
3377
3378 software_reset(ohci);
3379 free_irq(dev->irq, ohci);
3380
3381 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3382 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3383 ohci->next_config_rom, ohci->next_config_rom_bus);
3384 if (ohci->config_rom)
3385 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3386 ohci->config_rom, ohci->config_rom_bus);
3387 ar_context_release(&ohci->ar_request_ctx);
3388 ar_context_release(&ohci->ar_response_ctx);
3389 dma_free_coherent(ohci->card.device, PAGE_SIZE,
3390 ohci->misc_buffer, ohci->misc_buffer_bus);
3391 context_release(&ohci->at_request_ctx);
3392 context_release(&ohci->at_response_ctx);
3393 kfree(ohci->it_context_list);
3394 kfree(ohci->ir_context_list);
3395 pci_disable_msi(dev);
3396 pci_iounmap(dev, ohci->registers);
3397 pci_release_region(dev, 0);
3398 pci_disable_device(dev);
3399 kfree(ohci);
3400 pmac_ohci_off(dev);
3401
3402 fw_notify("Removed fw-ohci device.\n");
3403 }
3404
3405 #ifdef CONFIG_PM
3406 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3407 {
3408 struct fw_ohci *ohci = pci_get_drvdata(dev);
3409 int err;
3410
3411 software_reset(ohci);
3412 free_irq(dev->irq, ohci);
3413 pci_disable_msi(dev);
3414 err = pci_save_state(dev);
3415 if (err) {
3416 fw_error("pci_save_state failed\n");
3417 return err;
3418 }
3419 err = pci_set_power_state(dev, pci_choose_state(dev, state));
3420 if (err)
3421 fw_error("pci_set_power_state failed with %d\n", err);
3422 pmac_ohci_off(dev);
3423
3424 return 0;
3425 }
3426
3427 static int pci_resume(struct pci_dev *dev)
3428 {
3429 struct fw_ohci *ohci = pci_get_drvdata(dev);
3430 int err;
3431
3432 pmac_ohci_on(dev);
3433 pci_set_power_state(dev, PCI_D0);
3434 pci_restore_state(dev);
3435 err = pci_enable_device(dev);
3436 if (err) {
3437 fw_error("pci_enable_device failed\n");
3438 return err;
3439 }
3440
3441 /* Some systems don't setup GUID register on resume from ram */
3442 if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3443 !reg_read(ohci, OHCI1394_GUIDHi)) {
3444 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3445 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3446 }
3447
3448 err = ohci_enable(&ohci->card, NULL, 0);
3449 if (err)
3450 return err;
3451
3452 ohci_resume_iso_dma(ohci);
3453
3454 return 0;
3455 }
3456 #endif
3457
3458 static const struct pci_device_id pci_table[] = {
3459 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3460 { }
3461 };
3462
3463 MODULE_DEVICE_TABLE(pci, pci_table);
3464
3465 static struct pci_driver fw_ohci_pci_driver = {
3466 .name = ohci_driver_name,
3467 .id_table = pci_table,
3468 .probe = pci_probe,
3469 .remove = pci_remove,
3470 #ifdef CONFIG_PM
3471 .resume = pci_resume,
3472 .suspend = pci_suspend,
3473 #endif
3474 };
3475
3476 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3477 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3478 MODULE_LICENSE("GPL");
3479
3480 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3481 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3482 MODULE_ALIAS("ohci1394");
3483 #endif
3484
3485 static int __init fw_ohci_init(void)
3486 {
3487 return pci_register_driver(&fw_ohci_pci_driver);
3488 }
3489
3490 static void __exit fw_ohci_cleanup(void)
3491 {
3492 pci_unregister_driver(&fw_ohci_pci_driver);
3493 }
3494
3495 module_init(fw_ohci_init);
3496 module_exit(fw_ohci_cleanup);
Linux with added FPC-III support