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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / gpio / gpio-omap.c
blob35bebde23e835c7674aaaa5e6bbf0e998ab0fd32
1 /*
2 * Support functions for OMAP GPIO
3 *
4 * Copyright (C) 2003-2005 Nokia Corporation
5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/slab.h>
23 #include <linux/pm_runtime.h>
24
25 #include <mach/hardware.h>
26 #include <asm/irq.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
30
31 struct gpio_bank {
32 unsigned long pbase;
33 void __iomem *base;
34 u16 irq;
35 u16 virtual_irq_start;
36 int method;
37 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
38 u32 suspend_wakeup;
39 u32 saved_wakeup;
40 #endif
41 u32 non_wakeup_gpios;
42 u32 enabled_non_wakeup_gpios;
43
44 u32 saved_datain;
45 u32 saved_fallingdetect;
46 u32 saved_risingdetect;
47 u32 level_mask;
48 u32 toggle_mask;
49 spinlock_t lock;
50 struct gpio_chip chip;
51 struct clk *dbck;
52 u32 mod_usage;
53 u32 dbck_enable_mask;
54 struct device *dev;
55 bool dbck_flag;
56 int stride;
57 };
58
59 #ifdef CONFIG_ARCH_OMAP3
60 struct omap3_gpio_regs {
61 u32 irqenable1;
62 u32 irqenable2;
63 u32 wake_en;
64 u32 ctrl;
65 u32 oe;
66 u32 leveldetect0;
67 u32 leveldetect1;
68 u32 risingdetect;
69 u32 fallingdetect;
70 u32 dataout;
71 };
72
73 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
74 #endif
75
76 /*
77 * TODO: Cleanup gpio_bank usage as it is having information
78 * related to all instances of the device
79 */
80 static struct gpio_bank *gpio_bank;
81
82 static int bank_width;
83
84 /* TODO: Analyze removing gpio_bank_count usage from driver code */
85 int gpio_bank_count;
86
87 static inline struct gpio_bank *get_gpio_bank(int gpio)
88 {
89 if (cpu_is_omap15xx()) {
90 if (OMAP_GPIO_IS_MPUIO(gpio))
91 return &gpio_bank[0];
92 return &gpio_bank[1];
93 }
94 if (cpu_is_omap16xx()) {
95 if (OMAP_GPIO_IS_MPUIO(gpio))
96 return &gpio_bank[0];
97 return &gpio_bank[1 + (gpio >> 4)];
98 }
99 if (cpu_is_omap7xx()) {
100 if (OMAP_GPIO_IS_MPUIO(gpio))
101 return &gpio_bank[0];
102 return &gpio_bank[1 + (gpio >> 5)];
103 }
104 if (cpu_is_omap24xx())
105 return &gpio_bank[gpio >> 5];
106 if (cpu_is_omap34xx() || cpu_is_omap44xx())
107 return &gpio_bank[gpio >> 5];
108 BUG();
109 return NULL;
110 }
111
112 static inline int get_gpio_index(int gpio)
113 {
114 if (cpu_is_omap7xx())
115 return gpio & 0x1f;
116 if (cpu_is_omap24xx())
117 return gpio & 0x1f;
118 if (cpu_is_omap34xx() || cpu_is_omap44xx())
119 return gpio & 0x1f;
120 return gpio & 0x0f;
121 }
122
123 static inline int gpio_valid(int gpio)
124 {
125 if (gpio < 0)
126 return -1;
127 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
128 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
129 return -1;
130 return 0;
131 }
132 if (cpu_is_omap15xx() && gpio < 16)
133 return 0;
134 if ((cpu_is_omap16xx()) && gpio < 64)
135 return 0;
136 if (cpu_is_omap7xx() && gpio < 192)
137 return 0;
138 if (cpu_is_omap2420() && gpio < 128)
139 return 0;
140 if (cpu_is_omap2430() && gpio < 160)
141 return 0;
142 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
143 return 0;
144 return -1;
145 }
146
147 static int check_gpio(int gpio)
148 {
149 if (unlikely(gpio_valid(gpio) < 0)) {
150 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
151 dump_stack();
152 return -1;
153 }
154 return 0;
155 }
156
157 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
158 {
159 void __iomem *reg = bank->base;
160 u32 l;
161
162 switch (bank->method) {
163 #ifdef CONFIG_ARCH_OMAP1
164 case METHOD_MPUIO:
165 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
166 break;
167 #endif
168 #ifdef CONFIG_ARCH_OMAP15XX
169 case METHOD_GPIO_1510:
170 reg += OMAP1510_GPIO_DIR_CONTROL;
171 break;
172 #endif
173 #ifdef CONFIG_ARCH_OMAP16XX
174 case METHOD_GPIO_1610:
175 reg += OMAP1610_GPIO_DIRECTION;
176 break;
177 #endif
178 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
179 case METHOD_GPIO_7XX:
180 reg += OMAP7XX_GPIO_DIR_CONTROL;
181 break;
182 #endif
183 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
184 case METHOD_GPIO_24XX:
185 reg += OMAP24XX_GPIO_OE;
186 break;
187 #endif
188 #if defined(CONFIG_ARCH_OMAP4)
189 case METHOD_GPIO_44XX:
190 reg += OMAP4_GPIO_OE;
191 break;
192 #endif
193 default:
194 WARN_ON(1);
195 return;
196 }
197 l = __raw_readl(reg);
198 if (is_input)
199 l |= 1 << gpio;
200 else
201 l &= ~(1 << gpio);
202 __raw_writel(l, reg);
203 }
204
205 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
206 {
207 void __iomem *reg = bank->base;
208 u32 l = 0;
209
210 switch (bank->method) {
211 #ifdef CONFIG_ARCH_OMAP1
212 case METHOD_MPUIO:
213 reg += OMAP_MPUIO_OUTPUT / bank->stride;
214 l = __raw_readl(reg);
215 if (enable)
216 l |= 1 << gpio;
217 else
218 l &= ~(1 << gpio);
219 break;
220 #endif
221 #ifdef CONFIG_ARCH_OMAP15XX
222 case METHOD_GPIO_1510:
223 reg += OMAP1510_GPIO_DATA_OUTPUT;
224 l = __raw_readl(reg);
225 if (enable)
226 l |= 1 << gpio;
227 else
228 l &= ~(1 << gpio);
229 break;
230 #endif
231 #ifdef CONFIG_ARCH_OMAP16XX
232 case METHOD_GPIO_1610:
233 if (enable)
234 reg += OMAP1610_GPIO_SET_DATAOUT;
235 else
236 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
237 l = 1 << gpio;
238 break;
239 #endif
240 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
241 case METHOD_GPIO_7XX:
242 reg += OMAP7XX_GPIO_DATA_OUTPUT;
243 l = __raw_readl(reg);
244 if (enable)
245 l |= 1 << gpio;
246 else
247 l &= ~(1 << gpio);
248 break;
249 #endif
250 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
251 case METHOD_GPIO_24XX:
252 if (enable)
253 reg += OMAP24XX_GPIO_SETDATAOUT;
254 else
255 reg += OMAP24XX_GPIO_CLEARDATAOUT;
256 l = 1 << gpio;
257 break;
258 #endif
259 #ifdef CONFIG_ARCH_OMAP4
260 case METHOD_GPIO_44XX:
261 if (enable)
262 reg += OMAP4_GPIO_SETDATAOUT;
263 else
264 reg += OMAP4_GPIO_CLEARDATAOUT;
265 l = 1 << gpio;
266 break;
267 #endif
268 default:
269 WARN_ON(1);
270 return;
271 }
272 __raw_writel(l, reg);
273 }
274
275 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
276 {
277 void __iomem *reg;
278
279 if (check_gpio(gpio) < 0)
280 return -EINVAL;
281 reg = bank->base;
282 switch (bank->method) {
283 #ifdef CONFIG_ARCH_OMAP1
284 case METHOD_MPUIO:
285 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
286 break;
287 #endif
288 #ifdef CONFIG_ARCH_OMAP15XX
289 case METHOD_GPIO_1510:
290 reg += OMAP1510_GPIO_DATA_INPUT;
291 break;
292 #endif
293 #ifdef CONFIG_ARCH_OMAP16XX
294 case METHOD_GPIO_1610:
295 reg += OMAP1610_GPIO_DATAIN;
296 break;
297 #endif
298 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
299 case METHOD_GPIO_7XX:
300 reg += OMAP7XX_GPIO_DATA_INPUT;
301 break;
302 #endif
303 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
304 case METHOD_GPIO_24XX:
305 reg += OMAP24XX_GPIO_DATAIN;
306 break;
307 #endif
308 #ifdef CONFIG_ARCH_OMAP4
309 case METHOD_GPIO_44XX:
310 reg += OMAP4_GPIO_DATAIN;
311 break;
312 #endif
313 default:
314 return -EINVAL;
315 }
316 return (__raw_readl(reg)
317 & (1 << get_gpio_index(gpio))) != 0;
318 }
319
320 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
321 {
322 void __iomem *reg;
323
324 if (check_gpio(gpio) < 0)
325 return -EINVAL;
326 reg = bank->base;
327
328 switch (bank->method) {
329 #ifdef CONFIG_ARCH_OMAP1
330 case METHOD_MPUIO:
331 reg += OMAP_MPUIO_OUTPUT / bank->stride;
332 break;
333 #endif
334 #ifdef CONFIG_ARCH_OMAP15XX
335 case METHOD_GPIO_1510:
336 reg += OMAP1510_GPIO_DATA_OUTPUT;
337 break;
338 #endif
339 #ifdef CONFIG_ARCH_OMAP16XX
340 case METHOD_GPIO_1610:
341 reg += OMAP1610_GPIO_DATAOUT;
342 break;
343 #endif
344 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
345 case METHOD_GPIO_7XX:
346 reg += OMAP7XX_GPIO_DATA_OUTPUT;
347 break;
348 #endif
349 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
350 case METHOD_GPIO_24XX:
351 reg += OMAP24XX_GPIO_DATAOUT;
352 break;
353 #endif
354 #ifdef CONFIG_ARCH_OMAP4
355 case METHOD_GPIO_44XX:
356 reg += OMAP4_GPIO_DATAOUT;
357 break;
358 #endif
359 default:
360 return -EINVAL;
361 }
362
363 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
364 }
365
366 #define MOD_REG_BIT(reg, bit_mask, set) \
367 do { \
368 int l = __raw_readl(base + reg); \
369 if (set) l |= bit_mask; \
370 else l &= ~bit_mask; \
371 __raw_writel(l, base + reg); \
372 } while(0)
373
374 /**
375 * _set_gpio_debounce - low level gpio debounce time
376 * @bank: the gpio bank we're acting upon
377 * @gpio: the gpio number on this @gpio
378 * @debounce: debounce time to use
379 *
380 * OMAP's debounce time is in 31us steps so we need
381 * to convert and round up to the closest unit.
382 */
383 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
384 unsigned debounce)
385 {
386 void __iomem *reg = bank->base;
387 u32 val;
388 u32 l;
389
390 if (!bank->dbck_flag)
391 return;
392
393 if (debounce < 32)
394 debounce = 0x01;
395 else if (debounce > 7936)
396 debounce = 0xff;
397 else
398 debounce = (debounce / 0x1f) - 1;
399
400 l = 1 << get_gpio_index(gpio);
401
402 if (bank->method == METHOD_GPIO_44XX)
403 reg += OMAP4_GPIO_DEBOUNCINGTIME;
404 else
405 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
406
407 __raw_writel(debounce, reg);
408
409 reg = bank->base;
410 if (bank->method == METHOD_GPIO_44XX)
411 reg += OMAP4_GPIO_DEBOUNCENABLE;
412 else
413 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
414
415 val = __raw_readl(reg);
416
417 if (debounce) {
418 val |= l;
419 clk_enable(bank->dbck);
420 } else {
421 val &= ~l;
422 clk_disable(bank->dbck);
423 }
424 bank->dbck_enable_mask = val;
425
426 __raw_writel(val, reg);
427 }
428
429 #ifdef CONFIG_ARCH_OMAP2PLUS
430 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
431 int trigger)
432 {
433 void __iomem *base = bank->base;
434 u32 gpio_bit = 1 << gpio;
435
436 if (cpu_is_omap44xx()) {
437 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
438 trigger & IRQ_TYPE_LEVEL_LOW);
439 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
440 trigger & IRQ_TYPE_LEVEL_HIGH);
441 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
442 trigger & IRQ_TYPE_EDGE_RISING);
443 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
444 trigger & IRQ_TYPE_EDGE_FALLING);
445 } else {
446 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
447 trigger & IRQ_TYPE_LEVEL_LOW);
448 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
449 trigger & IRQ_TYPE_LEVEL_HIGH);
450 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
451 trigger & IRQ_TYPE_EDGE_RISING);
452 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
453 trigger & IRQ_TYPE_EDGE_FALLING);
454 }
455 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
456 if (cpu_is_omap44xx()) {
457 MOD_REG_BIT(OMAP4_GPIO_IRQWAKEN0, gpio_bit,
458 trigger != 0);
459 } else {
460 /*
461 * GPIO wakeup request can only be generated on edge
462 * transitions
463 */
464 if (trigger & IRQ_TYPE_EDGE_BOTH)
465 __raw_writel(1 << gpio, bank->base
466 + OMAP24XX_GPIO_SETWKUENA);
467 else
468 __raw_writel(1 << gpio, bank->base
469 + OMAP24XX_GPIO_CLEARWKUENA);
470 }
471 }
472 /* This part needs to be executed always for OMAP{34xx, 44xx} */
473 if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
474 (bank->non_wakeup_gpios & gpio_bit)) {
475 /*
476 * Log the edge gpio and manually trigger the IRQ
477 * after resume if the input level changes
478 * to avoid irq lost during PER RET/OFF mode
479 * Applies for omap2 non-wakeup gpio and all omap3 gpios
480 */
481 if (trigger & IRQ_TYPE_EDGE_BOTH)
482 bank->enabled_non_wakeup_gpios |= gpio_bit;
483 else
484 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
485 }
486
487 if (cpu_is_omap44xx()) {
488 bank->level_mask =
489 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
490 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
491 } else {
492 bank->level_mask =
493 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
494 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
495 }
496 }
497 #endif
498
499 #ifdef CONFIG_ARCH_OMAP1
500 /*
501 * This only applies to chips that can't do both rising and falling edge
502 * detection at once. For all other chips, this function is a noop.
503 */
504 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
505 {
506 void __iomem *reg = bank->base;
507 u32 l = 0;
508
509 switch (bank->method) {
510 case METHOD_MPUIO:
511 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
512 break;
513 #ifdef CONFIG_ARCH_OMAP15XX
514 case METHOD_GPIO_1510:
515 reg += OMAP1510_GPIO_INT_CONTROL;
516 break;
517 #endif
518 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
519 case METHOD_GPIO_7XX:
520 reg += OMAP7XX_GPIO_INT_CONTROL;
521 break;
522 #endif
523 default:
524 return;
525 }
526
527 l = __raw_readl(reg);
528 if ((l >> gpio) & 1)
529 l &= ~(1 << gpio);
530 else
531 l |= 1 << gpio;
532
533 __raw_writel(l, reg);
534 }
535 #endif
536
537 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
538 {
539 void __iomem *reg = bank->base;
540 u32 l = 0;
541
542 switch (bank->method) {
543 #ifdef CONFIG_ARCH_OMAP1
544 case METHOD_MPUIO:
545 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
546 l = __raw_readl(reg);
547 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
548 bank->toggle_mask |= 1 << gpio;
549 if (trigger & IRQ_TYPE_EDGE_RISING)
550 l |= 1 << gpio;
551 else if (trigger & IRQ_TYPE_EDGE_FALLING)
552 l &= ~(1 << gpio);
553 else
554 goto bad;
555 break;
556 #endif
557 #ifdef CONFIG_ARCH_OMAP15XX
558 case METHOD_GPIO_1510:
559 reg += OMAP1510_GPIO_INT_CONTROL;
560 l = __raw_readl(reg);
561 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
562 bank->toggle_mask |= 1 << gpio;
563 if (trigger & IRQ_TYPE_EDGE_RISING)
564 l |= 1 << gpio;
565 else if (trigger & IRQ_TYPE_EDGE_FALLING)
566 l &= ~(1 << gpio);
567 else
568 goto bad;
569 break;
570 #endif
571 #ifdef CONFIG_ARCH_OMAP16XX
572 case METHOD_GPIO_1610:
573 if (gpio & 0x08)
574 reg += OMAP1610_GPIO_EDGE_CTRL2;
575 else
576 reg += OMAP1610_GPIO_EDGE_CTRL1;
577 gpio &= 0x07;
578 l = __raw_readl(reg);
579 l &= ~(3 << (gpio << 1));
580 if (trigger & IRQ_TYPE_EDGE_RISING)
581 l |= 2 << (gpio << 1);
582 if (trigger & IRQ_TYPE_EDGE_FALLING)
583 l |= 1 << (gpio << 1);
584 if (trigger)
585 /* Enable wake-up during idle for dynamic tick */
586 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
587 else
588 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
589 break;
590 #endif
591 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
592 case METHOD_GPIO_7XX:
593 reg += OMAP7XX_GPIO_INT_CONTROL;
594 l = __raw_readl(reg);
595 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
596 bank->toggle_mask |= 1 << gpio;
597 if (trigger & IRQ_TYPE_EDGE_RISING)
598 l |= 1 << gpio;
599 else if (trigger & IRQ_TYPE_EDGE_FALLING)
600 l &= ~(1 << gpio);
601 else
602 goto bad;
603 break;
604 #endif
605 #ifdef CONFIG_ARCH_OMAP2PLUS
606 case METHOD_GPIO_24XX:
607 case METHOD_GPIO_44XX:
608 set_24xx_gpio_triggering(bank, gpio, trigger);
609 return 0;
610 #endif
611 default:
612 goto bad;
613 }
614 __raw_writel(l, reg);
615 return 0;
616 bad:
617 return -EINVAL;
618 }
619
620 static int gpio_irq_type(struct irq_data *d, unsigned type)
621 {
622 struct gpio_bank *bank;
623 unsigned gpio;
624 int retval;
625 unsigned long flags;
626
627 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
628 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
629 else
630 gpio = d->irq - IH_GPIO_BASE;
631
632 if (check_gpio(gpio) < 0)
633 return -EINVAL;
634
635 if (type & ~IRQ_TYPE_SENSE_MASK)
636 return -EINVAL;
637
638 /* OMAP1 allows only only edge triggering */
639 if (!cpu_class_is_omap2()
640 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
641 return -EINVAL;
642
643 bank = irq_data_get_irq_chip_data(d);
644 spin_lock_irqsave(&bank->lock, flags);
645 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
646 spin_unlock_irqrestore(&bank->lock, flags);
647
648 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
649 __irq_set_handler_locked(d->irq, handle_level_irq);
650 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
651 __irq_set_handler_locked(d->irq, handle_edge_irq);
652
653 return retval;
654 }
655
656 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
657 {
658 void __iomem *reg = bank->base;
659
660 switch (bank->method) {
661 #ifdef CONFIG_ARCH_OMAP1
662 case METHOD_MPUIO:
663 /* MPUIO irqstatus is reset by reading the status register,
664 * so do nothing here */
665 return;
666 #endif
667 #ifdef CONFIG_ARCH_OMAP15XX
668 case METHOD_GPIO_1510:
669 reg += OMAP1510_GPIO_INT_STATUS;
670 break;
671 #endif
672 #ifdef CONFIG_ARCH_OMAP16XX
673 case METHOD_GPIO_1610:
674 reg += OMAP1610_GPIO_IRQSTATUS1;
675 break;
676 #endif
677 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
678 case METHOD_GPIO_7XX:
679 reg += OMAP7XX_GPIO_INT_STATUS;
680 break;
681 #endif
682 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
683 case METHOD_GPIO_24XX:
684 reg += OMAP24XX_GPIO_IRQSTATUS1;
685 break;
686 #endif
687 #if defined(CONFIG_ARCH_OMAP4)
688 case METHOD_GPIO_44XX:
689 reg += OMAP4_GPIO_IRQSTATUS0;
690 break;
691 #endif
692 default:
693 WARN_ON(1);
694 return;
695 }
696 __raw_writel(gpio_mask, reg);
697
698 /* Workaround for clearing DSP GPIO interrupts to allow retention */
699 if (cpu_is_omap24xx() || cpu_is_omap34xx())
700 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
701 else if (cpu_is_omap44xx())
702 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
703
704 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
705 __raw_writel(gpio_mask, reg);
706
707 /* Flush posted write for the irq status to avoid spurious interrupts */
708 __raw_readl(reg);
709 }
710 }
711
712 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
713 {
714 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
715 }
716
717 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
718 {
719 void __iomem *reg = bank->base;
720 int inv = 0;
721 u32 l;
722 u32 mask;
723
724 switch (bank->method) {
725 #ifdef CONFIG_ARCH_OMAP1
726 case METHOD_MPUIO:
727 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
728 mask = 0xffff;
729 inv = 1;
730 break;
731 #endif
732 #ifdef CONFIG_ARCH_OMAP15XX
733 case METHOD_GPIO_1510:
734 reg += OMAP1510_GPIO_INT_MASK;
735 mask = 0xffff;
736 inv = 1;
737 break;
738 #endif
739 #ifdef CONFIG_ARCH_OMAP16XX
740 case METHOD_GPIO_1610:
741 reg += OMAP1610_GPIO_IRQENABLE1;
742 mask = 0xffff;
743 break;
744 #endif
745 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
746 case METHOD_GPIO_7XX:
747 reg += OMAP7XX_GPIO_INT_MASK;
748 mask = 0xffffffff;
749 inv = 1;
750 break;
751 #endif
752 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
753 case METHOD_GPIO_24XX:
754 reg += OMAP24XX_GPIO_IRQENABLE1;
755 mask = 0xffffffff;
756 break;
757 #endif
758 #if defined(CONFIG_ARCH_OMAP4)
759 case METHOD_GPIO_44XX:
760 reg += OMAP4_GPIO_IRQSTATUSSET0;
761 mask = 0xffffffff;
762 break;
763 #endif
764 default:
765 WARN_ON(1);
766 return 0;
767 }
768
769 l = __raw_readl(reg);
770 if (inv)
771 l = ~l;
772 l &= mask;
773 return l;
774 }
775
776 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
777 {
778 void __iomem *reg = bank->base;
779 u32 l;
780
781 switch (bank->method) {
782 #ifdef CONFIG_ARCH_OMAP1
783 case METHOD_MPUIO:
784 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
785 l = __raw_readl(reg);
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
791 #endif
792 #ifdef CONFIG_ARCH_OMAP15XX
793 case METHOD_GPIO_1510:
794 reg += OMAP1510_GPIO_INT_MASK;
795 l = __raw_readl(reg);
796 if (enable)
797 l &= ~(gpio_mask);
798 else
799 l |= gpio_mask;
800 break;
801 #endif
802 #ifdef CONFIG_ARCH_OMAP16XX
803 case METHOD_GPIO_1610:
804 if (enable)
805 reg += OMAP1610_GPIO_SET_IRQENABLE1;
806 else
807 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
808 l = gpio_mask;
809 break;
810 #endif
811 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
812 case METHOD_GPIO_7XX:
813 reg += OMAP7XX_GPIO_INT_MASK;
814 l = __raw_readl(reg);
815 if (enable)
816 l &= ~(gpio_mask);
817 else
818 l |= gpio_mask;
819 break;
820 #endif
821 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
822 case METHOD_GPIO_24XX:
823 if (enable)
824 reg += OMAP24XX_GPIO_SETIRQENABLE1;
825 else
826 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
827 l = gpio_mask;
828 break;
829 #endif
830 #ifdef CONFIG_ARCH_OMAP4
831 case METHOD_GPIO_44XX:
832 if (enable)
833 reg += OMAP4_GPIO_IRQSTATUSSET0;
834 else
835 reg += OMAP4_GPIO_IRQSTATUSCLR0;
836 l = gpio_mask;
837 break;
838 #endif
839 default:
840 WARN_ON(1);
841 return;
842 }
843 __raw_writel(l, reg);
844 }
845
846 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
847 {
848 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
849 }
850
851 /*
852 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
853 * 1510 does not seem to have a wake-up register. If JTAG is connected
854 * to the target, system will wake up always on GPIO events. While
855 * system is running all registered GPIO interrupts need to have wake-up
856 * enabled. When system is suspended, only selected GPIO interrupts need
857 * to have wake-up enabled.
858 */
859 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
860 {
861 unsigned long uninitialized_var(flags);
862
863 switch (bank->method) {
864 #ifdef CONFIG_ARCH_OMAP16XX
865 case METHOD_MPUIO:
866 case METHOD_GPIO_1610:
867 spin_lock_irqsave(&bank->lock, flags);
868 if (enable)
869 bank->suspend_wakeup |= (1 << gpio);
870 else
871 bank->suspend_wakeup &= ~(1 << gpio);
872 spin_unlock_irqrestore(&bank->lock, flags);
873 return 0;
874 #endif
875 #ifdef CONFIG_ARCH_OMAP2PLUS
876 case METHOD_GPIO_24XX:
877 case METHOD_GPIO_44XX:
878 if (bank->non_wakeup_gpios & (1 << gpio)) {
879 printk(KERN_ERR "Unable to modify wakeup on "
880 "non-wakeup GPIO%d\n",
881 (bank - gpio_bank) * 32 + gpio);
882 return -EINVAL;
883 }
884 spin_lock_irqsave(&bank->lock, flags);
885 if (enable)
886 bank->suspend_wakeup |= (1 << gpio);
887 else
888 bank->suspend_wakeup &= ~(1 << gpio);
889 spin_unlock_irqrestore(&bank->lock, flags);
890 return 0;
891 #endif
892 default:
893 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
894 bank->method);
895 return -EINVAL;
896 }
897 }
898
899 static void _reset_gpio(struct gpio_bank *bank, int gpio)
900 {
901 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
902 _set_gpio_irqenable(bank, gpio, 0);
903 _clear_gpio_irqstatus(bank, gpio);
904 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
905 }
906
907 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
908 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
909 {
910 unsigned int gpio = d->irq - IH_GPIO_BASE;
911 struct gpio_bank *bank;
912 int retval;
913
914 if (check_gpio(gpio) < 0)
915 return -ENODEV;
916 bank = irq_data_get_irq_chip_data(d);
917 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
918
919 return retval;
920 }
921
922 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
923 {
924 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
925 unsigned long flags;
926
927 spin_lock_irqsave(&bank->lock, flags);
928
929 /* Set trigger to none. You need to enable the desired trigger with
930 * request_irq() or set_irq_type().
931 */
932 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
933
934 #ifdef CONFIG_ARCH_OMAP15XX
935 if (bank->method == METHOD_GPIO_1510) {
936 void __iomem *reg;
937
938 /* Claim the pin for MPU */
939 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
940 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
941 }
942 #endif
943 if (!cpu_class_is_omap1()) {
944 if (!bank->mod_usage) {
945 void __iomem *reg = bank->base;
946 u32 ctrl;
947
948 if (cpu_is_omap24xx() || cpu_is_omap34xx())
949 reg += OMAP24XX_GPIO_CTRL;
950 else if (cpu_is_omap44xx())
951 reg += OMAP4_GPIO_CTRL;
952 ctrl = __raw_readl(reg);
953 /* Module is enabled, clocks are not gated */
954 ctrl &= 0xFFFFFFFE;
955 __raw_writel(ctrl, reg);
956 }
957 bank->mod_usage |= 1 << offset;
958 }
959 spin_unlock_irqrestore(&bank->lock, flags);
960
961 return 0;
962 }
963
964 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
965 {
966 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
967 unsigned long flags;
968
969 spin_lock_irqsave(&bank->lock, flags);
970 #ifdef CONFIG_ARCH_OMAP16XX
971 if (bank->method == METHOD_GPIO_1610) {
972 /* Disable wake-up during idle for dynamic tick */
973 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
974 __raw_writel(1 << offset, reg);
975 }
976 #endif
977 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
978 if (bank->method == METHOD_GPIO_24XX) {
979 /* Disable wake-up during idle for dynamic tick */
980 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
981 __raw_writel(1 << offset, reg);
982 }
983 #endif
984 #ifdef CONFIG_ARCH_OMAP4
985 if (bank->method == METHOD_GPIO_44XX) {
986 /* Disable wake-up during idle for dynamic tick */
987 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
988 __raw_writel(1 << offset, reg);
989 }
990 #endif
991 if (!cpu_class_is_omap1()) {
992 bank->mod_usage &= ~(1 << offset);
993 if (!bank->mod_usage) {
994 void __iomem *reg = bank->base;
995 u32 ctrl;
996
997 if (cpu_is_omap24xx() || cpu_is_omap34xx())
998 reg += OMAP24XX_GPIO_CTRL;
999 else if (cpu_is_omap44xx())
1000 reg += OMAP4_GPIO_CTRL;
1001 ctrl = __raw_readl(reg);
1002 /* Module is disabled, clocks are gated */
1003 ctrl |= 1;
1004 __raw_writel(ctrl, reg);
1005 }
1006 }
1007 _reset_gpio(bank, bank->chip.base + offset);
1008 spin_unlock_irqrestore(&bank->lock, flags);
1009 }
1010
1011 /*
1012 * We need to unmask the GPIO bank interrupt as soon as possible to
1013 * avoid missing GPIO interrupts for other lines in the bank.
1014 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1015 * in the bank to avoid missing nested interrupts for a GPIO line.
1016 * If we wait to unmask individual GPIO lines in the bank after the
1017 * line's interrupt handler has been run, we may miss some nested
1018 * interrupts.
1019 */
1020 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1021 {
1022 void __iomem *isr_reg = NULL;
1023 u32 isr;
1024 unsigned int gpio_irq, gpio_index;
1025 struct gpio_bank *bank;
1026 u32 retrigger = 0;
1027 int unmasked = 0;
1028 struct irq_chip *chip = irq_desc_get_chip(desc);
1029
1030 chained_irq_enter(chip, desc);
1031
1032 bank = irq_get_handler_data(irq);
1033 #ifdef CONFIG_ARCH_OMAP1
1034 if (bank->method == METHOD_MPUIO)
1035 isr_reg = bank->base +
1036 OMAP_MPUIO_GPIO_INT / bank->stride;
1037 #endif
1038 #ifdef CONFIG_ARCH_OMAP15XX
1039 if (bank->method == METHOD_GPIO_1510)
1040 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1041 #endif
1042 #if defined(CONFIG_ARCH_OMAP16XX)
1043 if (bank->method == METHOD_GPIO_1610)
1044 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1045 #endif
1046 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1047 if (bank->method == METHOD_GPIO_7XX)
1048 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1049 #endif
1050 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1051 if (bank->method == METHOD_GPIO_24XX)
1052 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1053 #endif
1054 #if defined(CONFIG_ARCH_OMAP4)
1055 if (bank->method == METHOD_GPIO_44XX)
1056 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1057 #endif
1058
1059 if (WARN_ON(!isr_reg))
1060 goto exit;
1061
1062 while(1) {
1063 u32 isr_saved, level_mask = 0;
1064 u32 enabled;
1065
1066 enabled = _get_gpio_irqbank_mask(bank);
1067 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1068
1069 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1070 isr &= 0x0000ffff;
1071
1072 if (cpu_class_is_omap2()) {
1073 level_mask = bank->level_mask & enabled;
1074 }
1075
1076 /* clear edge sensitive interrupts before handler(s) are
1077 called so that we don't miss any interrupt occurred while
1078 executing them */
1079 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1080 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1081 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1082
1083 /* if there is only edge sensitive GPIO pin interrupts
1084 configured, we could unmask GPIO bank interrupt immediately */
1085 if (!level_mask && !unmasked) {
1086 unmasked = 1;
1087 chained_irq_exit(chip, desc);
1088 }
1089
1090 isr |= retrigger;
1091 retrigger = 0;
1092 if (!isr)
1093 break;
1094
1095 gpio_irq = bank->virtual_irq_start;
1096 for (; isr != 0; isr >>= 1, gpio_irq++) {
1097 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1098
1099 if (!(isr & 1))
1100 continue;
1101
1102 #ifdef CONFIG_ARCH_OMAP1
1103 /*
1104 * Some chips can't respond to both rising and falling
1105 * at the same time. If this irq was requested with
1106 * both flags, we need to flip the ICR data for the IRQ
1107 * to respond to the IRQ for the opposite direction.
1108 * This will be indicated in the bank toggle_mask.
1109 */
1110 if (bank->toggle_mask & (1 << gpio_index))
1111 _toggle_gpio_edge_triggering(bank, gpio_index);
1112 #endif
1113
1114 generic_handle_irq(gpio_irq);
1115 }
1116 }
1117 /* if bank has any level sensitive GPIO pin interrupt
1118 configured, we must unmask the bank interrupt only after
1119 handler(s) are executed in order to avoid spurious bank
1120 interrupt */
1121 exit:
1122 if (!unmasked)
1123 chained_irq_exit(chip, desc);
1124 }
1125
1126 static void gpio_irq_shutdown(struct irq_data *d)
1127 {
1128 unsigned int gpio = d->irq - IH_GPIO_BASE;
1129 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1130 unsigned long flags;
1131
1132 spin_lock_irqsave(&bank->lock, flags);
1133 _reset_gpio(bank, gpio);
1134 spin_unlock_irqrestore(&bank->lock, flags);
1135 }
1136
1137 static void gpio_ack_irq(struct irq_data *d)
1138 {
1139 unsigned int gpio = d->irq - IH_GPIO_BASE;
1140 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1141
1142 _clear_gpio_irqstatus(bank, gpio);
1143 }
1144
1145 static void gpio_mask_irq(struct irq_data *d)
1146 {
1147 unsigned int gpio = d->irq - IH_GPIO_BASE;
1148 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1149 unsigned long flags;
1150
1151 spin_lock_irqsave(&bank->lock, flags);
1152 _set_gpio_irqenable(bank, gpio, 0);
1153 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1154 spin_unlock_irqrestore(&bank->lock, flags);
1155 }
1156
1157 static void gpio_unmask_irq(struct irq_data *d)
1158 {
1159 unsigned int gpio = d->irq - IH_GPIO_BASE;
1160 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1161 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1162 u32 trigger = irqd_get_trigger_type(d);
1163 unsigned long flags;
1164
1165 spin_lock_irqsave(&bank->lock, flags);
1166 if (trigger)
1167 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1168
1169 /* For level-triggered GPIOs, the clearing must be done after
1170 * the HW source is cleared, thus after the handler has run */
1171 if (bank->level_mask & irq_mask) {
1172 _set_gpio_irqenable(bank, gpio, 0);
1173 _clear_gpio_irqstatus(bank, gpio);
1174 }
1175
1176 _set_gpio_irqenable(bank, gpio, 1);
1177 spin_unlock_irqrestore(&bank->lock, flags);
1178 }
1179
1180 static struct irq_chip gpio_irq_chip = {
1181 .name = "GPIO",
1182 .irq_shutdown = gpio_irq_shutdown,
1183 .irq_ack = gpio_ack_irq,
1184 .irq_mask = gpio_mask_irq,
1185 .irq_unmask = gpio_unmask_irq,
1186 .irq_set_type = gpio_irq_type,
1187 .irq_set_wake = gpio_wake_enable,
1188 };
1189
1190 /*---------------------------------------------------------------------*/
1191
1192 #ifdef CONFIG_ARCH_OMAP1
1193
1194 /* MPUIO uses the always-on 32k clock */
1195
1196 static void mpuio_ack_irq(struct irq_data *d)
1197 {
1198 /* The ISR is reset automatically, so do nothing here. */
1199 }
1200
1201 static void mpuio_mask_irq(struct irq_data *d)
1202 {
1203 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1204 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1205
1206 _set_gpio_irqenable(bank, gpio, 0);
1207 }
1208
1209 static void mpuio_unmask_irq(struct irq_data *d)
1210 {
1211 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1212 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1213
1214 _set_gpio_irqenable(bank, gpio, 1);
1215 }
1216
1217 static struct irq_chip mpuio_irq_chip = {
1218 .name = "MPUIO",
1219 .irq_ack = mpuio_ack_irq,
1220 .irq_mask = mpuio_mask_irq,
1221 .irq_unmask = mpuio_unmask_irq,
1222 .irq_set_type = gpio_irq_type,
1223 #ifdef CONFIG_ARCH_OMAP16XX
1224 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1225 .irq_set_wake = gpio_wake_enable,
1226 #endif
1227 };
1228
1229
1230 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1231
1232
1233 #ifdef CONFIG_ARCH_OMAP16XX
1234
1235 #include <linux/platform_device.h>
1236
1237 static int omap_mpuio_suspend_noirq(struct device *dev)
1238 {
1239 struct platform_device *pdev = to_platform_device(dev);
1240 struct gpio_bank *bank = platform_get_drvdata(pdev);
1241 void __iomem *mask_reg = bank->base +
1242 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1243 unsigned long flags;
1244
1245 spin_lock_irqsave(&bank->lock, flags);
1246 bank->saved_wakeup = __raw_readl(mask_reg);
1247 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1248 spin_unlock_irqrestore(&bank->lock, flags);
1249
1250 return 0;
1251 }
1252
1253 static int omap_mpuio_resume_noirq(struct device *dev)
1254 {
1255 struct platform_device *pdev = to_platform_device(dev);
1256 struct gpio_bank *bank = platform_get_drvdata(pdev);
1257 void __iomem *mask_reg = bank->base +
1258 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1259 unsigned long flags;
1260
1261 spin_lock_irqsave(&bank->lock, flags);
1262 __raw_writel(bank->saved_wakeup, mask_reg);
1263 spin_unlock_irqrestore(&bank->lock, flags);
1264
1265 return 0;
1266 }
1267
1268 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1269 .suspend_noirq = omap_mpuio_suspend_noirq,
1270 .resume_noirq = omap_mpuio_resume_noirq,
1271 };
1272
1273 /* use platform_driver for this. */
1274 static struct platform_driver omap_mpuio_driver = {
1275 .driver = {
1276 .name = "mpuio",
1277 .pm = &omap_mpuio_dev_pm_ops,
1278 },
1279 };
1280
1281 static struct platform_device omap_mpuio_device = {
1282 .name = "mpuio",
1283 .id = -1,
1284 .dev = {
1285 .driver = &omap_mpuio_driver.driver,
1286 }
1287 /* could list the /proc/iomem resources */
1288 };
1289
1290 static inline void mpuio_init(void)
1291 {
1292 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1293 platform_set_drvdata(&omap_mpuio_device, bank);
1294
1295 if (platform_driver_register(&omap_mpuio_driver) == 0)
1296 (void) platform_device_register(&omap_mpuio_device);
1297 }
1298
1299 #else
1300 static inline void mpuio_init(void) {}
1301 #endif /* 16xx */
1302
1303 #else
1304
1305 extern struct irq_chip mpuio_irq_chip;
1306
1307 #define bank_is_mpuio(bank) 0
1308 static inline void mpuio_init(void) {}
1309
1310 #endif
1311
1312 /*---------------------------------------------------------------------*/
1313
1314 /* REVISIT these are stupid implementations! replace by ones that
1315 * don't switch on METHOD_* and which mostly avoid spinlocks
1316 */
1317
1318 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1319 {
1320 struct gpio_bank *bank;
1321 unsigned long flags;
1322
1323 bank = container_of(chip, struct gpio_bank, chip);
1324 spin_lock_irqsave(&bank->lock, flags);
1325 _set_gpio_direction(bank, offset, 1);
1326 spin_unlock_irqrestore(&bank->lock, flags);
1327 return 0;
1328 }
1329
1330 static int gpio_is_input(struct gpio_bank *bank, int mask)
1331 {
1332 void __iomem *reg = bank->base;
1333
1334 switch (bank->method) {
1335 case METHOD_MPUIO:
1336 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1337 break;
1338 case METHOD_GPIO_1510:
1339 reg += OMAP1510_GPIO_DIR_CONTROL;
1340 break;
1341 case METHOD_GPIO_1610:
1342 reg += OMAP1610_GPIO_DIRECTION;
1343 break;
1344 case METHOD_GPIO_7XX:
1345 reg += OMAP7XX_GPIO_DIR_CONTROL;
1346 break;
1347 case METHOD_GPIO_24XX:
1348 reg += OMAP24XX_GPIO_OE;
1349 break;
1350 case METHOD_GPIO_44XX:
1351 reg += OMAP4_GPIO_OE;
1352 break;
1353 default:
1354 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1355 return -EINVAL;
1356 }
1357 return __raw_readl(reg) & mask;
1358 }
1359
1360 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1361 {
1362 struct gpio_bank *bank;
1363 void __iomem *reg;
1364 int gpio;
1365 u32 mask;
1366
1367 gpio = chip->base + offset;
1368 bank = get_gpio_bank(gpio);
1369 reg = bank->base;
1370 mask = 1 << get_gpio_index(gpio);
1371
1372 if (gpio_is_input(bank, mask))
1373 return _get_gpio_datain(bank, gpio);
1374 else
1375 return _get_gpio_dataout(bank, gpio);
1376 }
1377
1378 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1379 {
1380 struct gpio_bank *bank;
1381 unsigned long flags;
1382
1383 bank = container_of(chip, struct gpio_bank, chip);
1384 spin_lock_irqsave(&bank->lock, flags);
1385 _set_gpio_dataout(bank, offset, value);
1386 _set_gpio_direction(bank, offset, 0);
1387 spin_unlock_irqrestore(&bank->lock, flags);
1388 return 0;
1389 }
1390
1391 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1392 unsigned debounce)
1393 {
1394 struct gpio_bank *bank;
1395 unsigned long flags;
1396
1397 bank = container_of(chip, struct gpio_bank, chip);
1398
1399 if (!bank->dbck) {
1400 bank->dbck = clk_get(bank->dev, "dbclk");
1401 if (IS_ERR(bank->dbck))
1402 dev_err(bank->dev, "Could not get gpio dbck\n");
1403 }
1404
1405 spin_lock_irqsave(&bank->lock, flags);
1406 _set_gpio_debounce(bank, offset, debounce);
1407 spin_unlock_irqrestore(&bank->lock, flags);
1408
1409 return 0;
1410 }
1411
1412 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1413 {
1414 struct gpio_bank *bank;
1415 unsigned long flags;
1416
1417 bank = container_of(chip, struct gpio_bank, chip);
1418 spin_lock_irqsave(&bank->lock, flags);
1419 _set_gpio_dataout(bank, offset, value);
1420 spin_unlock_irqrestore(&bank->lock, flags);
1421 }
1422
1423 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1424 {
1425 struct gpio_bank *bank;
1426
1427 bank = container_of(chip, struct gpio_bank, chip);
1428 return bank->virtual_irq_start + offset;
1429 }
1430
1431 /*---------------------------------------------------------------------*/
1432
1433 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1434 {
1435 u32 rev;
1436
1437 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1438 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1439 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1440 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1441 else if (cpu_is_omap44xx())
1442 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1443 else
1444 return;
1445
1446 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1447 (rev >> 4) & 0x0f, rev & 0x0f);
1448 }
1449
1450 /* This lock class tells lockdep that GPIO irqs are in a different
1451 * category than their parents, so it won't report false recursion.
1452 */
1453 static struct lock_class_key gpio_lock_class;
1454
1455 static inline int init_gpio_info(struct platform_device *pdev)
1456 {
1457 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1458 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1459 GFP_KERNEL);
1460 if (!gpio_bank) {
1461 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1462 return -ENOMEM;
1463 }
1464 return 0;
1465 }
1466
1467 /* TODO: Cleanup cpu_is_* checks */
1468 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1469 {
1470 if (cpu_class_is_omap2()) {
1471 if (cpu_is_omap44xx()) {
1472 __raw_writel(0xffffffff, bank->base +
1473 OMAP4_GPIO_IRQSTATUSCLR0);
1474 __raw_writel(0x00000000, bank->base +
1475 OMAP4_GPIO_DEBOUNCENABLE);
1476 /* Initialize interface clk ungated, module enabled */
1477 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1478 } else if (cpu_is_omap34xx()) {
1479 __raw_writel(0x00000000, bank->base +
1480 OMAP24XX_GPIO_IRQENABLE1);
1481 __raw_writel(0xffffffff, bank->base +
1482 OMAP24XX_GPIO_IRQSTATUS1);
1483 __raw_writel(0x00000000, bank->base +
1484 OMAP24XX_GPIO_DEBOUNCE_EN);
1485
1486 /* Initialize interface clk ungated, module enabled */
1487 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1488 } else if (cpu_is_omap24xx()) {
1489 static const u32 non_wakeup_gpios[] = {
1490 0xe203ffc0, 0x08700040
1491 };
1492 if (id < ARRAY_SIZE(non_wakeup_gpios))
1493 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1494 }
1495 } else if (cpu_class_is_omap1()) {
1496 if (bank_is_mpuio(bank))
1497 __raw_writew(0xffff, bank->base +
1498 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1499 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1500 __raw_writew(0xffff, bank->base
1501 + OMAP1510_GPIO_INT_MASK);
1502 __raw_writew(0x0000, bank->base
1503 + OMAP1510_GPIO_INT_STATUS);
1504 }
1505 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1506 __raw_writew(0x0000, bank->base
1507 + OMAP1610_GPIO_IRQENABLE1);
1508 __raw_writew(0xffff, bank->base
1509 + OMAP1610_GPIO_IRQSTATUS1);
1510 __raw_writew(0x0014, bank->base
1511 + OMAP1610_GPIO_SYSCONFIG);
1512
1513 /*
1514 * Enable system clock for GPIO module.
1515 * The CAM_CLK_CTRL *is* really the right place.
1516 */
1517 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1518 ULPD_CAM_CLK_CTRL);
1519 }
1520 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1521 __raw_writel(0xffffffff, bank->base
1522 + OMAP7XX_GPIO_INT_MASK);
1523 __raw_writel(0x00000000, bank->base
1524 + OMAP7XX_GPIO_INT_STATUS);
1525 }
1526 }
1527 }
1528
1529 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1530 {
1531 int j;
1532 static int gpio;
1533
1534 bank->mod_usage = 0;
1535 /*
1536 * REVISIT eventually switch from OMAP-specific gpio structs
1537 * over to the generic ones
1538 */
1539 bank->chip.request = omap_gpio_request;
1540 bank->chip.free = omap_gpio_free;
1541 bank->chip.direction_input = gpio_input;
1542 bank->chip.get = gpio_get;
1543 bank->chip.direction_output = gpio_output;
1544 bank->chip.set_debounce = gpio_debounce;
1545 bank->chip.set = gpio_set;
1546 bank->chip.to_irq = gpio_2irq;
1547 if (bank_is_mpuio(bank)) {
1548 bank->chip.label = "mpuio";
1549 #ifdef CONFIG_ARCH_OMAP16XX
1550 bank->chip.dev = &omap_mpuio_device.dev;
1551 #endif
1552 bank->chip.base = OMAP_MPUIO(0);
1553 } else {
1554 bank->chip.label = "gpio";
1555 bank->chip.base = gpio;
1556 gpio += bank_width;
1557 }
1558 bank->chip.ngpio = bank_width;
1559
1560 gpiochip_add(&bank->chip);
1561
1562 for (j = bank->virtual_irq_start;
1563 j < bank->virtual_irq_start + bank_width; j++) {
1564 irq_set_lockdep_class(j, &gpio_lock_class);
1565 irq_set_chip_data(j, bank);
1566 if (bank_is_mpuio(bank))
1567 irq_set_chip(j, &mpuio_irq_chip);
1568 else
1569 irq_set_chip(j, &gpio_irq_chip);
1570 irq_set_handler(j, handle_simple_irq);
1571 set_irq_flags(j, IRQF_VALID);
1572 }
1573 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1574 irq_set_handler_data(bank->irq, bank);
1575 }
1576
1577 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1578 {
1579 static int gpio_init_done;
1580 struct omap_gpio_platform_data *pdata;
1581 struct resource *res;
1582 int id;
1583 struct gpio_bank *bank;
1584
1585 if (!pdev->dev.platform_data)
1586 return -EINVAL;
1587
1588 pdata = pdev->dev.platform_data;
1589
1590 if (!gpio_init_done) {
1591 int ret;
1592
1593 ret = init_gpio_info(pdev);
1594 if (ret)
1595 return ret;
1596 }
1597
1598 id = pdev->id;
1599 bank = &gpio_bank[id];
1600
1601 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1602 if (unlikely(!res)) {
1603 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1604 return -ENODEV;
1605 }
1606
1607 bank->irq = res->start;
1608 bank->virtual_irq_start = pdata->virtual_irq_start;
1609 bank->method = pdata->bank_type;
1610 bank->dev = &pdev->dev;
1611 bank->dbck_flag = pdata->dbck_flag;
1612 bank->stride = pdata->bank_stride;
1613 bank_width = pdata->bank_width;
1614
1615 spin_lock_init(&bank->lock);
1616
1617 /* Static mapping, never released */
1618 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1619 if (unlikely(!res)) {
1620 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1621 return -ENODEV;
1622 }
1623
1624 bank->base = ioremap(res->start, resource_size(res));
1625 if (!bank->base) {
1626 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1627 return -ENOMEM;
1628 }
1629
1630 pm_runtime_enable(bank->dev);
1631 pm_runtime_get_sync(bank->dev);
1632
1633 omap_gpio_mod_init(bank, id);
1634 omap_gpio_chip_init(bank);
1635 omap_gpio_show_rev(bank);
1636
1637 if (!gpio_init_done)
1638 gpio_init_done = 1;
1639
1640 return 0;
1641 }
1642
1643 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1644 static int omap_gpio_suspend(void)
1645 {
1646 int i;
1647
1648 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1649 return 0;
1650
1651 for (i = 0; i < gpio_bank_count; i++) {
1652 struct gpio_bank *bank = &gpio_bank[i];
1653 void __iomem *wake_status;
1654 void __iomem *wake_clear;
1655 void __iomem *wake_set;
1656 unsigned long flags;
1657
1658 switch (bank->method) {
1659 #ifdef CONFIG_ARCH_OMAP16XX
1660 case METHOD_GPIO_1610:
1661 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1662 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1663 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1664 break;
1665 #endif
1666 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1667 case METHOD_GPIO_24XX:
1668 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1669 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1670 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1671 break;
1672 #endif
1673 #ifdef CONFIG_ARCH_OMAP4
1674 case METHOD_GPIO_44XX:
1675 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1676 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1677 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1678 break;
1679 #endif
1680 default:
1681 continue;
1682 }
1683
1684 spin_lock_irqsave(&bank->lock, flags);
1685 bank->saved_wakeup = __raw_readl(wake_status);
1686 __raw_writel(0xffffffff, wake_clear);
1687 __raw_writel(bank->suspend_wakeup, wake_set);
1688 spin_unlock_irqrestore(&bank->lock, flags);
1689 }
1690
1691 return 0;
1692 }
1693
1694 static void omap_gpio_resume(void)
1695 {
1696 int i;
1697
1698 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1699 return;
1700
1701 for (i = 0; i < gpio_bank_count; i++) {
1702 struct gpio_bank *bank = &gpio_bank[i];
1703 void __iomem *wake_clear;
1704 void __iomem *wake_set;
1705 unsigned long flags;
1706
1707 switch (bank->method) {
1708 #ifdef CONFIG_ARCH_OMAP16XX
1709 case METHOD_GPIO_1610:
1710 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1711 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1712 break;
1713 #endif
1714 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1715 case METHOD_GPIO_24XX:
1716 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1717 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1718 break;
1719 #endif
1720 #ifdef CONFIG_ARCH_OMAP4
1721 case METHOD_GPIO_44XX:
1722 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1723 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1724 break;
1725 #endif
1726 default:
1727 continue;
1728 }
1729
1730 spin_lock_irqsave(&bank->lock, flags);
1731 __raw_writel(0xffffffff, wake_clear);
1732 __raw_writel(bank->saved_wakeup, wake_set);
1733 spin_unlock_irqrestore(&bank->lock, flags);
1734 }
1735 }
1736
1737 static struct syscore_ops omap_gpio_syscore_ops = {
1738 .suspend = omap_gpio_suspend,
1739 .resume = omap_gpio_resume,
1740 };
1741
1742 #endif
1743
1744 #ifdef CONFIG_ARCH_OMAP2PLUS
1745
1746 static int workaround_enabled;
1747
1748 void omap2_gpio_prepare_for_idle(int off_mode)
1749 {
1750 int i, c = 0;
1751 int min = 0;
1752
1753 if (cpu_is_omap34xx())
1754 min = 1;
1755
1756 for (i = min; i < gpio_bank_count; i++) {
1757 struct gpio_bank *bank = &gpio_bank[i];
1758 u32 l1 = 0, l2 = 0;
1759 int j;
1760
1761 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1762 clk_disable(bank->dbck);
1763
1764 if (!off_mode)
1765 continue;
1766
1767 /* If going to OFF, remove triggering for all
1768 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1769 * generated. See OMAP2420 Errata item 1.101. */
1770 if (!(bank->enabled_non_wakeup_gpios))
1771 continue;
1772
1773 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1774 bank->saved_datain = __raw_readl(bank->base +
1775 OMAP24XX_GPIO_DATAIN);
1776 l1 = __raw_readl(bank->base +
1777 OMAP24XX_GPIO_FALLINGDETECT);
1778 l2 = __raw_readl(bank->base +
1779 OMAP24XX_GPIO_RISINGDETECT);
1780 }
1781
1782 if (cpu_is_omap44xx()) {
1783 bank->saved_datain = __raw_readl(bank->base +
1784 OMAP4_GPIO_DATAIN);
1785 l1 = __raw_readl(bank->base +
1786 OMAP4_GPIO_FALLINGDETECT);
1787 l2 = __raw_readl(bank->base +
1788 OMAP4_GPIO_RISINGDETECT);
1789 }
1790
1791 bank->saved_fallingdetect = l1;
1792 bank->saved_risingdetect = l2;
1793 l1 &= ~bank->enabled_non_wakeup_gpios;
1794 l2 &= ~bank->enabled_non_wakeup_gpios;
1795
1796 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1797 __raw_writel(l1, bank->base +
1798 OMAP24XX_GPIO_FALLINGDETECT);
1799 __raw_writel(l2, bank->base +
1800 OMAP24XX_GPIO_RISINGDETECT);
1801 }
1802
1803 if (cpu_is_omap44xx()) {
1804 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1805 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1806 }
1807
1808 c++;
1809 }
1810 if (!c) {
1811 workaround_enabled = 0;
1812 return;
1813 }
1814 workaround_enabled = 1;
1815 }
1816
1817 void omap2_gpio_resume_after_idle(void)
1818 {
1819 int i;
1820 int min = 0;
1821
1822 if (cpu_is_omap34xx())
1823 min = 1;
1824 for (i = min; i < gpio_bank_count; i++) {
1825 struct gpio_bank *bank = &gpio_bank[i];
1826 u32 l = 0, gen, gen0, gen1;
1827 int j;
1828
1829 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1830 clk_enable(bank->dbck);
1831
1832 if (!workaround_enabled)
1833 continue;
1834
1835 if (!(bank->enabled_non_wakeup_gpios))
1836 continue;
1837
1838 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1839 __raw_writel(bank->saved_fallingdetect,
1840 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1841 __raw_writel(bank->saved_risingdetect,
1842 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1843 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1844 }
1845
1846 if (cpu_is_omap44xx()) {
1847 __raw_writel(bank->saved_fallingdetect,
1848 bank->base + OMAP4_GPIO_FALLINGDETECT);
1849 __raw_writel(bank->saved_risingdetect,
1850 bank->base + OMAP4_GPIO_RISINGDETECT);
1851 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1852 }
1853
1854 /* Check if any of the non-wakeup interrupt GPIOs have changed
1855 * state. If so, generate an IRQ by software. This is
1856 * horribly racy, but it's the best we can do to work around
1857 * this silicon bug. */
1858 l ^= bank->saved_datain;
1859 l &= bank->enabled_non_wakeup_gpios;
1860
1861 /*
1862 * No need to generate IRQs for the rising edge for gpio IRQs
1863 * configured with falling edge only; and vice versa.
1864 */
1865 gen0 = l & bank->saved_fallingdetect;
1866 gen0 &= bank->saved_datain;
1867
1868 gen1 = l & bank->saved_risingdetect;
1869 gen1 &= ~(bank->saved_datain);
1870
1871 /* FIXME: Consider GPIO IRQs with level detections properly! */
1872 gen = l & (~(bank->saved_fallingdetect) &
1873 ~(bank->saved_risingdetect));
1874 /* Consider all GPIO IRQs needed to be updated */
1875 gen |= gen0 | gen1;
1876
1877 if (gen) {
1878 u32 old0, old1;
1879
1880 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1881 old0 = __raw_readl(bank->base +
1882 OMAP24XX_GPIO_LEVELDETECT0);
1883 old1 = __raw_readl(bank->base +
1884 OMAP24XX_GPIO_LEVELDETECT1);
1885 __raw_writel(old0 | gen, bank->base +
1886 OMAP24XX_GPIO_LEVELDETECT0);
1887 __raw_writel(old1 | gen, bank->base +
1888 OMAP24XX_GPIO_LEVELDETECT1);
1889 __raw_writel(old0, bank->base +
1890 OMAP24XX_GPIO_LEVELDETECT0);
1891 __raw_writel(old1, bank->base +
1892 OMAP24XX_GPIO_LEVELDETECT1);
1893 }
1894
1895 if (cpu_is_omap44xx()) {
1896 old0 = __raw_readl(bank->base +
1897 OMAP4_GPIO_LEVELDETECT0);
1898 old1 = __raw_readl(bank->base +
1899 OMAP4_GPIO_LEVELDETECT1);
1900 __raw_writel(old0 | l, bank->base +
1901 OMAP4_GPIO_LEVELDETECT0);
1902 __raw_writel(old1 | l, bank->base +
1903 OMAP4_GPIO_LEVELDETECT1);
1904 __raw_writel(old0, bank->base +
1905 OMAP4_GPIO_LEVELDETECT0);
1906 __raw_writel(old1, bank->base +
1907 OMAP4_GPIO_LEVELDETECT1);
1908 }
1909 }
1910 }
1911
1912 }
1913
1914 #endif
1915
1916 #ifdef CONFIG_ARCH_OMAP3
1917 /* save the registers of bank 2-6 */
1918 void omap_gpio_save_context(void)
1919 {
1920 int i;
1921
1922 /* saving banks from 2-6 only since GPIO1 is in WKUP */
1923 for (i = 1; i < gpio_bank_count; i++) {
1924 struct gpio_bank *bank = &gpio_bank[i];
1925 gpio_context[i].irqenable1 =
1926 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
1927 gpio_context[i].irqenable2 =
1928 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
1929 gpio_context[i].wake_en =
1930 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
1931 gpio_context[i].ctrl =
1932 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
1933 gpio_context[i].oe =
1934 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
1935 gpio_context[i].leveldetect0 =
1936 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1937 gpio_context[i].leveldetect1 =
1938 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1939 gpio_context[i].risingdetect =
1940 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1941 gpio_context[i].fallingdetect =
1942 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1943 gpio_context[i].dataout =
1944 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
1945 }
1946 }
1947
1948 /* restore the required registers of bank 2-6 */
1949 void omap_gpio_restore_context(void)
1950 {
1951 int i;
1952
1953 for (i = 1; i < gpio_bank_count; i++) {
1954 struct gpio_bank *bank = &gpio_bank[i];
1955 __raw_writel(gpio_context[i].irqenable1,
1956 bank->base + OMAP24XX_GPIO_IRQENABLE1);
1957 __raw_writel(gpio_context[i].irqenable2,
1958 bank->base + OMAP24XX_GPIO_IRQENABLE2);
1959 __raw_writel(gpio_context[i].wake_en,
1960 bank->base + OMAP24XX_GPIO_WAKE_EN);
1961 __raw_writel(gpio_context[i].ctrl,
1962 bank->base + OMAP24XX_GPIO_CTRL);
1963 __raw_writel(gpio_context[i].oe,
1964 bank->base + OMAP24XX_GPIO_OE);
1965 __raw_writel(gpio_context[i].leveldetect0,
1966 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1967 __raw_writel(gpio_context[i].leveldetect1,
1968 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1969 __raw_writel(gpio_context[i].risingdetect,
1970 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1971 __raw_writel(gpio_context[i].fallingdetect,
1972 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1973 __raw_writel(gpio_context[i].dataout,
1974 bank->base + OMAP24XX_GPIO_DATAOUT);
1975 }
1976 }
1977 #endif
1978
1979 static struct platform_driver omap_gpio_driver = {
1980 .probe = omap_gpio_probe,
1981 .driver = {
1982 .name = "omap_gpio",
1983 },
1984 };
1985
1986 /*
1987 * gpio driver register needs to be done before
1988 * machine_init functions access gpio APIs.
1989 * Hence omap_gpio_drv_reg() is a postcore_initcall.
1990 */
1991 static int __init omap_gpio_drv_reg(void)
1992 {
1993 return platform_driver_register(&omap_gpio_driver);
1994 }
1995 postcore_initcall(omap_gpio_drv_reg);
1996
1997 static int __init omap_gpio_sysinit(void)
1998 {
1999 mpuio_init();
2000
2001 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2002 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2003 register_syscore_ops(&omap_gpio_syscore_ops);
2004 #endif
2005
2006 return 0;
2007 }
2008
2009 arch_initcall(omap_gpio_sysinit);
Linux with added FPC-III support