2 * HP i8042-based System Device Controller driver.
4 * Copyright (c) 2001 Brian S. Julin
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * Alternatively, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL").
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * System Device Controller Microprocessor Firmware Theory of Operation
31 * for Part Number 1820-4784 Revision B. Dwg No. A-1820-4784-2
32 * Helge Deller's original hilkbd.c port for PA-RISC.
35 * Driver theory of operation:
37 * hp_sdc_put does all writing to the SDC. ISR can run on a different
38 * CPU than hp_sdc_put, but only one CPU runs hp_sdc_put at a time
39 * (it cannot really benefit from SMP anyway.) A tasket fit this perfectly.
41 * All data coming back from the SDC is sent via interrupt and can be read
42 * fully in the ISR, so there are no latency/throughput problems there.
43 * The problem is with output, due to the slow clock speed of the SDC
44 * compared to the CPU. This should not be too horrible most of the time,
45 * but if used with HIL devices that support the multibyte transfer command,
46 * keeping outbound throughput flowing at the 6500KBps that the HIL is
47 * capable of is more than can be done at HZ=100.
49 * Busy polling for IBF clear wastes CPU cycles and bus cycles. hp_sdc.ibf
50 * is set to 0 when the IBF flag in the status register has cleared. ISR
51 * may do this, and may also access the parts of queued transactions related
52 * to reading data back from the SDC, but otherwise will not touch the
53 * hp_sdc state. Whenever a register is written hp_sdc.ibf is set to 1.
55 * The i8042 write index and the values in the 4-byte input buffer
56 * starting at 0x70 are kept track of in hp_sdc.wi, and .r7[], respectively,
57 * to minimize the amount of IO needed to the SDC. However these values
58 * do not need to be locked since they are only ever accessed by hp_sdc_put.
60 * A timer task schedules the tasklet once per second just to make
61 * sure it doesn't freeze up and to allow for bad reads to time out.
64 #include <linux/hp_sdc.h>
65 #include <linux/errno.h>
66 #include <linux/init.h>
67 #include <linux/module.h>
68 #include <linux/ioport.h>
69 #include <linux/time.h>
70 #include <linux/semaphore.h>
71 #include <linux/slab.h>
72 #include <linux/hil.h>
74 #include <asm/system.h>
76 /* Machine-specific abstraction */
79 # include <asm/parisc-device.h>
80 # define sdc_readb(p) gsc_readb(p)
81 # define sdc_writeb(v,p) gsc_writeb((v),(p))
82 #elif defined(__mc68000__)
83 # include <asm/uaccess.h>
84 # define sdc_readb(p) in_8(p)
85 # define sdc_writeb(v,p) out_8((p),(v))
87 # error "HIL is not supported on this platform"
90 #define PREFIX "HP SDC: "
92 MODULE_AUTHOR("Brian S. Julin <bri@calyx.com>");
93 MODULE_DESCRIPTION("HP i8042-based SDC Driver");
94 MODULE_LICENSE("Dual BSD/GPL");
96 EXPORT_SYMBOL(hp_sdc_request_timer_irq
);
97 EXPORT_SYMBOL(hp_sdc_request_hil_irq
);
98 EXPORT_SYMBOL(hp_sdc_request_cooked_irq
);
100 EXPORT_SYMBOL(hp_sdc_release_timer_irq
);
101 EXPORT_SYMBOL(hp_sdc_release_hil_irq
);
102 EXPORT_SYMBOL(hp_sdc_release_cooked_irq
);
104 EXPORT_SYMBOL(__hp_sdc_enqueue_transaction
);
105 EXPORT_SYMBOL(hp_sdc_enqueue_transaction
);
106 EXPORT_SYMBOL(hp_sdc_dequeue_transaction
);
108 static unsigned int hp_sdc_disabled
;
109 module_param_named(no_hpsdc
, hp_sdc_disabled
, bool, 0);
110 MODULE_PARM_DESC(no_hpsdc
, "Do not enable HP SDC driver.");
112 static hp_i8042_sdc hp_sdc
; /* All driver state is kept in here. */
114 /*************** primitives for use in any context *********************/
115 static inline uint8_t hp_sdc_status_in8(void)
120 write_lock_irqsave(&hp_sdc
.ibf_lock
, flags
);
121 status
= sdc_readb(hp_sdc
.status_io
);
122 if (!(status
& HP_SDC_STATUS_IBF
))
124 write_unlock_irqrestore(&hp_sdc
.ibf_lock
, flags
);
129 static inline uint8_t hp_sdc_data_in8(void)
131 return sdc_readb(hp_sdc
.data_io
);
134 static inline void hp_sdc_status_out8(uint8_t val
)
138 write_lock_irqsave(&hp_sdc
.ibf_lock
, flags
);
140 if ((val
& 0xf0) == 0xe0)
142 sdc_writeb(val
, hp_sdc
.status_io
);
143 write_unlock_irqrestore(&hp_sdc
.ibf_lock
, flags
);
146 static inline void hp_sdc_data_out8(uint8_t val
)
150 write_lock_irqsave(&hp_sdc
.ibf_lock
, flags
);
152 sdc_writeb(val
, hp_sdc
.data_io
);
153 write_unlock_irqrestore(&hp_sdc
.ibf_lock
, flags
);
156 /* Care must be taken to only invoke hp_sdc_spin_ibf when
157 * absolutely needed, or in rarely invoked subroutines.
158 * Not only does it waste CPU cycles, it also wastes bus cycles.
160 static inline void hp_sdc_spin_ibf(void)
165 lock
= &hp_sdc
.ibf_lock
;
167 read_lock_irqsave(lock
, flags
);
169 read_unlock_irqrestore(lock
, flags
);
174 while (sdc_readb(hp_sdc
.status_io
) & HP_SDC_STATUS_IBF
)
177 write_unlock_irqrestore(lock
, flags
);
181 /************************ Interrupt context functions ************************/
182 static void hp_sdc_take(int irq
, void *dev_id
, uint8_t status
, uint8_t data
)
184 hp_sdc_transaction
*curr
;
186 read_lock(&hp_sdc
.rtq_lock
);
187 if (hp_sdc
.rcurr
< 0) {
188 read_unlock(&hp_sdc
.rtq_lock
);
191 curr
= hp_sdc
.tq
[hp_sdc
.rcurr
];
192 read_unlock(&hp_sdc
.rtq_lock
);
194 curr
->seq
[curr
->idx
++] = status
;
195 curr
->seq
[curr
->idx
++] = data
;
197 do_gettimeofday(&hp_sdc
.rtv
);
199 if (hp_sdc
.rqty
<= 0) {
200 /* All data has been gathered. */
201 if (curr
->seq
[curr
->actidx
] & HP_SDC_ACT_SEMAPHORE
)
202 if (curr
->act
.semaphore
)
203 up(curr
->act
.semaphore
);
205 if (curr
->seq
[curr
->actidx
] & HP_SDC_ACT_CALLBACK
)
206 if (curr
->act
.irqhook
)
207 curr
->act
.irqhook(irq
, dev_id
, status
, data
);
209 curr
->actidx
= curr
->idx
;
211 /* Return control of this transaction */
212 write_lock(&hp_sdc
.rtq_lock
);
215 write_unlock(&hp_sdc
.rtq_lock
);
216 tasklet_schedule(&hp_sdc
.task
);
220 static irqreturn_t
hp_sdc_isr(int irq
, void *dev_id
)
222 uint8_t status
, data
;
224 status
= hp_sdc_status_in8();
225 /* Read data unconditionally to advance i8042. */
226 data
= hp_sdc_data_in8();
228 /* For now we are ignoring these until we get the SDC to behave. */
229 if (((status
& 0xf1) == 0x51) && data
== 0x82)
232 switch (status
& HP_SDC_STATUS_IRQMASK
) {
233 case 0: /* This case is not documented. */
236 case HP_SDC_STATUS_USERTIMER
:
237 case HP_SDC_STATUS_PERIODIC
:
238 case HP_SDC_STATUS_TIMER
:
239 read_lock(&hp_sdc
.hook_lock
);
240 if (hp_sdc
.timer
!= NULL
)
241 hp_sdc
.timer(irq
, dev_id
, status
, data
);
242 read_unlock(&hp_sdc
.hook_lock
);
245 case HP_SDC_STATUS_REG
:
246 hp_sdc_take(irq
, dev_id
, status
, data
);
249 case HP_SDC_STATUS_HILCMD
:
250 case HP_SDC_STATUS_HILDATA
:
251 read_lock(&hp_sdc
.hook_lock
);
252 if (hp_sdc
.hil
!= NULL
)
253 hp_sdc
.hil(irq
, dev_id
, status
, data
);
254 read_unlock(&hp_sdc
.hook_lock
);
257 case HP_SDC_STATUS_PUP
:
258 read_lock(&hp_sdc
.hook_lock
);
259 if (hp_sdc
.pup
!= NULL
)
260 hp_sdc
.pup(irq
, dev_id
, status
, data
);
262 printk(KERN_INFO PREFIX
"HP SDC reports successful PUP.\n");
263 read_unlock(&hp_sdc
.hook_lock
);
267 read_lock(&hp_sdc
.hook_lock
);
268 if (hp_sdc
.cooked
!= NULL
)
269 hp_sdc
.cooked(irq
, dev_id
, status
, data
);
270 read_unlock(&hp_sdc
.hook_lock
);
278 static irqreturn_t
hp_sdc_nmisr(int irq
, void *dev_id
)
282 status
= hp_sdc_status_in8();
283 printk(KERN_WARNING PREFIX
"NMI !\n");
286 if (status
& HP_SDC_NMISTATUS_FHS
) {
287 read_lock(&hp_sdc
.hook_lock
);
288 if (hp_sdc
.timer
!= NULL
)
289 hp_sdc
.timer(irq
, dev_id
, status
, 0);
290 read_unlock(&hp_sdc
.hook_lock
);
292 /* TODO: pass this on to the HIL handler, or do SAK here? */
293 printk(KERN_WARNING PREFIX
"HIL NMI\n");
301 /***************** Kernel (tasklet) context functions ****************/
303 unsigned long hp_sdc_put(void);
305 static void hp_sdc_tasklet(unsigned long foo
)
307 write_lock_irq(&hp_sdc
.rtq_lock
);
309 if (hp_sdc
.rcurr
>= 0) {
312 do_gettimeofday(&tv
);
313 if (tv
.tv_sec
> hp_sdc
.rtv
.tv_sec
)
314 tv
.tv_usec
+= USEC_PER_SEC
;
316 if (tv
.tv_usec
- hp_sdc
.rtv
.tv_usec
> HP_SDC_MAX_REG_DELAY
) {
317 hp_sdc_transaction
*curr
;
320 curr
= hp_sdc
.tq
[hp_sdc
.rcurr
];
321 /* If this turns out to be a normal failure mode
322 * we'll need to figure out a way to communicate
323 * it back to the application. and be less verbose.
325 printk(KERN_WARNING PREFIX
"read timeout (%ius)!\n",
326 (int)(tv
.tv_usec
- hp_sdc
.rtv
.tv_usec
));
327 curr
->idx
+= hp_sdc
.rqty
;
329 tmp
= curr
->seq
[curr
->actidx
];
330 curr
->seq
[curr
->actidx
] |= HP_SDC_ACT_DEAD
;
331 if (tmp
& HP_SDC_ACT_SEMAPHORE
)
332 if (curr
->act
.semaphore
)
333 up(curr
->act
.semaphore
);
335 if (tmp
& HP_SDC_ACT_CALLBACK
) {
336 /* Note this means that irqhooks may be called
337 * in tasklet/bh context.
339 if (curr
->act
.irqhook
)
340 curr
->act
.irqhook(0, NULL
, 0, 0);
343 curr
->actidx
= curr
->idx
;
348 write_unlock_irq(&hp_sdc
.rtq_lock
);
352 unsigned long hp_sdc_put(void)
354 hp_sdc_transaction
*curr
;
360 write_lock(&hp_sdc
.lock
);
362 /* If i8042 buffers are full, we cannot do anything that
363 requires output, so we skip to the administrativa. */
371 /* See if we are in the middle of a sequence. */
372 if (hp_sdc
.wcurr
< 0)
374 read_lock_irq(&hp_sdc
.rtq_lock
);
375 if (hp_sdc
.rcurr
== hp_sdc
.wcurr
)
377 read_unlock_irq(&hp_sdc
.rtq_lock
);
378 if (hp_sdc
.wcurr
>= HP_SDC_QUEUE_LEN
)
380 curridx
= hp_sdc
.wcurr
;
382 if (hp_sdc
.tq
[curridx
] != NULL
)
385 while (++curridx
!= hp_sdc
.wcurr
) {
386 if (curridx
>= HP_SDC_QUEUE_LEN
) {
387 curridx
= -1; /* Wrap to top */
390 read_lock_irq(&hp_sdc
.rtq_lock
);
391 if (hp_sdc
.rcurr
== curridx
) {
392 read_unlock_irq(&hp_sdc
.rtq_lock
);
395 read_unlock_irq(&hp_sdc
.rtq_lock
);
396 if (hp_sdc
.tq
[curridx
] != NULL
)
397 break; /* Found one. */
399 if (curridx
== hp_sdc
.wcurr
) { /* There's nothing queued to do. */
402 hp_sdc
.wcurr
= curridx
;
406 /* Check to see if the interrupt mask needs to be set. */
408 hp_sdc_status_out8(hp_sdc
.im
| HP_SDC_CMD_SET_IM
);
413 if (hp_sdc
.wcurr
== -1)
416 curr
= hp_sdc
.tq
[curridx
];
419 if (curr
->actidx
>= curr
->endidx
) {
420 hp_sdc
.tq
[curridx
] = NULL
;
421 /* Interleave outbound data between the transactions. */
423 if (hp_sdc
.wcurr
>= HP_SDC_QUEUE_LEN
)
428 act
= curr
->seq
[idx
];
431 if (curr
->idx
>= curr
->endidx
) {
432 if (act
& HP_SDC_ACT_DEALLOC
)
434 hp_sdc
.tq
[curridx
] = NULL
;
435 /* Interleave outbound data between the transactions. */
437 if (hp_sdc
.wcurr
>= HP_SDC_QUEUE_LEN
)
442 while (act
& HP_SDC_ACT_PRECMD
) {
443 if (curr
->idx
!= idx
) {
445 act
&= ~HP_SDC_ACT_PRECMD
;
448 hp_sdc_status_out8(curr
->seq
[idx
]);
451 if ((act
& HP_SDC_ACT_DURING
) == HP_SDC_ACT_PRECMD
)
453 /* skip quantity field if data-out sequence follows. */
454 if (act
& HP_SDC_ACT_DATAOUT
)
458 if (act
& HP_SDC_ACT_DATAOUT
) {
461 qty
= curr
->seq
[idx
];
463 if (curr
->idx
- idx
< qty
) {
464 hp_sdc_data_out8(curr
->seq
[curr
->idx
]);
467 if (curr
->idx
- idx
>= qty
&&
468 (act
& HP_SDC_ACT_DURING
) == HP_SDC_ACT_DATAOUT
)
473 act
&= ~HP_SDC_ACT_DATAOUT
;
475 while (act
& HP_SDC_ACT_DATAREG
) {
479 mask
= curr
->seq
[idx
];
480 if (idx
!= curr
->idx
) {
486 act
&= ~HP_SDC_ACT_DATAREG
;
490 w7
[0] = (mask
& 1) ? curr
->seq
[++idx
] : hp_sdc
.r7
[0];
491 w7
[1] = (mask
& 2) ? curr
->seq
[++idx
] : hp_sdc
.r7
[1];
492 w7
[2] = (mask
& 4) ? curr
->seq
[++idx
] : hp_sdc
.r7
[2];
493 w7
[3] = (mask
& 8) ? curr
->seq
[++idx
] : hp_sdc
.r7
[3];
495 if (hp_sdc
.wi
> 0x73 || hp_sdc
.wi
< 0x70 ||
496 w7
[hp_sdc
.wi
- 0x70] == hp_sdc
.r7
[hp_sdc
.wi
- 0x70]) {
499 /* Need to point the write index register */
500 while (i
< 4 && w7
[i
] == hp_sdc
.r7
[i
])
504 hp_sdc_status_out8(HP_SDC_CMD_SET_D0
+ i
);
505 hp_sdc
.wi
= 0x70 + i
;
510 if ((act
& HP_SDC_ACT_DURING
) == HP_SDC_ACT_DATAREG
)
514 act
&= ~HP_SDC_ACT_DATAREG
;
518 hp_sdc_data_out8(w7
[hp_sdc
.wi
- 0x70]);
519 hp_sdc
.r7
[hp_sdc
.wi
- 0x70] = w7
[hp_sdc
.wi
- 0x70];
520 hp_sdc
.wi
++; /* write index register autoincrements */
524 while ((i
< 4) && w7
[i
] == hp_sdc
.r7
[i
])
528 if ((act
& HP_SDC_ACT_DURING
) ==
535 /* We don't go any further in the command if there is a pending read,
536 because we don't want interleaved results. */
537 read_lock_irq(&hp_sdc
.rtq_lock
);
538 if (hp_sdc
.rcurr
>= 0) {
539 read_unlock_irq(&hp_sdc
.rtq_lock
);
542 read_unlock_irq(&hp_sdc
.rtq_lock
);
545 if (act
& HP_SDC_ACT_POSTCMD
) {
548 /* curr->idx should == idx at this point. */
549 postcmd
= curr
->seq
[idx
];
551 if (act
& HP_SDC_ACT_DATAIN
) {
553 /* Start a new read */
554 hp_sdc
.rqty
= curr
->seq
[curr
->idx
];
555 do_gettimeofday(&hp_sdc
.rtv
);
557 /* Still need to lock here in case of spurious irq. */
558 write_lock_irq(&hp_sdc
.rtq_lock
);
559 hp_sdc
.rcurr
= curridx
;
560 write_unlock_irq(&hp_sdc
.rtq_lock
);
561 hp_sdc_status_out8(postcmd
);
564 hp_sdc_status_out8(postcmd
);
569 if (act
& HP_SDC_ACT_SEMAPHORE
)
570 up(curr
->act
.semaphore
);
571 else if (act
& HP_SDC_ACT_CALLBACK
)
572 curr
->act
.irqhook(0,NULL
,0,0);
574 if (curr
->idx
>= curr
->endidx
) { /* This transaction is over. */
575 if (act
& HP_SDC_ACT_DEALLOC
)
577 hp_sdc
.tq
[curridx
] = NULL
;
579 curr
->actidx
= idx
+ 1;
582 /* Interleave outbound data between the transactions. */
584 if (hp_sdc
.wcurr
>= HP_SDC_QUEUE_LEN
)
588 /* If by some quirk IBF has cleared and our ISR has run to
589 see that that has happened, do it all again. */
590 if (!hp_sdc
.ibf
&& limit
++ < 20)
594 if (hp_sdc
.wcurr
>= 0)
595 tasklet_schedule(&hp_sdc
.task
);
596 write_unlock(&hp_sdc
.lock
);
601 /******* Functions called in either user or kernel context ****/
602 int __hp_sdc_enqueue_transaction(hp_sdc_transaction
*this)
611 /* Can't have same transaction on queue twice */
612 for (i
= 0; i
< HP_SDC_QUEUE_LEN
; i
++)
613 if (hp_sdc
.tq
[i
] == this)
619 /* Search for empty slot */
620 for (i
= 0; i
< HP_SDC_QUEUE_LEN
; i
++)
621 if (hp_sdc
.tq
[i
] == NULL
) {
623 tasklet_schedule(&hp_sdc
.task
);
627 printk(KERN_WARNING PREFIX
"No free slot to add transaction.\n");
631 printk(KERN_WARNING PREFIX
"Transaction add failed: transaction already queued?\n");
635 int hp_sdc_enqueue_transaction(hp_sdc_transaction
*this) {
639 write_lock_irqsave(&hp_sdc
.lock
, flags
);
640 ret
= __hp_sdc_enqueue_transaction(this);
641 write_unlock_irqrestore(&hp_sdc
.lock
,flags
);
646 int hp_sdc_dequeue_transaction(hp_sdc_transaction
*this)
651 write_lock_irqsave(&hp_sdc
.lock
, flags
);
653 /* TODO: don't remove it if it's not done. */
655 for (i
= 0; i
< HP_SDC_QUEUE_LEN
; i
++)
656 if (hp_sdc
.tq
[i
] == this)
659 write_unlock_irqrestore(&hp_sdc
.lock
, flags
);
665 /********************** User context functions **************************/
666 int hp_sdc_request_timer_irq(hp_sdc_irqhook
*callback
)
668 if (callback
== NULL
|| hp_sdc
.dev
== NULL
)
671 write_lock_irq(&hp_sdc
.hook_lock
);
672 if (hp_sdc
.timer
!= NULL
) {
673 write_unlock_irq(&hp_sdc
.hook_lock
);
677 hp_sdc
.timer
= callback
;
678 /* Enable interrupts from the timers */
679 hp_sdc
.im
&= ~HP_SDC_IM_FH
;
680 hp_sdc
.im
&= ~HP_SDC_IM_PT
;
681 hp_sdc
.im
&= ~HP_SDC_IM_TIMERS
;
683 write_unlock_irq(&hp_sdc
.hook_lock
);
685 tasklet_schedule(&hp_sdc
.task
);
690 int hp_sdc_request_hil_irq(hp_sdc_irqhook
*callback
)
692 if (callback
== NULL
|| hp_sdc
.dev
== NULL
)
695 write_lock_irq(&hp_sdc
.hook_lock
);
696 if (hp_sdc
.hil
!= NULL
) {
697 write_unlock_irq(&hp_sdc
.hook_lock
);
701 hp_sdc
.hil
= callback
;
702 hp_sdc
.im
&= ~(HP_SDC_IM_HIL
| HP_SDC_IM_RESET
);
704 write_unlock_irq(&hp_sdc
.hook_lock
);
706 tasklet_schedule(&hp_sdc
.task
);
711 int hp_sdc_request_cooked_irq(hp_sdc_irqhook
*callback
)
713 if (callback
== NULL
|| hp_sdc
.dev
== NULL
)
716 write_lock_irq(&hp_sdc
.hook_lock
);
717 if (hp_sdc
.cooked
!= NULL
) {
718 write_unlock_irq(&hp_sdc
.hook_lock
);
722 /* Enable interrupts from the HIL MLC */
723 hp_sdc
.cooked
= callback
;
724 hp_sdc
.im
&= ~(HP_SDC_IM_HIL
| HP_SDC_IM_RESET
);
726 write_unlock_irq(&hp_sdc
.hook_lock
);
728 tasklet_schedule(&hp_sdc
.task
);
733 int hp_sdc_release_timer_irq(hp_sdc_irqhook
*callback
)
735 write_lock_irq(&hp_sdc
.hook_lock
);
736 if ((callback
!= hp_sdc
.timer
) ||
737 (hp_sdc
.timer
== NULL
)) {
738 write_unlock_irq(&hp_sdc
.hook_lock
);
742 /* Disable interrupts from the timers */
744 hp_sdc
.im
|= HP_SDC_IM_TIMERS
;
745 hp_sdc
.im
|= HP_SDC_IM_FH
;
746 hp_sdc
.im
|= HP_SDC_IM_PT
;
748 write_unlock_irq(&hp_sdc
.hook_lock
);
749 tasklet_schedule(&hp_sdc
.task
);
754 int hp_sdc_release_hil_irq(hp_sdc_irqhook
*callback
)
756 write_lock_irq(&hp_sdc
.hook_lock
);
757 if ((callback
!= hp_sdc
.hil
) ||
758 (hp_sdc
.hil
== NULL
)) {
759 write_unlock_irq(&hp_sdc
.hook_lock
);
764 /* Disable interrupts from HIL only if there is no cooked driver. */
765 if(hp_sdc
.cooked
== NULL
) {
766 hp_sdc
.im
|= (HP_SDC_IM_HIL
| HP_SDC_IM_RESET
);
769 write_unlock_irq(&hp_sdc
.hook_lock
);
770 tasklet_schedule(&hp_sdc
.task
);
775 int hp_sdc_release_cooked_irq(hp_sdc_irqhook
*callback
)
777 write_lock_irq(&hp_sdc
.hook_lock
);
778 if ((callback
!= hp_sdc
.cooked
) ||
779 (hp_sdc
.cooked
== NULL
)) {
780 write_unlock_irq(&hp_sdc
.hook_lock
);
784 hp_sdc
.cooked
= NULL
;
785 /* Disable interrupts from HIL only if there is no raw HIL driver. */
786 if(hp_sdc
.hil
== NULL
) {
787 hp_sdc
.im
|= (HP_SDC_IM_HIL
| HP_SDC_IM_RESET
);
790 write_unlock_irq(&hp_sdc
.hook_lock
);
791 tasklet_schedule(&hp_sdc
.task
);
796 /************************* Keepalive timer task *********************/
798 void hp_sdc_kicker (unsigned long data
)
800 tasklet_schedule(&hp_sdc
.task
);
801 /* Re-insert the periodic task. */
802 mod_timer(&hp_sdc
.kicker
, jiffies
+ HZ
);
805 /************************** Module Initialization ***************************/
807 #if defined(__hppa__)
809 static const struct parisc_device_id hp_sdc_tbl
[] = {
812 .hversion_rev
= HVERSION_REV_ANY_ID
,
813 .hversion
= HVERSION_ANY_ID
,
819 MODULE_DEVICE_TABLE(parisc
, hp_sdc_tbl
);
821 static int __init
hp_sdc_init_hppa(struct parisc_device
*d
);
822 static struct delayed_work moduleloader_work
;
824 static struct parisc_driver hp_sdc_driver
= {
826 .id_table
= hp_sdc_tbl
,
827 .probe
= hp_sdc_init_hppa
,
830 #endif /* __hppa__ */
832 static int __init
hp_sdc_init(void)
835 hp_sdc_transaction t_sync
;
837 struct semaphore s_sync
;
839 rwlock_init(&hp_sdc
.lock
);
840 rwlock_init(&hp_sdc
.ibf_lock
);
841 rwlock_init(&hp_sdc
.rtq_lock
);
842 rwlock_init(&hp_sdc
.hook_lock
);
847 hp_sdc
.cooked
= NULL
;
848 hp_sdc
.im
= HP_SDC_IM_MASK
; /* Mask maskable irqs */
857 memset(&hp_sdc
.tq
, 0, sizeof(hp_sdc
.tq
));
863 hp_sdc
.dev_err
= -ENODEV
;
865 errstr
= "IO not found for";
869 errstr
= "IRQ not found for";
873 hp_sdc
.dev_err
= -EBUSY
;
875 #if defined(__hppa__)
876 errstr
= "IO not available for";
877 if (request_region(hp_sdc
.data_io
, 2, hp_sdc_driver
.name
))
881 errstr
= "IRQ not available for";
882 if (request_irq(hp_sdc
.irq
, &hp_sdc_isr
, IRQF_SHARED
|IRQF_SAMPLE_RANDOM
,
886 errstr
= "NMI not available for";
887 if (request_irq(hp_sdc
.nmi
, &hp_sdc_nmisr
, IRQF_SHARED
,
888 "HP SDC NMI", &hp_sdc
))
891 printk(KERN_INFO PREFIX
"HP SDC at 0x%p, IRQ %d (NMI IRQ %d)\n",
892 (void *)hp_sdc
.base_io
, hp_sdc
.irq
, hp_sdc
.nmi
);
897 tasklet_init(&hp_sdc
.task
, hp_sdc_tasklet
, 0);
899 /* Sync the output buffer registers, thus scheduling hp_sdc_tasklet. */
903 t_sync
.seq
= ts_sync
;
904 ts_sync
[0] = HP_SDC_ACT_DATAREG
| HP_SDC_ACT_SEMAPHORE
;
906 ts_sync
[2] = ts_sync
[3] = ts_sync
[4] = ts_sync
[5] = 0;
907 t_sync
.act
.semaphore
= &s_sync
;
908 sema_init(&s_sync
, 0);
909 hp_sdc_enqueue_transaction(&t_sync
);
910 down(&s_sync
); /* Wait for t_sync to complete */
912 /* Create the keepalive task */
913 init_timer(&hp_sdc
.kicker
);
914 hp_sdc
.kicker
.expires
= jiffies
+ HZ
;
915 hp_sdc
.kicker
.function
= &hp_sdc_kicker
;
916 add_timer(&hp_sdc
.kicker
);
921 free_irq(hp_sdc
.irq
, &hp_sdc
);
923 release_region(hp_sdc
.data_io
, 2);
925 printk(KERN_WARNING PREFIX
": %s SDC IO=0x%p IRQ=0x%x NMI=0x%x\n",
926 errstr
, (void *)hp_sdc
.base_io
, hp_sdc
.irq
, hp_sdc
.nmi
);
929 return hp_sdc
.dev_err
;
932 #if defined(__hppa__)
934 static void request_module_delayed(struct work_struct
*work
)
936 request_module("hp_sdc_mlc");
939 static int __init
hp_sdc_init_hppa(struct parisc_device
*d
)
945 if (hp_sdc
.dev
!= NULL
)
946 return 1; /* We only expect one SDC */
950 hp_sdc
.nmi
= d
->aux_irq
;
951 hp_sdc
.base_io
= d
->hpa
.start
;
952 hp_sdc
.data_io
= d
->hpa
.start
+ 0x800;
953 hp_sdc
.status_io
= d
->hpa
.start
+ 0x801;
955 INIT_DELAYED_WORK(&moduleloader_work
, request_module_delayed
);
958 /* after successful initialization give SDC some time to settle
959 * and then load the hp_sdc_mlc upper layer driver */
961 schedule_delayed_work(&moduleloader_work
,
962 msecs_to_jiffies(2000));
967 #endif /* __hppa__ */
969 static void hp_sdc_exit(void)
971 /* do nothing if we don't have a SDC */
975 write_lock_irq(&hp_sdc
.lock
);
977 /* Turn off all maskable "sub-function" irq's. */
979 sdc_writeb(HP_SDC_CMD_SET_IM
| HP_SDC_IM_MASK
, hp_sdc
.status_io
);
981 /* Wait until we know this has been processed by the i8042 */
984 free_irq(hp_sdc
.nmi
, &hp_sdc
);
985 free_irq(hp_sdc
.irq
, &hp_sdc
);
986 write_unlock_irq(&hp_sdc
.lock
);
988 del_timer(&hp_sdc
.kicker
);
990 tasklet_kill(&hp_sdc
.task
);
992 #if defined(__hppa__)
993 cancel_delayed_work_sync(&moduleloader_work
);
994 if (unregister_parisc_driver(&hp_sdc_driver
))
995 printk(KERN_WARNING PREFIX
"Error unregistering HP SDC");
999 static int __init
hp_sdc_register(void)
1001 hp_sdc_transaction tq_init
;
1002 uint8_t tq_init_seq
[5];
1003 struct semaphore tq_init_sem
;
1004 #if defined(__mc68000__)
1009 if (hp_sdc_disabled
) {
1010 printk(KERN_WARNING PREFIX
"HP SDC driver disabled by no_hpsdc=1.\n");
1016 #if defined(__hppa__)
1017 if (register_parisc_driver(&hp_sdc_driver
)) {
1018 printk(KERN_WARNING PREFIX
"Error registering SDC with system bus tree.\n");
1021 #elif defined(__mc68000__)
1027 hp_sdc
.base_io
= (unsigned long) 0xf0428000;
1028 hp_sdc
.data_io
= (unsigned long) hp_sdc
.base_io
+ 1;
1029 hp_sdc
.status_io
= (unsigned long) hp_sdc
.base_io
+ 3;
1032 if (!get_user(i
, (unsigned char *)hp_sdc
.data_io
))
1033 hp_sdc
.dev
= (void *)1;
1035 hp_sdc
.dev_err
= hp_sdc_init();
1037 if (hp_sdc
.dev
== NULL
) {
1038 printk(KERN_WARNING PREFIX
"No SDC found.\n");
1039 return hp_sdc
.dev_err
;
1042 sema_init(&tq_init_sem
, 0);
1047 tq_init
.seq
= tq_init_seq
;
1048 tq_init
.act
.semaphore
= &tq_init_sem
;
1051 HP_SDC_ACT_POSTCMD
| HP_SDC_ACT_DATAIN
| HP_SDC_ACT_SEMAPHORE
;
1052 tq_init_seq
[1] = HP_SDC_CMD_READ_KCC
;
1057 hp_sdc_enqueue_transaction(&tq_init
);
1062 if ((tq_init_seq
[0] & HP_SDC_ACT_DEAD
) == HP_SDC_ACT_DEAD
) {
1063 printk(KERN_WARNING PREFIX
"Error reading config byte.\n");
1067 hp_sdc
.r11
= tq_init_seq
[4];
1068 if (hp_sdc
.r11
& HP_SDC_CFG_NEW
) {
1070 printk(KERN_INFO PREFIX
"New style SDC\n");
1071 tq_init_seq
[1] = HP_SDC_CMD_READ_XTD
;
1075 hp_sdc_enqueue_transaction(&tq_init
);
1078 if ((tq_init_seq
[0] & HP_SDC_ACT_DEAD
) == HP_SDC_ACT_DEAD
) {
1079 printk(KERN_WARNING PREFIX
"Error reading extended config byte.\n");
1082 hp_sdc
.r7e
= tq_init_seq
[4];
1083 HP_SDC_XTD_REV_STRINGS(hp_sdc
.r7e
& HP_SDC_XTD_REV
, str
)
1084 printk(KERN_INFO PREFIX
"Revision: %s\n", str
);
1085 if (hp_sdc
.r7e
& HP_SDC_XTD_BEEPER
)
1086 printk(KERN_INFO PREFIX
"TI SN76494 beeper present\n");
1087 if (hp_sdc
.r7e
& HP_SDC_XTD_BBRTC
)
1088 printk(KERN_INFO PREFIX
"OKI MSM-58321 BBRTC present\n");
1089 printk(KERN_INFO PREFIX
"Spunking the self test register to force PUP "
1090 "on next firmware reset.\n");
1091 tq_init_seq
[0] = HP_SDC_ACT_PRECMD
|
1092 HP_SDC_ACT_DATAOUT
| HP_SDC_ACT_SEMAPHORE
;
1093 tq_init_seq
[1] = HP_SDC_CMD_SET_STR
;
1100 hp_sdc_enqueue_transaction(&tq_init
);
1104 printk(KERN_INFO PREFIX
"Old style SDC (1820-%s).\n",
1105 (hp_sdc
.r11
& HP_SDC_CFG_REV
) ? "3300" : "2564/3087");
1110 module_init(hp_sdc_register
);
1111 module_exit(hp_sdc_exit
);
1113 /* Timing notes: These measurements taken on my 64MHz 7100-LC (715/64)
1114 * cycles cycles-adj time
1115 * between two consecutive mfctl(16)'s: 4 n/a 63ns
1116 * hp_sdc_spin_ibf when idle: 119 115 1.7us
1117 * gsc_writeb status register: 83 79 1.2us
1118 * IBF to clear after sending SET_IM: 6204 6006 93us
1119 * IBF to clear after sending LOAD_RT: 4467 4352 68us
1120 * IBF to clear after sending two LOAD_RTs: 18974 18859 295us
1121 * READ_T1, read status/data, IRQ, call handler: 35564 n/a 556us
1122 * cmd to ~IBF READ_T1 2nd time right after: 5158403 n/a 81ms
1123 * between IRQ received and ~IBF for above: 2578877 n/a 40ms
1125 * Performance stats after a run of this module configuring HIL and
1126 * receiving a few mouse events:
1128 * status in8 282508 cycles 7128 calls
1129 * status out8 8404 cycles 341 calls
1130 * data out8 1734 cycles 78 calls
1131 * isr 174324 cycles 617 calls (includes take)
1132 * take 1241 cycles 2 calls
1133 * put 1411504 cycles 6937 calls
1134 * task 1655209 cycles 6937 calls (includes put)