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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / mtd / nand / nand_base.c
blob86f05f45780ab46b708e7671bbfc5d69540dd68b
1 /*
2 * drivers/mtd/nand.c
3 *
4 * Overview:
5 * This is the generic MTD driver for NAND flash devices. It should be
6 * capable of working with almost all NAND chips currently available.
7 * Basic support for AG-AND chips is provided.
8 *
9 * Additional technical information is available on
10 * http://www.linux-mtd.infradead.org/doc/nand.html
11 *
12 * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
13 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
14 *
15 * Credits:
16 * David Woodhouse for adding multichip support
17 *
18 * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
19 * rework for 2K page size chips
20 *
21 * TODO:
22 * Enable cached programming for 2k page size chips
23 * Check, if mtd->ecctype should be set to MTD_ECC_HW
24 * if we have HW ecc support.
25 * The AG-AND chips have nice features for speed improvement,
26 * which are not supported yet. Read / program 4 pages in one go.
27 * BBT table is not serialized, has to be fixed
28 *
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License version 2 as
31 * published by the Free Software Foundation.
32 *
33 */
34
35 #include <linux/module.h>
36 #include <linux/delay.h>
37 #include <linux/errno.h>
38 #include <linux/err.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/types.h>
42 #include <linux/mtd/mtd.h>
43 #include <linux/mtd/nand.h>
44 #include <linux/mtd/nand_ecc.h>
45 #include <linux/mtd/nand_bch.h>
46 #include <linux/interrupt.h>
47 #include <linux/bitops.h>
48 #include <linux/leds.h>
49 #include <linux/io.h>
50 #include <linux/mtd/partitions.h>
51
52 /* Define default oob placement schemes for large and small page devices */
53 static struct nand_ecclayout nand_oob_8 = {
54 .eccbytes = 3,
55 .eccpos = {0, 1, 2},
56 .oobfree = {
57 {.offset = 3,
58 .length = 2},
59 {.offset = 6,
60 .length = 2} }
61 };
62
63 static struct nand_ecclayout nand_oob_16 = {
64 .eccbytes = 6,
65 .eccpos = {0, 1, 2, 3, 6, 7},
66 .oobfree = {
67 {.offset = 8,
68 . length = 8} }
69 };
70
71 static struct nand_ecclayout nand_oob_64 = {
72 .eccbytes = 24,
73 .eccpos = {
74 40, 41, 42, 43, 44, 45, 46, 47,
75 48, 49, 50, 51, 52, 53, 54, 55,
76 56, 57, 58, 59, 60, 61, 62, 63},
77 .oobfree = {
78 {.offset = 2,
79 .length = 38} }
80 };
81
82 static struct nand_ecclayout nand_oob_128 = {
83 .eccbytes = 48,
84 .eccpos = {
85 80, 81, 82, 83, 84, 85, 86, 87,
86 88, 89, 90, 91, 92, 93, 94, 95,
87 96, 97, 98, 99, 100, 101, 102, 103,
88 104, 105, 106, 107, 108, 109, 110, 111,
89 112, 113, 114, 115, 116, 117, 118, 119,
90 120, 121, 122, 123, 124, 125, 126, 127},
91 .oobfree = {
92 {.offset = 2,
93 .length = 78} }
94 };
95
96 static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd,
97 int new_state);
98
99 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
100 struct mtd_oob_ops *ops);
101
102 /*
103 * For devices which display every fart in the system on a separate LED. Is
104 * compiled away when LED support is disabled.
105 */
106 DEFINE_LED_TRIGGER(nand_led_trigger);
107
108 static int check_offs_len(struct mtd_info *mtd,
109 loff_t ofs, uint64_t len)
110 {
111 struct nand_chip *chip = mtd->priv;
112 int ret = 0;
113
114 /* Start address must align on block boundary */
115 if (ofs & ((1 << chip->phys_erase_shift) - 1)) {
116 DEBUG(MTD_DEBUG_LEVEL0, "%s: Unaligned address\n", __func__);
117 ret = -EINVAL;
118 }
119
120 /* Length must align on block boundary */
121 if (len & ((1 << chip->phys_erase_shift) - 1)) {
122 DEBUG(MTD_DEBUG_LEVEL0, "%s: Length not block aligned\n",
123 __func__);
124 ret = -EINVAL;
125 }
126
127 /* Do not allow past end of device */
128 if (ofs + len > mtd->size) {
129 DEBUG(MTD_DEBUG_LEVEL0, "%s: Past end of device\n",
130 __func__);
131 ret = -EINVAL;
132 }
133
134 return ret;
135 }
136
137 /**
138 * nand_release_device - [GENERIC] release chip
139 * @mtd: MTD device structure
140 *
141 * Deselect, release chip lock and wake up anyone waiting on the device
142 */
143 static void nand_release_device(struct mtd_info *mtd)
144 {
145 struct nand_chip *chip = mtd->priv;
146
147 /* De-select the NAND device */
148 chip->select_chip(mtd, -1);
149
150 /* Release the controller and the chip */
151 spin_lock(&chip->controller->lock);
152 chip->controller->active = NULL;
153 chip->state = FL_READY;
154 wake_up(&chip->controller->wq);
155 spin_unlock(&chip->controller->lock);
156 }
157
158 /**
159 * nand_read_byte - [DEFAULT] read one byte from the chip
160 * @mtd: MTD device structure
161 *
162 * Default read function for 8bit buswith
163 */
164 static uint8_t nand_read_byte(struct mtd_info *mtd)
165 {
166 struct nand_chip *chip = mtd->priv;
167 return readb(chip->IO_ADDR_R);
168 }
169
170 /**
171 * nand_read_byte16 - [DEFAULT] read one byte endianess aware from the chip
172 * @mtd: MTD device structure
173 *
174 * Default read function for 16bit buswith with
175 * endianess conversion
176 */
177 static uint8_t nand_read_byte16(struct mtd_info *mtd)
178 {
179 struct nand_chip *chip = mtd->priv;
180 return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
181 }
182
183 /**
184 * nand_read_word - [DEFAULT] read one word from the chip
185 * @mtd: MTD device structure
186 *
187 * Default read function for 16bit buswith without
188 * endianess conversion
189 */
190 static u16 nand_read_word(struct mtd_info *mtd)
191 {
192 struct nand_chip *chip = mtd->priv;
193 return readw(chip->IO_ADDR_R);
194 }
195
196 /**
197 * nand_select_chip - [DEFAULT] control CE line
198 * @mtd: MTD device structure
199 * @chipnr: chipnumber to select, -1 for deselect
200 *
201 * Default select function for 1 chip devices.
202 */
203 static void nand_select_chip(struct mtd_info *mtd, int chipnr)
204 {
205 struct nand_chip *chip = mtd->priv;
206
207 switch (chipnr) {
208 case -1:
209 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
210 break;
211 case 0:
212 break;
213
214 default:
215 BUG();
216 }
217 }
218
219 /**
220 * nand_write_buf - [DEFAULT] write buffer to chip
221 * @mtd: MTD device structure
222 * @buf: data buffer
223 * @len: number of bytes to write
224 *
225 * Default write function for 8bit buswith
226 */
227 static void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
228 {
229 int i;
230 struct nand_chip *chip = mtd->priv;
231
232 for (i = 0; i < len; i++)
233 writeb(buf[i], chip->IO_ADDR_W);
234 }
235
236 /**
237 * nand_read_buf - [DEFAULT] read chip data into buffer
238 * @mtd: MTD device structure
239 * @buf: buffer to store date
240 * @len: number of bytes to read
241 *
242 * Default read function for 8bit buswith
243 */
244 static void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
245 {
246 int i;
247 struct nand_chip *chip = mtd->priv;
248
249 for (i = 0; i < len; i++)
250 buf[i] = readb(chip->IO_ADDR_R);
251 }
252
253 /**
254 * nand_verify_buf - [DEFAULT] Verify chip data against buffer
255 * @mtd: MTD device structure
256 * @buf: buffer containing the data to compare
257 * @len: number of bytes to compare
258 *
259 * Default verify function for 8bit buswith
260 */
261 static int nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
262 {
263 int i;
264 struct nand_chip *chip = mtd->priv;
265
266 for (i = 0; i < len; i++)
267 if (buf[i] != readb(chip->IO_ADDR_R))
268 return -EFAULT;
269 return 0;
270 }
271
272 /**
273 * nand_write_buf16 - [DEFAULT] write buffer to chip
274 * @mtd: MTD device structure
275 * @buf: data buffer
276 * @len: number of bytes to write
277 *
278 * Default write function for 16bit buswith
279 */
280 static void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
281 {
282 int i;
283 struct nand_chip *chip = mtd->priv;
284 u16 *p = (u16 *) buf;
285 len >>= 1;
286
287 for (i = 0; i < len; i++)
288 writew(p[i], chip->IO_ADDR_W);
289
290 }
291
292 /**
293 * nand_read_buf16 - [DEFAULT] read chip data into buffer
294 * @mtd: MTD device structure
295 * @buf: buffer to store date
296 * @len: number of bytes to read
297 *
298 * Default read function for 16bit buswith
299 */
300 static void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
301 {
302 int i;
303 struct nand_chip *chip = mtd->priv;
304 u16 *p = (u16 *) buf;
305 len >>= 1;
306
307 for (i = 0; i < len; i++)
308 p[i] = readw(chip->IO_ADDR_R);
309 }
310
311 /**
312 * nand_verify_buf16 - [DEFAULT] Verify chip data against buffer
313 * @mtd: MTD device structure
314 * @buf: buffer containing the data to compare
315 * @len: number of bytes to compare
316 *
317 * Default verify function for 16bit buswith
318 */
319 static int nand_verify_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
320 {
321 int i;
322 struct nand_chip *chip = mtd->priv;
323 u16 *p = (u16 *) buf;
324 len >>= 1;
325
326 for (i = 0; i < len; i++)
327 if (p[i] != readw(chip->IO_ADDR_R))
328 return -EFAULT;
329
330 return 0;
331 }
332
333 /**
334 * nand_block_bad - [DEFAULT] Read bad block marker from the chip
335 * @mtd: MTD device structure
336 * @ofs: offset from device start
337 * @getchip: 0, if the chip is already selected
338 *
339 * Check, if the block is bad.
340 */
341 static int nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
342 {
343 int page, chipnr, res = 0;
344 struct nand_chip *chip = mtd->priv;
345 u16 bad;
346
347 if (chip->options & NAND_BBT_SCANLASTPAGE)
348 ofs += mtd->erasesize - mtd->writesize;
349
350 page = (int)(ofs >> chip->page_shift) & chip->pagemask;
351
352 if (getchip) {
353 chipnr = (int)(ofs >> chip->chip_shift);
354
355 nand_get_device(chip, mtd, FL_READING);
356
357 /* Select the NAND device */
358 chip->select_chip(mtd, chipnr);
359 }
360
361 if (chip->options & NAND_BUSWIDTH_16) {
362 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos & 0xFE,
363 page);
364 bad = cpu_to_le16(chip->read_word(mtd));
365 if (chip->badblockpos & 0x1)
366 bad >>= 8;
367 else
368 bad &= 0xFF;
369 } else {
370 chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
371 bad = chip->read_byte(mtd);
372 }
373
374 if (likely(chip->badblockbits == 8))
375 res = bad != 0xFF;
376 else
377 res = hweight8(bad) < chip->badblockbits;
378
379 if (getchip)
380 nand_release_device(mtd);
381
382 return res;
383 }
384
385 /**
386 * nand_default_block_markbad - [DEFAULT] mark a block bad
387 * @mtd: MTD device structure
388 * @ofs: offset from device start
389 *
390 * This is the default implementation, which can be overridden by
391 * a hardware specific driver.
392 */
393 static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
394 {
395 struct nand_chip *chip = mtd->priv;
396 uint8_t buf[2] = { 0, 0 };
397 int block, ret, i = 0;
398
399 if (chip->options & NAND_BBT_SCANLASTPAGE)
400 ofs += mtd->erasesize - mtd->writesize;
401
402 /* Get block number */
403 block = (int)(ofs >> chip->bbt_erase_shift);
404 if (chip->bbt)
405 chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
406
407 /* Do we have a flash based bad block table ? */
408 if (chip->options & NAND_USE_FLASH_BBT)
409 ret = nand_update_bbt(mtd, ofs);
410 else {
411 nand_get_device(chip, mtd, FL_WRITING);
412
413 /* Write to first two pages and to byte 1 and 6 if necessary.
414 * If we write to more than one location, the first error
415 * encountered quits the procedure. We write two bytes per
416 * location, so we dont have to mess with 16 bit access.
417 */
418 do {
419 chip->ops.len = chip->ops.ooblen = 2;
420 chip->ops.datbuf = NULL;
421 chip->ops.oobbuf = buf;
422 chip->ops.ooboffs = chip->badblockpos & ~0x01;
423
424 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
425
426 if (!ret && (chip->options & NAND_BBT_SCANBYTE1AND6)) {
427 chip->ops.ooboffs = NAND_SMALL_BADBLOCK_POS
428 & ~0x01;
429 ret = nand_do_write_oob(mtd, ofs, &chip->ops);
430 }
431 i++;
432 ofs += mtd->writesize;
433 } while (!ret && (chip->options & NAND_BBT_SCAN2NDPAGE) &&
434 i < 2);
435
436 nand_release_device(mtd);
437 }
438 if (!ret)
439 mtd->ecc_stats.badblocks++;
440
441 return ret;
442 }
443
444 /**
445 * nand_check_wp - [GENERIC] check if the chip is write protected
446 * @mtd: MTD device structure
447 * Check, if the device is write protected
448 *
449 * The function expects, that the device is already selected
450 */
451 static int nand_check_wp(struct mtd_info *mtd)
452 {
453 struct nand_chip *chip = mtd->priv;
454
455 /* broken xD cards report WP despite being writable */
456 if (chip->options & NAND_BROKEN_XD)
457 return 0;
458
459 /* Check the WP bit */
460 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
461 return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
462 }
463
464 /**
465 * nand_block_checkbad - [GENERIC] Check if a block is marked bad
466 * @mtd: MTD device structure
467 * @ofs: offset from device start
468 * @getchip: 0, if the chip is already selected
469 * @allowbbt: 1, if its allowed to access the bbt area
470 *
471 * Check, if the block is bad. Either by reading the bad block table or
472 * calling of the scan function.
473 */
474 static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int getchip,
475 int allowbbt)
476 {
477 struct nand_chip *chip = mtd->priv;
478
479 if (!chip->bbt)
480 return chip->block_bad(mtd, ofs, getchip);
481
482 /* Return info from the table */
483 return nand_isbad_bbt(mtd, ofs, allowbbt);
484 }
485
486 /**
487 * panic_nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
488 * @mtd: MTD device structure
489 * @timeo: Timeout
490 *
491 * Helper function for nand_wait_ready used when needing to wait in interrupt
492 * context.
493 */
494 static void panic_nand_wait_ready(struct mtd_info *mtd, unsigned long timeo)
495 {
496 struct nand_chip *chip = mtd->priv;
497 int i;
498
499 /* Wait for the device to get ready */
500 for (i = 0; i < timeo; i++) {
501 if (chip->dev_ready(mtd))
502 break;
503 touch_softlockup_watchdog();
504 mdelay(1);
505 }
506 }
507
508 /*
509 * Wait for the ready pin, after a command
510 * The timeout is catched later.
511 */
512 void nand_wait_ready(struct mtd_info *mtd)
513 {
514 struct nand_chip *chip = mtd->priv;
515 unsigned long timeo = jiffies + 2;
516
517 /* 400ms timeout */
518 if (in_interrupt() || oops_in_progress)
519 return panic_nand_wait_ready(mtd, 400);
520
521 led_trigger_event(nand_led_trigger, LED_FULL);
522 /* wait until command is processed or timeout occures */
523 do {
524 if (chip->dev_ready(mtd))
525 break;
526 touch_softlockup_watchdog();
527 } while (time_before(jiffies, timeo));
528 led_trigger_event(nand_led_trigger, LED_OFF);
529 }
530 EXPORT_SYMBOL_GPL(nand_wait_ready);
531
532 /**
533 * nand_command - [DEFAULT] Send command to NAND device
534 * @mtd: MTD device structure
535 * @command: the command to be sent
536 * @column: the column address for this command, -1 if none
537 * @page_addr: the page address for this command, -1 if none
538 *
539 * Send command to NAND device. This function is used for small page
540 * devices (256/512 Bytes per page)
541 */
542 static void nand_command(struct mtd_info *mtd, unsigned int command,
543 int column, int page_addr)
544 {
545 register struct nand_chip *chip = mtd->priv;
546 int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
547
548 /*
549 * Write out the command to the device.
550 */
551 if (command == NAND_CMD_SEQIN) {
552 int readcmd;
553
554 if (column >= mtd->writesize) {
555 /* OOB area */
556 column -= mtd->writesize;
557 readcmd = NAND_CMD_READOOB;
558 } else if (column < 256) {
559 /* First 256 bytes --> READ0 */
560 readcmd = NAND_CMD_READ0;
561 } else {
562 column -= 256;
563 readcmd = NAND_CMD_READ1;
564 }
565 chip->cmd_ctrl(mtd, readcmd, ctrl);
566 ctrl &= ~NAND_CTRL_CHANGE;
567 }
568 chip->cmd_ctrl(mtd, command, ctrl);
569
570 /*
571 * Address cycle, when necessary
572 */
573 ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
574 /* Serially input address */
575 if (column != -1) {
576 /* Adjust columns for 16 bit buswidth */
577 if (chip->options & NAND_BUSWIDTH_16)
578 column >>= 1;
579 chip->cmd_ctrl(mtd, column, ctrl);
580 ctrl &= ~NAND_CTRL_CHANGE;
581 }
582 if (page_addr != -1) {
583 chip->cmd_ctrl(mtd, page_addr, ctrl);
584 ctrl &= ~NAND_CTRL_CHANGE;
585 chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
586 /* One more address cycle for devices > 32MiB */
587 if (chip->chipsize > (32 << 20))
588 chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
589 }
590 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
591
592 /*
593 * program and erase have their own busy handlers
594 * status and sequential in needs no delay
595 */
596 switch (command) {
597
598 case NAND_CMD_PAGEPROG:
599 case NAND_CMD_ERASE1:
600 case NAND_CMD_ERASE2:
601 case NAND_CMD_SEQIN:
602 case NAND_CMD_STATUS:
603 return;
604
605 case NAND_CMD_RESET:
606 if (chip->dev_ready)
607 break;
608 udelay(chip->chip_delay);
609 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
610 NAND_CTRL_CLE | NAND_CTRL_CHANGE);
611 chip->cmd_ctrl(mtd,
612 NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
613 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
614 ;
615 return;
616
617 /* This applies to read commands */
618 default:
619 /*
620 * If we don't have access to the busy pin, we apply the given
621 * command delay
622 */
623 if (!chip->dev_ready) {
624 udelay(chip->chip_delay);
625 return;
626 }
627 }
628 /* Apply this short delay always to ensure that we do wait tWB in
629 * any case on any machine. */
630 ndelay(100);
631
632 nand_wait_ready(mtd);
633 }
634
635 /**
636 * nand_command_lp - [DEFAULT] Send command to NAND large page device
637 * @mtd: MTD device structure
638 * @command: the command to be sent
639 * @column: the column address for this command, -1 if none
640 * @page_addr: the page address for this command, -1 if none
641 *
642 * Send command to NAND device. This is the version for the new large page
643 * devices We dont have the separate regions as we have in the small page
644 * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
645 */
646 static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
647 int column, int page_addr)
648 {
649 register struct nand_chip *chip = mtd->priv;
650
651 /* Emulate NAND_CMD_READOOB */
652 if (command == NAND_CMD_READOOB) {
653 column += mtd->writesize;
654 command = NAND_CMD_READ0;
655 }
656
657 /* Command latch cycle */
658 chip->cmd_ctrl(mtd, command & 0xff,
659 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
660
661 if (column != -1 || page_addr != -1) {
662 int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
663
664 /* Serially input address */
665 if (column != -1) {
666 /* Adjust columns for 16 bit buswidth */
667 if (chip->options & NAND_BUSWIDTH_16)
668 column >>= 1;
669 chip->cmd_ctrl(mtd, column, ctrl);
670 ctrl &= ~NAND_CTRL_CHANGE;
671 chip->cmd_ctrl(mtd, column >> 8, ctrl);
672 }
673 if (page_addr != -1) {
674 chip->cmd_ctrl(mtd, page_addr, ctrl);
675 chip->cmd_ctrl(mtd, page_addr >> 8,
676 NAND_NCE | NAND_ALE);
677 /* One more address cycle for devices > 128MiB */
678 if (chip->chipsize > (128 << 20))
679 chip->cmd_ctrl(mtd, page_addr >> 16,
680 NAND_NCE | NAND_ALE);
681 }
682 }
683 chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
684
685 /*
686 * program and erase have their own busy handlers
687 * status, sequential in, and deplete1 need no delay
688 */
689 switch (command) {
690
691 case NAND_CMD_CACHEDPROG:
692 case NAND_CMD_PAGEPROG:
693 case NAND_CMD_ERASE1:
694 case NAND_CMD_ERASE2:
695 case NAND_CMD_SEQIN:
696 case NAND_CMD_RNDIN:
697 case NAND_CMD_STATUS:
698 case NAND_CMD_DEPLETE1:
699 return;
700
701 /*
702 * read error status commands require only a short delay
703 */
704 case NAND_CMD_STATUS_ERROR:
705 case NAND_CMD_STATUS_ERROR0:
706 case NAND_CMD_STATUS_ERROR1:
707 case NAND_CMD_STATUS_ERROR2:
708 case NAND_CMD_STATUS_ERROR3:
709 udelay(chip->chip_delay);
710 return;
711
712 case NAND_CMD_RESET:
713 if (chip->dev_ready)
714 break;
715 udelay(chip->chip_delay);
716 chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
717 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
718 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
719 NAND_NCE | NAND_CTRL_CHANGE);
720 while (!(chip->read_byte(mtd) & NAND_STATUS_READY))
721 ;
722 return;
723
724 case NAND_CMD_RNDOUT:
725 /* No ready / busy check necessary */
726 chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
727 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
728 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
729 NAND_NCE | NAND_CTRL_CHANGE);
730 return;
731
732 case NAND_CMD_READ0:
733 chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
734 NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
735 chip->cmd_ctrl(mtd, NAND_CMD_NONE,
736 NAND_NCE | NAND_CTRL_CHANGE);
737
738 /* This applies to read commands */
739 default:
740 /*
741 * If we don't have access to the busy pin, we apply the given
742 * command delay
743 */
744 if (!chip->dev_ready) {
745 udelay(chip->chip_delay);
746 return;
747 }
748 }
749
750 /* Apply this short delay always to ensure that we do wait tWB in
751 * any case on any machine. */
752 ndelay(100);
753
754 nand_wait_ready(mtd);
755 }
756
757 /**
758 * panic_nand_get_device - [GENERIC] Get chip for selected access
759 * @chip: the nand chip descriptor
760 * @mtd: MTD device structure
761 * @new_state: the state which is requested
762 *
763 * Used when in panic, no locks are taken.
764 */
765 static void panic_nand_get_device(struct nand_chip *chip,
766 struct mtd_info *mtd, int new_state)
767 {
768 /* Hardware controller shared among independend devices */
769 chip->controller->active = chip;
770 chip->state = new_state;
771 }
772
773 /**
774 * nand_get_device - [GENERIC] Get chip for selected access
775 * @chip: the nand chip descriptor
776 * @mtd: MTD device structure
777 * @new_state: the state which is requested
778 *
779 * Get the device and lock it for exclusive access
780 */
781 static int
782 nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state)
783 {
784 spinlock_t *lock = &chip->controller->lock;
785 wait_queue_head_t *wq = &chip->controller->wq;
786 DECLARE_WAITQUEUE(wait, current);
787 retry:
788 spin_lock(lock);
789
790 /* Hardware controller shared among independent devices */
791 if (!chip->controller->active)
792 chip->controller->active = chip;
793
794 if (chip->controller->active == chip && chip->state == FL_READY) {
795 chip->state = new_state;
796 spin_unlock(lock);
797 return 0;
798 }
799 if (new_state == FL_PM_SUSPENDED) {
800 if (chip->controller->active->state == FL_PM_SUSPENDED) {
801 chip->state = FL_PM_SUSPENDED;
802 spin_unlock(lock);
803 return 0;
804 }
805 }
806 set_current_state(TASK_UNINTERRUPTIBLE);
807 add_wait_queue(wq, &wait);
808 spin_unlock(lock);
809 schedule();
810 remove_wait_queue(wq, &wait);
811 goto retry;
812 }
813
814 /**
815 * panic_nand_wait - [GENERIC] wait until the command is done
816 * @mtd: MTD device structure
817 * @chip: NAND chip structure
818 * @timeo: Timeout
819 *
820 * Wait for command done. This is a helper function for nand_wait used when
821 * we are in interrupt context. May happen when in panic and trying to write
822 * an oops through mtdoops.
823 */
824 static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
825 unsigned long timeo)
826 {
827 int i;
828 for (i = 0; i < timeo; i++) {
829 if (chip->dev_ready) {
830 if (chip->dev_ready(mtd))
831 break;
832 } else {
833 if (chip->read_byte(mtd) & NAND_STATUS_READY)
834 break;
835 }
836 mdelay(1);
837 }
838 }
839
840 /**
841 * nand_wait - [DEFAULT] wait until the command is done
842 * @mtd: MTD device structure
843 * @chip: NAND chip structure
844 *
845 * Wait for command done. This applies to erase and program only
846 * Erase can take up to 400ms and program up to 20ms according to
847 * general NAND and SmartMedia specs
848 */
849 static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
850 {
851
852 unsigned long timeo = jiffies;
853 int status, state = chip->state;
854
855 if (state == FL_ERASING)
856 timeo += (HZ * 400) / 1000;
857 else
858 timeo += (HZ * 20) / 1000;
859
860 led_trigger_event(nand_led_trigger, LED_FULL);
861
862 /* Apply this short delay always to ensure that we do wait tWB in
863 * any case on any machine. */
864 ndelay(100);
865
866 if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
867 chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
868 else
869 chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
870
871 if (in_interrupt() || oops_in_progress)
872 panic_nand_wait(mtd, chip, timeo);
873 else {
874 while (time_before(jiffies, timeo)) {
875 if (chip->dev_ready) {
876 if (chip->dev_ready(mtd))
877 break;
878 } else {
879 if (chip->read_byte(mtd) & NAND_STATUS_READY)
880 break;
881 }
882 cond_resched();
883 }
884 }
885 led_trigger_event(nand_led_trigger, LED_OFF);
886
887 status = (int)chip->read_byte(mtd);
888 return status;
889 }
890
891 /**
892 * __nand_unlock - [REPLACEABLE] unlocks specified locked blocks
893 *
894 * @mtd: mtd info
895 * @ofs: offset to start unlock from
896 * @len: length to unlock
897 * @invert: when = 0, unlock the range of blocks within the lower and
898 * upper boundary address
899 * when = 1, unlock the range of blocks outside the boundaries
900 * of the lower and upper boundary address
901 *
902 * return - unlock status
903 */
904 static int __nand_unlock(struct mtd_info *mtd, loff_t ofs,
905 uint64_t len, int invert)
906 {
907 int ret = 0;
908 int status, page;
909 struct nand_chip *chip = mtd->priv;
910
911 /* Submit address of first page to unlock */
912 page = ofs >> chip->page_shift;
913 chip->cmdfunc(mtd, NAND_CMD_UNLOCK1, -1, page & chip->pagemask);
914
915 /* Submit address of last page to unlock */
916 page = (ofs + len) >> chip->page_shift;
917 chip->cmdfunc(mtd, NAND_CMD_UNLOCK2, -1,
918 (page | invert) & chip->pagemask);
919
920 /* Call wait ready function */
921 status = chip->waitfunc(mtd, chip);
922 udelay(1000);
923 /* See if device thinks it succeeded */
924 if (status & 0x01) {
925 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
926 __func__, status);
927 ret = -EIO;
928 }
929
930 return ret;
931 }
932
933 /**
934 * nand_unlock - [REPLACEABLE] unlocks specified locked blocks
935 *
936 * @mtd: mtd info
937 * @ofs: offset to start unlock from
938 * @len: length to unlock
939 *
940 * return - unlock status
941 */
942 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
943 {
944 int ret = 0;
945 int chipnr;
946 struct nand_chip *chip = mtd->priv;
947
948 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
949 __func__, (unsigned long long)ofs, len);
950
951 if (check_offs_len(mtd, ofs, len))
952 ret = -EINVAL;
953
954 /* Align to last block address if size addresses end of the device */
955 if (ofs + len == mtd->size)
956 len -= mtd->erasesize;
957
958 nand_get_device(chip, mtd, FL_UNLOCKING);
959
960 /* Shift to get chip number */
961 chipnr = ofs >> chip->chip_shift;
962
963 chip->select_chip(mtd, chipnr);
964
965 /* Check, if it is write protected */
966 if (nand_check_wp(mtd)) {
967 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
968 __func__);
969 ret = -EIO;
970 goto out;
971 }
972
973 ret = __nand_unlock(mtd, ofs, len, 0);
974
975 out:
976 nand_release_device(mtd);
977
978 return ret;
979 }
980 EXPORT_SYMBOL(nand_unlock);
981
982 /**
983 * nand_lock - [REPLACEABLE] locks all blocks present in the device
984 *
985 * @mtd: mtd info
986 * @ofs: offset to start unlock from
987 * @len: length to unlock
988 *
989 * return - lock status
990 *
991 * This feature is not supported in many NAND parts. 'Micron' NAND parts
992 * do have this feature, but it allows only to lock all blocks, not for
993 * specified range for block.
994 *
995 * Implementing 'lock' feature by making use of 'unlock', for now.
996 */
997 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
998 {
999 int ret = 0;
1000 int chipnr, status, page;
1001 struct nand_chip *chip = mtd->priv;
1002
1003 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
1004 __func__, (unsigned long long)ofs, len);
1005
1006 if (check_offs_len(mtd, ofs, len))
1007 ret = -EINVAL;
1008
1009 nand_get_device(chip, mtd, FL_LOCKING);
1010
1011 /* Shift to get chip number */
1012 chipnr = ofs >> chip->chip_shift;
1013
1014 chip->select_chip(mtd, chipnr);
1015
1016 /* Check, if it is write protected */
1017 if (nand_check_wp(mtd)) {
1018 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
1019 __func__);
1020 status = MTD_ERASE_FAILED;
1021 ret = -EIO;
1022 goto out;
1023 }
1024
1025 /* Submit address of first page to lock */
1026 page = ofs >> chip->page_shift;
1027 chip->cmdfunc(mtd, NAND_CMD_LOCK, -1, page & chip->pagemask);
1028
1029 /* Call wait ready function */
1030 status = chip->waitfunc(mtd, chip);
1031 udelay(1000);
1032 /* See if device thinks it succeeded */
1033 if (status & 0x01) {
1034 DEBUG(MTD_DEBUG_LEVEL0, "%s: Error status = 0x%08x\n",
1035 __func__, status);
1036 ret = -EIO;
1037 goto out;
1038 }
1039
1040 ret = __nand_unlock(mtd, ofs, len, 0x1);
1041
1042 out:
1043 nand_release_device(mtd);
1044
1045 return ret;
1046 }
1047 EXPORT_SYMBOL(nand_lock);
1048
1049 /**
1050 * nand_read_page_raw - [Intern] read raw page data without ecc
1051 * @mtd: mtd info structure
1052 * @chip: nand chip info structure
1053 * @buf: buffer to store read data
1054 * @page: page number to read
1055 *
1056 * Not for syndrome calculating ecc controllers, which use a special oob layout
1057 */
1058 static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1059 uint8_t *buf, int page)
1060 {
1061 chip->read_buf(mtd, buf, mtd->writesize);
1062 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1063 return 0;
1064 }
1065
1066 /**
1067 * nand_read_page_raw_syndrome - [Intern] read raw page data without ecc
1068 * @mtd: mtd info structure
1069 * @chip: nand chip info structure
1070 * @buf: buffer to store read data
1071 * @page: page number to read
1072 *
1073 * We need a special oob layout and handling even when OOB isn't used.
1074 */
1075 static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
1076 struct nand_chip *chip,
1077 uint8_t *buf, int page)
1078 {
1079 int eccsize = chip->ecc.size;
1080 int eccbytes = chip->ecc.bytes;
1081 uint8_t *oob = chip->oob_poi;
1082 int steps, size;
1083
1084 for (steps = chip->ecc.steps; steps > 0; steps--) {
1085 chip->read_buf(mtd, buf, eccsize);
1086 buf += eccsize;
1087
1088 if (chip->ecc.prepad) {
1089 chip->read_buf(mtd, oob, chip->ecc.prepad);
1090 oob += chip->ecc.prepad;
1091 }
1092
1093 chip->read_buf(mtd, oob, eccbytes);
1094 oob += eccbytes;
1095
1096 if (chip->ecc.postpad) {
1097 chip->read_buf(mtd, oob, chip->ecc.postpad);
1098 oob += chip->ecc.postpad;
1099 }
1100 }
1101
1102 size = mtd->oobsize - (oob - chip->oob_poi);
1103 if (size)
1104 chip->read_buf(mtd, oob, size);
1105
1106 return 0;
1107 }
1108
1109 /**
1110 * nand_read_page_swecc - [REPLACABLE] software ecc based page read function
1111 * @mtd: mtd info structure
1112 * @chip: nand chip info structure
1113 * @buf: buffer to store read data
1114 * @page: page number to read
1115 */
1116 static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1117 uint8_t *buf, int page)
1118 {
1119 int i, eccsize = chip->ecc.size;
1120 int eccbytes = chip->ecc.bytes;
1121 int eccsteps = chip->ecc.steps;
1122 uint8_t *p = buf;
1123 uint8_t *ecc_calc = chip->buffers->ecccalc;
1124 uint8_t *ecc_code = chip->buffers->ecccode;
1125 uint32_t *eccpos = chip->ecc.layout->eccpos;
1126
1127 chip->ecc.read_page_raw(mtd, chip, buf, page);
1128
1129 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1130 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1131
1132 for (i = 0; i < chip->ecc.total; i++)
1133 ecc_code[i] = chip->oob_poi[eccpos[i]];
1134
1135 eccsteps = chip->ecc.steps;
1136 p = buf;
1137
1138 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1139 int stat;
1140
1141 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1142 if (stat < 0)
1143 mtd->ecc_stats.failed++;
1144 else
1145 mtd->ecc_stats.corrected += stat;
1146 }
1147 return 0;
1148 }
1149
1150 /**
1151 * nand_read_subpage - [REPLACABLE] software ecc based sub-page read function
1152 * @mtd: mtd info structure
1153 * @chip: nand chip info structure
1154 * @data_offs: offset of requested data within the page
1155 * @readlen: data length
1156 * @bufpoi: buffer to store read data
1157 */
1158 static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
1159 uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi)
1160 {
1161 int start_step, end_step, num_steps;
1162 uint32_t *eccpos = chip->ecc.layout->eccpos;
1163 uint8_t *p;
1164 int data_col_addr, i, gaps = 0;
1165 int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
1166 int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
1167 int index = 0;
1168
1169 /* Column address wihin the page aligned to ECC size (256bytes). */
1170 start_step = data_offs / chip->ecc.size;
1171 end_step = (data_offs + readlen - 1) / chip->ecc.size;
1172 num_steps = end_step - start_step + 1;
1173
1174 /* Data size aligned to ECC ecc.size*/
1175 datafrag_len = num_steps * chip->ecc.size;
1176 eccfrag_len = num_steps * chip->ecc.bytes;
1177
1178 data_col_addr = start_step * chip->ecc.size;
1179 /* If we read not a page aligned data */
1180 if (data_col_addr != 0)
1181 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
1182
1183 p = bufpoi + data_col_addr;
1184 chip->read_buf(mtd, p, datafrag_len);
1185
1186 /* Calculate ECC */
1187 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
1188 chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
1189
1190 /* The performance is faster if to position offsets
1191 according to ecc.pos. Let make sure here that
1192 there are no gaps in ecc positions */
1193 for (i = 0; i < eccfrag_len - 1; i++) {
1194 if (eccpos[i + start_step * chip->ecc.bytes] + 1 !=
1195 eccpos[i + start_step * chip->ecc.bytes + 1]) {
1196 gaps = 1;
1197 break;
1198 }
1199 }
1200 if (gaps) {
1201 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1202 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1203 } else {
1204 /* send the command to read the particular ecc bytes */
1205 /* take care about buswidth alignment in read_buf */
1206 index = start_step * chip->ecc.bytes;
1207
1208 aligned_pos = eccpos[index] & ~(busw - 1);
1209 aligned_len = eccfrag_len;
1210 if (eccpos[index] & (busw - 1))
1211 aligned_len++;
1212 if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
1213 aligned_len++;
1214
1215 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1216 mtd->writesize + aligned_pos, -1);
1217 chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
1218 }
1219
1220 for (i = 0; i < eccfrag_len; i++)
1221 chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
1222
1223 p = bufpoi + data_col_addr;
1224 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
1225 int stat;
1226
1227 stat = chip->ecc.correct(mtd, p,
1228 &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
1229 if (stat < 0)
1230 mtd->ecc_stats.failed++;
1231 else
1232 mtd->ecc_stats.corrected += stat;
1233 }
1234 return 0;
1235 }
1236
1237 /**
1238 * nand_read_page_hwecc - [REPLACABLE] hardware ecc based page read function
1239 * @mtd: mtd info structure
1240 * @chip: nand chip info structure
1241 * @buf: buffer to store read data
1242 * @page: page number to read
1243 *
1244 * Not for syndrome calculating ecc controllers which need a special oob layout
1245 */
1246 static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1247 uint8_t *buf, int page)
1248 {
1249 int i, eccsize = chip->ecc.size;
1250 int eccbytes = chip->ecc.bytes;
1251 int eccsteps = chip->ecc.steps;
1252 uint8_t *p = buf;
1253 uint8_t *ecc_calc = chip->buffers->ecccalc;
1254 uint8_t *ecc_code = chip->buffers->ecccode;
1255 uint32_t *eccpos = chip->ecc.layout->eccpos;
1256
1257 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1258 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1259 chip->read_buf(mtd, p, eccsize);
1260 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1261 }
1262 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1263
1264 for (i = 0; i < chip->ecc.total; i++)
1265 ecc_code[i] = chip->oob_poi[eccpos[i]];
1266
1267 eccsteps = chip->ecc.steps;
1268 p = buf;
1269
1270 for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1271 int stat;
1272
1273 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
1274 if (stat < 0)
1275 mtd->ecc_stats.failed++;
1276 else
1277 mtd->ecc_stats.corrected += stat;
1278 }
1279 return 0;
1280 }
1281
1282 /**
1283 * nand_read_page_hwecc_oob_first - [REPLACABLE] hw ecc, read oob first
1284 * @mtd: mtd info structure
1285 * @chip: nand chip info structure
1286 * @buf: buffer to store read data
1287 * @page: page number to read
1288 *
1289 * Hardware ECC for large page chips, require OOB to be read first.
1290 * For this ECC mode, the write_page method is re-used from ECC_HW.
1291 * These methods read/write ECC from the OOB area, unlike the
1292 * ECC_HW_SYNDROME support with multiple ECC steps, follows the
1293 * "infix ECC" scheme and reads/writes ECC from the data area, by
1294 * overwriting the NAND manufacturer bad block markings.
1295 */
1296 static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
1297 struct nand_chip *chip, uint8_t *buf, int page)
1298 {
1299 int i, eccsize = chip->ecc.size;
1300 int eccbytes = chip->ecc.bytes;
1301 int eccsteps = chip->ecc.steps;
1302 uint8_t *p = buf;
1303 uint8_t *ecc_code = chip->buffers->ecccode;
1304 uint32_t *eccpos = chip->ecc.layout->eccpos;
1305 uint8_t *ecc_calc = chip->buffers->ecccalc;
1306
1307 /* Read the OOB area first */
1308 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1309 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1310 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
1311
1312 for (i = 0; i < chip->ecc.total; i++)
1313 ecc_code[i] = chip->oob_poi[eccpos[i]];
1314
1315 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1316 int stat;
1317
1318 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1319 chip->read_buf(mtd, p, eccsize);
1320 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1321
1322 stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
1323 if (stat < 0)
1324 mtd->ecc_stats.failed++;
1325 else
1326 mtd->ecc_stats.corrected += stat;
1327 }
1328 return 0;
1329 }
1330
1331 /**
1332 * nand_read_page_syndrome - [REPLACABLE] hardware ecc syndrom based page read
1333 * @mtd: mtd info structure
1334 * @chip: nand chip info structure
1335 * @buf: buffer to store read data
1336 * @page: page number to read
1337 *
1338 * The hw generator calculates the error syndrome automatically. Therefor
1339 * we need a special oob layout and handling.
1340 */
1341 static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1342 uint8_t *buf, int page)
1343 {
1344 int i, eccsize = chip->ecc.size;
1345 int eccbytes = chip->ecc.bytes;
1346 int eccsteps = chip->ecc.steps;
1347 uint8_t *p = buf;
1348 uint8_t *oob = chip->oob_poi;
1349
1350 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1351 int stat;
1352
1353 chip->ecc.hwctl(mtd, NAND_ECC_READ);
1354 chip->read_buf(mtd, p, eccsize);
1355
1356 if (chip->ecc.prepad) {
1357 chip->read_buf(mtd, oob, chip->ecc.prepad);
1358 oob += chip->ecc.prepad;
1359 }
1360
1361 chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
1362 chip->read_buf(mtd, oob, eccbytes);
1363 stat = chip->ecc.correct(mtd, p, oob, NULL);
1364
1365 if (stat < 0)
1366 mtd->ecc_stats.failed++;
1367 else
1368 mtd->ecc_stats.corrected += stat;
1369
1370 oob += eccbytes;
1371
1372 if (chip->ecc.postpad) {
1373 chip->read_buf(mtd, oob, chip->ecc.postpad);
1374 oob += chip->ecc.postpad;
1375 }
1376 }
1377
1378 /* Calculate remaining oob bytes */
1379 i = mtd->oobsize - (oob - chip->oob_poi);
1380 if (i)
1381 chip->read_buf(mtd, oob, i);
1382
1383 return 0;
1384 }
1385
1386 /**
1387 * nand_transfer_oob - [Internal] Transfer oob to client buffer
1388 * @chip: nand chip structure
1389 * @oob: oob destination address
1390 * @ops: oob ops structure
1391 * @len: size of oob to transfer
1392 */
1393 static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
1394 struct mtd_oob_ops *ops, size_t len)
1395 {
1396 switch (ops->mode) {
1397
1398 case MTD_OOB_PLACE:
1399 case MTD_OOB_RAW:
1400 memcpy(oob, chip->oob_poi + ops->ooboffs, len);
1401 return oob + len;
1402
1403 case MTD_OOB_AUTO: {
1404 struct nand_oobfree *free = chip->ecc.layout->oobfree;
1405 uint32_t boffs = 0, roffs = ops->ooboffs;
1406 size_t bytes = 0;
1407
1408 for (; free->length && len; free++, len -= bytes) {
1409 /* Read request not from offset 0 ? */
1410 if (unlikely(roffs)) {
1411 if (roffs >= free->length) {
1412 roffs -= free->length;
1413 continue;
1414 }
1415 boffs = free->offset + roffs;
1416 bytes = min_t(size_t, len,
1417 (free->length - roffs));
1418 roffs = 0;
1419 } else {
1420 bytes = min_t(size_t, len, free->length);
1421 boffs = free->offset;
1422 }
1423 memcpy(oob, chip->oob_poi + boffs, bytes);
1424 oob += bytes;
1425 }
1426 return oob;
1427 }
1428 default:
1429 BUG();
1430 }
1431 return NULL;
1432 }
1433
1434 /**
1435 * nand_do_read_ops - [Internal] Read data with ECC
1436 *
1437 * @mtd: MTD device structure
1438 * @from: offset to read from
1439 * @ops: oob ops structure
1440 *
1441 * Internal function. Called with chip held.
1442 */
1443 static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
1444 struct mtd_oob_ops *ops)
1445 {
1446 int chipnr, page, realpage, col, bytes, aligned;
1447 struct nand_chip *chip = mtd->priv;
1448 struct mtd_ecc_stats stats;
1449 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1450 int sndcmd = 1;
1451 int ret = 0;
1452 uint32_t readlen = ops->len;
1453 uint32_t oobreadlen = ops->ooblen;
1454 uint32_t max_oobsize = ops->mode == MTD_OOB_AUTO ?
1455 mtd->oobavail : mtd->oobsize;
1456
1457 uint8_t *bufpoi, *oob, *buf;
1458
1459 stats = mtd->ecc_stats;
1460
1461 chipnr = (int)(from >> chip->chip_shift);
1462 chip->select_chip(mtd, chipnr);
1463
1464 realpage = (int)(from >> chip->page_shift);
1465 page = realpage & chip->pagemask;
1466
1467 col = (int)(from & (mtd->writesize - 1));
1468
1469 buf = ops->datbuf;
1470 oob = ops->oobbuf;
1471
1472 while (1) {
1473 bytes = min(mtd->writesize - col, readlen);
1474 aligned = (bytes == mtd->writesize);
1475
1476 /* Is the current page in the buffer ? */
1477 if (realpage != chip->pagebuf || oob) {
1478 bufpoi = aligned ? buf : chip->buffers->databuf;
1479
1480 if (likely(sndcmd)) {
1481 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1482 sndcmd = 0;
1483 }
1484
1485 /* Now read the page into the buffer */
1486 if (unlikely(ops->mode == MTD_OOB_RAW))
1487 ret = chip->ecc.read_page_raw(mtd, chip,
1488 bufpoi, page);
1489 else if (!aligned && NAND_SUBPAGE_READ(chip) && !oob)
1490 ret = chip->ecc.read_subpage(mtd, chip,
1491 col, bytes, bufpoi);
1492 else
1493 ret = chip->ecc.read_page(mtd, chip, bufpoi,
1494 page);
1495 if (ret < 0)
1496 break;
1497
1498 /* Transfer not aligned data */
1499 if (!aligned) {
1500 if (!NAND_SUBPAGE_READ(chip) && !oob &&
1501 !(mtd->ecc_stats.failed - stats.failed))
1502 chip->pagebuf = realpage;
1503 memcpy(buf, chip->buffers->databuf + col, bytes);
1504 }
1505
1506 buf += bytes;
1507
1508 if (unlikely(oob)) {
1509
1510 int toread = min(oobreadlen, max_oobsize);
1511
1512 if (toread) {
1513 oob = nand_transfer_oob(chip,
1514 oob, ops, toread);
1515 oobreadlen -= toread;
1516 }
1517 }
1518
1519 if (!(chip->options & NAND_NO_READRDY)) {
1520 /*
1521 * Apply delay or wait for ready/busy pin. Do
1522 * this before the AUTOINCR check, so no
1523 * problems arise if a chip which does auto
1524 * increment is marked as NOAUTOINCR by the
1525 * board driver.
1526 */
1527 if (!chip->dev_ready)
1528 udelay(chip->chip_delay);
1529 else
1530 nand_wait_ready(mtd);
1531 }
1532 } else {
1533 memcpy(buf, chip->buffers->databuf + col, bytes);
1534 buf += bytes;
1535 }
1536
1537 readlen -= bytes;
1538
1539 if (!readlen)
1540 break;
1541
1542 /* For subsequent reads align to page boundary. */
1543 col = 0;
1544 /* Increment page address */
1545 realpage++;
1546
1547 page = realpage & chip->pagemask;
1548 /* Check, if we cross a chip boundary */
1549 if (!page) {
1550 chipnr++;
1551 chip->select_chip(mtd, -1);
1552 chip->select_chip(mtd, chipnr);
1553 }
1554
1555 /* Check, if the chip supports auto page increment
1556 * or if we have hit a block boundary.
1557 */
1558 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1559 sndcmd = 1;
1560 }
1561
1562 ops->retlen = ops->len - (size_t) readlen;
1563 if (oob)
1564 ops->oobretlen = ops->ooblen - oobreadlen;
1565
1566 if (ret)
1567 return ret;
1568
1569 if (mtd->ecc_stats.failed - stats.failed)
1570 return -EBADMSG;
1571
1572 return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
1573 }
1574
1575 /**
1576 * nand_read - [MTD Interface] MTD compatibility function for nand_do_read_ecc
1577 * @mtd: MTD device structure
1578 * @from: offset to read from
1579 * @len: number of bytes to read
1580 * @retlen: pointer to variable to store the number of read bytes
1581 * @buf: the databuffer to put data
1582 *
1583 * Get hold of the chip and call nand_do_read
1584 */
1585 static int nand_read(struct mtd_info *mtd, loff_t from, size_t len,
1586 size_t *retlen, uint8_t *buf)
1587 {
1588 struct nand_chip *chip = mtd->priv;
1589 int ret;
1590
1591 /* Do not allow reads past end of device */
1592 if ((from + len) > mtd->size)
1593 return -EINVAL;
1594 if (!len)
1595 return 0;
1596
1597 nand_get_device(chip, mtd, FL_READING);
1598
1599 chip->ops.len = len;
1600 chip->ops.datbuf = buf;
1601 chip->ops.oobbuf = NULL;
1602
1603 ret = nand_do_read_ops(mtd, from, &chip->ops);
1604
1605 *retlen = chip->ops.retlen;
1606
1607 nand_release_device(mtd);
1608
1609 return ret;
1610 }
1611
1612 /**
1613 * nand_read_oob_std - [REPLACABLE] the most common OOB data read function
1614 * @mtd: mtd info structure
1615 * @chip: nand chip info structure
1616 * @page: page number to read
1617 * @sndcmd: flag whether to issue read command or not
1618 */
1619 static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1620 int page, int sndcmd)
1621 {
1622 if (sndcmd) {
1623 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
1624 sndcmd = 0;
1625 }
1626 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
1627 return sndcmd;
1628 }
1629
1630 /**
1631 * nand_read_oob_syndrome - [REPLACABLE] OOB data read function for HW ECC
1632 * with syndromes
1633 * @mtd: mtd info structure
1634 * @chip: nand chip info structure
1635 * @page: page number to read
1636 * @sndcmd: flag whether to issue read command or not
1637 */
1638 static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1639 int page, int sndcmd)
1640 {
1641 uint8_t *buf = chip->oob_poi;
1642 int length = mtd->oobsize;
1643 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1644 int eccsize = chip->ecc.size;
1645 uint8_t *bufpoi = buf;
1646 int i, toread, sndrnd = 0, pos;
1647
1648 chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
1649 for (i = 0; i < chip->ecc.steps; i++) {
1650 if (sndrnd) {
1651 pos = eccsize + i * (eccsize + chunk);
1652 if (mtd->writesize > 512)
1653 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
1654 else
1655 chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
1656 } else
1657 sndrnd = 1;
1658 toread = min_t(int, length, chunk);
1659 chip->read_buf(mtd, bufpoi, toread);
1660 bufpoi += toread;
1661 length -= toread;
1662 }
1663 if (length > 0)
1664 chip->read_buf(mtd, bufpoi, length);
1665
1666 return 1;
1667 }
1668
1669 /**
1670 * nand_write_oob_std - [REPLACABLE] the most common OOB data write function
1671 * @mtd: mtd info structure
1672 * @chip: nand chip info structure
1673 * @page: page number to write
1674 */
1675 static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
1676 int page)
1677 {
1678 int status = 0;
1679 const uint8_t *buf = chip->oob_poi;
1680 int length = mtd->oobsize;
1681
1682 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
1683 chip->write_buf(mtd, buf, length);
1684 /* Send command to program the OOB data */
1685 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1686
1687 status = chip->waitfunc(mtd, chip);
1688
1689 return status & NAND_STATUS_FAIL ? -EIO : 0;
1690 }
1691
1692 /**
1693 * nand_write_oob_syndrome - [REPLACABLE] OOB data write function for HW ECC
1694 * with syndrome - only for large page flash !
1695 * @mtd: mtd info structure
1696 * @chip: nand chip info structure
1697 * @page: page number to write
1698 */
1699 static int nand_write_oob_syndrome(struct mtd_info *mtd,
1700 struct nand_chip *chip, int page)
1701 {
1702 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
1703 int eccsize = chip->ecc.size, length = mtd->oobsize;
1704 int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
1705 const uint8_t *bufpoi = chip->oob_poi;
1706
1707 /*
1708 * data-ecc-data-ecc ... ecc-oob
1709 * or
1710 * data-pad-ecc-pad-data-pad .... ecc-pad-oob
1711 */
1712 if (!chip->ecc.prepad && !chip->ecc.postpad) {
1713 pos = steps * (eccsize + chunk);
1714 steps = 0;
1715 } else
1716 pos = eccsize;
1717
1718 chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
1719 for (i = 0; i < steps; i++) {
1720 if (sndcmd) {
1721 if (mtd->writesize <= 512) {
1722 uint32_t fill = 0xFFFFFFFF;
1723
1724 len = eccsize;
1725 while (len > 0) {
1726 int num = min_t(int, len, 4);
1727 chip->write_buf(mtd, (uint8_t *)&fill,
1728 num);
1729 len -= num;
1730 }
1731 } else {
1732 pos = eccsize + i * (eccsize + chunk);
1733 chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
1734 }
1735 } else
1736 sndcmd = 1;
1737 len = min_t(int, length, chunk);
1738 chip->write_buf(mtd, bufpoi, len);
1739 bufpoi += len;
1740 length -= len;
1741 }
1742 if (length > 0)
1743 chip->write_buf(mtd, bufpoi, length);
1744
1745 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
1746 status = chip->waitfunc(mtd, chip);
1747
1748 return status & NAND_STATUS_FAIL ? -EIO : 0;
1749 }
1750
1751 /**
1752 * nand_do_read_oob - [Intern] NAND read out-of-band
1753 * @mtd: MTD device structure
1754 * @from: offset to read from
1755 * @ops: oob operations description structure
1756 *
1757 * NAND read out-of-band data from the spare area
1758 */
1759 static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
1760 struct mtd_oob_ops *ops)
1761 {
1762 int page, realpage, chipnr, sndcmd = 1;
1763 struct nand_chip *chip = mtd->priv;
1764 int blkcheck = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
1765 int readlen = ops->ooblen;
1766 int len;
1767 uint8_t *buf = ops->oobbuf;
1768
1769 DEBUG(MTD_DEBUG_LEVEL3, "%s: from = 0x%08Lx, len = %i\n",
1770 __func__, (unsigned long long)from, readlen);
1771
1772 if (ops->mode == MTD_OOB_AUTO)
1773 len = chip->ecc.layout->oobavail;
1774 else
1775 len = mtd->oobsize;
1776
1777 if (unlikely(ops->ooboffs >= len)) {
1778 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start read "
1779 "outside oob\n", __func__);
1780 return -EINVAL;
1781 }
1782
1783 /* Do not allow reads past end of device */
1784 if (unlikely(from >= mtd->size ||
1785 ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
1786 (from >> chip->page_shift)) * len)) {
1787 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read beyond end "
1788 "of device\n", __func__);
1789 return -EINVAL;
1790 }
1791
1792 chipnr = (int)(from >> chip->chip_shift);
1793 chip->select_chip(mtd, chipnr);
1794
1795 /* Shift to get page */
1796 realpage = (int)(from >> chip->page_shift);
1797 page = realpage & chip->pagemask;
1798
1799 while (1) {
1800 sndcmd = chip->ecc.read_oob(mtd, chip, page, sndcmd);
1801
1802 len = min(len, readlen);
1803 buf = nand_transfer_oob(chip, buf, ops, len);
1804
1805 if (!(chip->options & NAND_NO_READRDY)) {
1806 /*
1807 * Apply delay or wait for ready/busy pin. Do this
1808 * before the AUTOINCR check, so no problems arise if a
1809 * chip which does auto increment is marked as
1810 * NOAUTOINCR by the board driver.
1811 */
1812 if (!chip->dev_ready)
1813 udelay(chip->chip_delay);
1814 else
1815 nand_wait_ready(mtd);
1816 }
1817
1818 readlen -= len;
1819 if (!readlen)
1820 break;
1821
1822 /* Increment page address */
1823 realpage++;
1824
1825 page = realpage & chip->pagemask;
1826 /* Check, if we cross a chip boundary */
1827 if (!page) {
1828 chipnr++;
1829 chip->select_chip(mtd, -1);
1830 chip->select_chip(mtd, chipnr);
1831 }
1832
1833 /* Check, if the chip supports auto page increment
1834 * or if we have hit a block boundary.
1835 */
1836 if (!NAND_CANAUTOINCR(chip) || !(page & blkcheck))
1837 sndcmd = 1;
1838 }
1839
1840 ops->oobretlen = ops->ooblen;
1841 return 0;
1842 }
1843
1844 /**
1845 * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
1846 * @mtd: MTD device structure
1847 * @from: offset to read from
1848 * @ops: oob operation description structure
1849 *
1850 * NAND read data and/or out-of-band data
1851 */
1852 static int nand_read_oob(struct mtd_info *mtd, loff_t from,
1853 struct mtd_oob_ops *ops)
1854 {
1855 struct nand_chip *chip = mtd->priv;
1856 int ret = -ENOTSUPP;
1857
1858 ops->retlen = 0;
1859
1860 /* Do not allow reads past end of device */
1861 if (ops->datbuf && (from + ops->len) > mtd->size) {
1862 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt read "
1863 "beyond end of device\n", __func__);
1864 return -EINVAL;
1865 }
1866
1867 nand_get_device(chip, mtd, FL_READING);
1868
1869 switch (ops->mode) {
1870 case MTD_OOB_PLACE:
1871 case MTD_OOB_AUTO:
1872 case MTD_OOB_RAW:
1873 break;
1874
1875 default:
1876 goto out;
1877 }
1878
1879 if (!ops->datbuf)
1880 ret = nand_do_read_oob(mtd, from, ops);
1881 else
1882 ret = nand_do_read_ops(mtd, from, ops);
1883
1884 out:
1885 nand_release_device(mtd);
1886 return ret;
1887 }
1888
1889
1890 /**
1891 * nand_write_page_raw - [Intern] raw page write function
1892 * @mtd: mtd info structure
1893 * @chip: nand chip info structure
1894 * @buf: data buffer
1895 *
1896 * Not for syndrome calculating ecc controllers, which use a special oob layout
1897 */
1898 static void nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1899 const uint8_t *buf)
1900 {
1901 chip->write_buf(mtd, buf, mtd->writesize);
1902 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1903 }
1904
1905 /**
1906 * nand_write_page_raw_syndrome - [Intern] raw page write function
1907 * @mtd: mtd info structure
1908 * @chip: nand chip info structure
1909 * @buf: data buffer
1910 *
1911 * We need a special oob layout and handling even when ECC isn't checked.
1912 */
1913 static void nand_write_page_raw_syndrome(struct mtd_info *mtd,
1914 struct nand_chip *chip,
1915 const uint8_t *buf)
1916 {
1917 int eccsize = chip->ecc.size;
1918 int eccbytes = chip->ecc.bytes;
1919 uint8_t *oob = chip->oob_poi;
1920 int steps, size;
1921
1922 for (steps = chip->ecc.steps; steps > 0; steps--) {
1923 chip->write_buf(mtd, buf, eccsize);
1924 buf += eccsize;
1925
1926 if (chip->ecc.prepad) {
1927 chip->write_buf(mtd, oob, chip->ecc.prepad);
1928 oob += chip->ecc.prepad;
1929 }
1930
1931 chip->read_buf(mtd, oob, eccbytes);
1932 oob += eccbytes;
1933
1934 if (chip->ecc.postpad) {
1935 chip->write_buf(mtd, oob, chip->ecc.postpad);
1936 oob += chip->ecc.postpad;
1937 }
1938 }
1939
1940 size = mtd->oobsize - (oob - chip->oob_poi);
1941 if (size)
1942 chip->write_buf(mtd, oob, size);
1943 }
1944 /**
1945 * nand_write_page_swecc - [REPLACABLE] software ecc based page write function
1946 * @mtd: mtd info structure
1947 * @chip: nand chip info structure
1948 * @buf: data buffer
1949 */
1950 static void nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
1951 const uint8_t *buf)
1952 {
1953 int i, eccsize = chip->ecc.size;
1954 int eccbytes = chip->ecc.bytes;
1955 int eccsteps = chip->ecc.steps;
1956 uint8_t *ecc_calc = chip->buffers->ecccalc;
1957 const uint8_t *p = buf;
1958 uint32_t *eccpos = chip->ecc.layout->eccpos;
1959
1960 /* Software ecc calculation */
1961 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
1962 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1963
1964 for (i = 0; i < chip->ecc.total; i++)
1965 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1966
1967 chip->ecc.write_page_raw(mtd, chip, buf);
1968 }
1969
1970 /**
1971 * nand_write_page_hwecc - [REPLACABLE] hardware ecc based page write function
1972 * @mtd: mtd info structure
1973 * @chip: nand chip info structure
1974 * @buf: data buffer
1975 */
1976 static void nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
1977 const uint8_t *buf)
1978 {
1979 int i, eccsize = chip->ecc.size;
1980 int eccbytes = chip->ecc.bytes;
1981 int eccsteps = chip->ecc.steps;
1982 uint8_t *ecc_calc = chip->buffers->ecccalc;
1983 const uint8_t *p = buf;
1984 uint32_t *eccpos = chip->ecc.layout->eccpos;
1985
1986 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
1987 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
1988 chip->write_buf(mtd, p, eccsize);
1989 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
1990 }
1991
1992 for (i = 0; i < chip->ecc.total; i++)
1993 chip->oob_poi[eccpos[i]] = ecc_calc[i];
1994
1995 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1996 }
1997
1998 /**
1999 * nand_write_page_syndrome - [REPLACABLE] hardware ecc syndrom based page write
2000 * @mtd: mtd info structure
2001 * @chip: nand chip info structure
2002 * @buf: data buffer
2003 *
2004 * The hw generator calculates the error syndrome automatically. Therefor
2005 * we need a special oob layout and handling.
2006 */
2007 static void nand_write_page_syndrome(struct mtd_info *mtd,
2008 struct nand_chip *chip, const uint8_t *buf)
2009 {
2010 int i, eccsize = chip->ecc.size;
2011 int eccbytes = chip->ecc.bytes;
2012 int eccsteps = chip->ecc.steps;
2013 const uint8_t *p = buf;
2014 uint8_t *oob = chip->oob_poi;
2015
2016 for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
2017
2018 chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
2019 chip->write_buf(mtd, p, eccsize);
2020
2021 if (chip->ecc.prepad) {
2022 chip->write_buf(mtd, oob, chip->ecc.prepad);
2023 oob += chip->ecc.prepad;
2024 }
2025
2026 chip->ecc.calculate(mtd, p, oob);
2027 chip->write_buf(mtd, oob, eccbytes);
2028 oob += eccbytes;
2029
2030 if (chip->ecc.postpad) {
2031 chip->write_buf(mtd, oob, chip->ecc.postpad);
2032 oob += chip->ecc.postpad;
2033 }
2034 }
2035
2036 /* Calculate remaining oob bytes */
2037 i = mtd->oobsize - (oob - chip->oob_poi);
2038 if (i)
2039 chip->write_buf(mtd, oob, i);
2040 }
2041
2042 /**
2043 * nand_write_page - [REPLACEABLE] write one page
2044 * @mtd: MTD device structure
2045 * @chip: NAND chip descriptor
2046 * @buf: the data to write
2047 * @page: page number to write
2048 * @cached: cached programming
2049 * @raw: use _raw version of write_page
2050 */
2051 static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2052 const uint8_t *buf, int page, int cached, int raw)
2053 {
2054 int status;
2055
2056 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2057
2058 if (unlikely(raw))
2059 chip->ecc.write_page_raw(mtd, chip, buf);
2060 else
2061 chip->ecc.write_page(mtd, chip, buf);
2062
2063 /*
2064 * Cached progamming disabled for now, Not sure if its worth the
2065 * trouble. The speed gain is not very impressive. (2.3->2.6Mib/s)
2066 */
2067 cached = 0;
2068
2069 if (!cached || !(chip->options & NAND_CACHEPRG)) {
2070
2071 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2072 status = chip->waitfunc(mtd, chip);
2073 /*
2074 * See if operation failed and additional status checks are
2075 * available
2076 */
2077 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2078 status = chip->errstat(mtd, chip, FL_WRITING, status,
2079 page);
2080
2081 if (status & NAND_STATUS_FAIL)
2082 return -EIO;
2083 } else {
2084 chip->cmdfunc(mtd, NAND_CMD_CACHEDPROG, -1, -1);
2085 status = chip->waitfunc(mtd, chip);
2086 }
2087
2088 #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
2089 /* Send command to read back the data */
2090 chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
2091
2092 if (chip->verify_buf(mtd, buf, mtd->writesize))
2093 return -EIO;
2094 #endif
2095 return 0;
2096 }
2097
2098 /**
2099 * nand_fill_oob - [Internal] Transfer client buffer to oob
2100 * @mtd: MTD device structure
2101 * @oob: oob data buffer
2102 * @len: oob data write length
2103 * @ops: oob ops structure
2104 */
2105 static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
2106 struct mtd_oob_ops *ops)
2107 {
2108 struct nand_chip *chip = mtd->priv;
2109
2110 /*
2111 * Initialise to all 0xFF, to avoid the possibility of left over OOB
2112 * data from a previous OOB read.
2113 */
2114 memset(chip->oob_poi, 0xff, mtd->oobsize);
2115
2116 switch (ops->mode) {
2117
2118 case MTD_OOB_PLACE:
2119 case MTD_OOB_RAW:
2120 memcpy(chip->oob_poi + ops->ooboffs, oob, len);
2121 return oob + len;
2122
2123 case MTD_OOB_AUTO: {
2124 struct nand_oobfree *free = chip->ecc.layout->oobfree;
2125 uint32_t boffs = 0, woffs = ops->ooboffs;
2126 size_t bytes = 0;
2127
2128 for (; free->length && len; free++, len -= bytes) {
2129 /* Write request not from offset 0 ? */
2130 if (unlikely(woffs)) {
2131 if (woffs >= free->length) {
2132 woffs -= free->length;
2133 continue;
2134 }
2135 boffs = free->offset + woffs;
2136 bytes = min_t(size_t, len,
2137 (free->length - woffs));
2138 woffs = 0;
2139 } else {
2140 bytes = min_t(size_t, len, free->length);
2141 boffs = free->offset;
2142 }
2143 memcpy(chip->oob_poi + boffs, oob, bytes);
2144 oob += bytes;
2145 }
2146 return oob;
2147 }
2148 default:
2149 BUG();
2150 }
2151 return NULL;
2152 }
2153
2154 #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
2155
2156 /**
2157 * nand_do_write_ops - [Internal] NAND write with ECC
2158 * @mtd: MTD device structure
2159 * @to: offset to write to
2160 * @ops: oob operations description structure
2161 *
2162 * NAND write with ECC
2163 */
2164 static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
2165 struct mtd_oob_ops *ops)
2166 {
2167 int chipnr, realpage, page, blockmask, column;
2168 struct nand_chip *chip = mtd->priv;
2169 uint32_t writelen = ops->len;
2170
2171 uint32_t oobwritelen = ops->ooblen;
2172 uint32_t oobmaxlen = ops->mode == MTD_OOB_AUTO ?
2173 mtd->oobavail : mtd->oobsize;
2174
2175 uint8_t *oob = ops->oobbuf;
2176 uint8_t *buf = ops->datbuf;
2177 int ret, subpage;
2178
2179 ops->retlen = 0;
2180 if (!writelen)
2181 return 0;
2182
2183 /* reject writes, which are not page aligned */
2184 if (NOTALIGNED(to) || NOTALIGNED(ops->len)) {
2185 printk(KERN_NOTICE "%s: Attempt to write not "
2186 "page aligned data\n", __func__);
2187 return -EINVAL;
2188 }
2189
2190 column = to & (mtd->writesize - 1);
2191 subpage = column || (writelen & (mtd->writesize - 1));
2192
2193 if (subpage && oob)
2194 return -EINVAL;
2195
2196 chipnr = (int)(to >> chip->chip_shift);
2197 chip->select_chip(mtd, chipnr);
2198
2199 /* Check, if it is write protected */
2200 if (nand_check_wp(mtd))
2201 return -EIO;
2202
2203 realpage = (int)(to >> chip->page_shift);
2204 page = realpage & chip->pagemask;
2205 blockmask = (1 << (chip->phys_erase_shift - chip->page_shift)) - 1;
2206
2207 /* Invalidate the page cache, when we write to the cached page */
2208 if (to <= (chip->pagebuf << chip->page_shift) &&
2209 (chip->pagebuf << chip->page_shift) < (to + ops->len))
2210 chip->pagebuf = -1;
2211
2212 /* Don't allow multipage oob writes with offset */
2213 if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen))
2214 return -EINVAL;
2215
2216 while (1) {
2217 int bytes = mtd->writesize;
2218 int cached = writelen > bytes && page != blockmask;
2219 uint8_t *wbuf = buf;
2220
2221 /* Partial page write ? */
2222 if (unlikely(column || writelen < (mtd->writesize - 1))) {
2223 cached = 0;
2224 bytes = min_t(int, bytes - column, (int) writelen);
2225 chip->pagebuf = -1;
2226 memset(chip->buffers->databuf, 0xff, mtd->writesize);
2227 memcpy(&chip->buffers->databuf[column], buf, bytes);
2228 wbuf = chip->buffers->databuf;
2229 }
2230
2231 if (unlikely(oob)) {
2232 size_t len = min(oobwritelen, oobmaxlen);
2233 oob = nand_fill_oob(mtd, oob, len, ops);
2234 oobwritelen -= len;
2235 } else {
2236 /* We still need to erase leftover OOB data */
2237 memset(chip->oob_poi, 0xff, mtd->oobsize);
2238 }
2239
2240 ret = chip->write_page(mtd, chip, wbuf, page, cached,
2241 (ops->mode == MTD_OOB_RAW));
2242 if (ret)
2243 break;
2244
2245 writelen -= bytes;
2246 if (!writelen)
2247 break;
2248
2249 column = 0;
2250 buf += bytes;
2251 realpage++;
2252
2253 page = realpage & chip->pagemask;
2254 /* Check, if we cross a chip boundary */
2255 if (!page) {
2256 chipnr++;
2257 chip->select_chip(mtd, -1);
2258 chip->select_chip(mtd, chipnr);
2259 }
2260 }
2261
2262 ops->retlen = ops->len - writelen;
2263 if (unlikely(oob))
2264 ops->oobretlen = ops->ooblen;
2265 return ret;
2266 }
2267
2268 /**
2269 * panic_nand_write - [MTD Interface] NAND write with ECC
2270 * @mtd: MTD device structure
2271 * @to: offset to write to
2272 * @len: number of bytes to write
2273 * @retlen: pointer to variable to store the number of written bytes
2274 * @buf: the data to write
2275 *
2276 * NAND write with ECC. Used when performing writes in interrupt context, this
2277 * may for example be called by mtdoops when writing an oops while in panic.
2278 */
2279 static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2280 size_t *retlen, const uint8_t *buf)
2281 {
2282 struct nand_chip *chip = mtd->priv;
2283 int ret;
2284
2285 /* Do not allow reads past end of device */
2286 if ((to + len) > mtd->size)
2287 return -EINVAL;
2288 if (!len)
2289 return 0;
2290
2291 /* Wait for the device to get ready. */
2292 panic_nand_wait(mtd, chip, 400);
2293
2294 /* Grab the device. */
2295 panic_nand_get_device(chip, mtd, FL_WRITING);
2296
2297 chip->ops.len = len;
2298 chip->ops.datbuf = (uint8_t *)buf;
2299 chip->ops.oobbuf = NULL;
2300
2301 ret = nand_do_write_ops(mtd, to, &chip->ops);
2302
2303 *retlen = chip->ops.retlen;
2304 return ret;
2305 }
2306
2307 /**
2308 * nand_write - [MTD Interface] NAND write with ECC
2309 * @mtd: MTD device structure
2310 * @to: offset to write to
2311 * @len: number of bytes to write
2312 * @retlen: pointer to variable to store the number of written bytes
2313 * @buf: the data to write
2314 *
2315 * NAND write with ECC
2316 */
2317 static int nand_write(struct mtd_info *mtd, loff_t to, size_t len,
2318 size_t *retlen, const uint8_t *buf)
2319 {
2320 struct nand_chip *chip = mtd->priv;
2321 int ret;
2322
2323 /* Do not allow reads past end of device */
2324 if ((to + len) > mtd->size)
2325 return -EINVAL;
2326 if (!len)
2327 return 0;
2328
2329 nand_get_device(chip, mtd, FL_WRITING);
2330
2331 chip->ops.len = len;
2332 chip->ops.datbuf = (uint8_t *)buf;
2333 chip->ops.oobbuf = NULL;
2334
2335 ret = nand_do_write_ops(mtd, to, &chip->ops);
2336
2337 *retlen = chip->ops.retlen;
2338
2339 nand_release_device(mtd);
2340
2341 return ret;
2342 }
2343
2344 /**
2345 * nand_do_write_oob - [MTD Interface] NAND write out-of-band
2346 * @mtd: MTD device structure
2347 * @to: offset to write to
2348 * @ops: oob operation description structure
2349 *
2350 * NAND write out-of-band
2351 */
2352 static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
2353 struct mtd_oob_ops *ops)
2354 {
2355 int chipnr, page, status, len;
2356 struct nand_chip *chip = mtd->priv;
2357
2358 DEBUG(MTD_DEBUG_LEVEL3, "%s: to = 0x%08x, len = %i\n",
2359 __func__, (unsigned int)to, (int)ops->ooblen);
2360
2361 if (ops->mode == MTD_OOB_AUTO)
2362 len = chip->ecc.layout->oobavail;
2363 else
2364 len = mtd->oobsize;
2365
2366 /* Do not allow write past end of page */
2367 if ((ops->ooboffs + ops->ooblen) > len) {
2368 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to write "
2369 "past end of page\n", __func__);
2370 return -EINVAL;
2371 }
2372
2373 if (unlikely(ops->ooboffs >= len)) {
2374 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt to start "
2375 "write outside oob\n", __func__);
2376 return -EINVAL;
2377 }
2378
2379 /* Do not allow write past end of device */
2380 if (unlikely(to >= mtd->size ||
2381 ops->ooboffs + ops->ooblen >
2382 ((mtd->size >> chip->page_shift) -
2383 (to >> chip->page_shift)) * len)) {
2384 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2385 "end of device\n", __func__);
2386 return -EINVAL;
2387 }
2388
2389 chipnr = (int)(to >> chip->chip_shift);
2390 chip->select_chip(mtd, chipnr);
2391
2392 /* Shift to get page */
2393 page = (int)(to >> chip->page_shift);
2394
2395 /*
2396 * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
2397 * of my DiskOnChip 2000 test units) will clear the whole data page too
2398 * if we don't do this. I have no clue why, but I seem to have 'fixed'
2399 * it in the doc2000 driver in August 1999. dwmw2.
2400 */
2401 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2402
2403 /* Check, if it is write protected */
2404 if (nand_check_wp(mtd))
2405 return -EROFS;
2406
2407 /* Invalidate the page cache, if we write to the cached page */
2408 if (page == chip->pagebuf)
2409 chip->pagebuf = -1;
2410
2411 nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
2412 status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
2413
2414 if (status)
2415 return status;
2416
2417 ops->oobretlen = ops->ooblen;
2418
2419 return 0;
2420 }
2421
2422 /**
2423 * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
2424 * @mtd: MTD device structure
2425 * @to: offset to write to
2426 * @ops: oob operation description structure
2427 */
2428 static int nand_write_oob(struct mtd_info *mtd, loff_t to,
2429 struct mtd_oob_ops *ops)
2430 {
2431 struct nand_chip *chip = mtd->priv;
2432 int ret = -ENOTSUPP;
2433
2434 ops->retlen = 0;
2435
2436 /* Do not allow writes past end of device */
2437 if (ops->datbuf && (to + ops->len) > mtd->size) {
2438 DEBUG(MTD_DEBUG_LEVEL0, "%s: Attempt write beyond "
2439 "end of device\n", __func__);
2440 return -EINVAL;
2441 }
2442
2443 nand_get_device(chip, mtd, FL_WRITING);
2444
2445 switch (ops->mode) {
2446 case MTD_OOB_PLACE:
2447 case MTD_OOB_AUTO:
2448 case MTD_OOB_RAW:
2449 break;
2450
2451 default:
2452 goto out;
2453 }
2454
2455 if (!ops->datbuf)
2456 ret = nand_do_write_oob(mtd, to, ops);
2457 else
2458 ret = nand_do_write_ops(mtd, to, ops);
2459
2460 out:
2461 nand_release_device(mtd);
2462 return ret;
2463 }
2464
2465 /**
2466 * single_erease_cmd - [GENERIC] NAND standard block erase command function
2467 * @mtd: MTD device structure
2468 * @page: the page address of the block which will be erased
2469 *
2470 * Standard erase command for NAND chips
2471 */
2472 static void single_erase_cmd(struct mtd_info *mtd, int page)
2473 {
2474 struct nand_chip *chip = mtd->priv;
2475 /* Send commands to erase a block */
2476 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2477 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2478 }
2479
2480 /**
2481 * multi_erease_cmd - [GENERIC] AND specific block erase command function
2482 * @mtd: MTD device structure
2483 * @page: the page address of the block which will be erased
2484 *
2485 * AND multi block erase command function
2486 * Erase 4 consecutive blocks
2487 */
2488 static void multi_erase_cmd(struct mtd_info *mtd, int page)
2489 {
2490 struct nand_chip *chip = mtd->priv;
2491 /* Send commands to erase a block */
2492 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2493 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2494 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page++);
2495 chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
2496 chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
2497 }
2498
2499 /**
2500 * nand_erase - [MTD Interface] erase block(s)
2501 * @mtd: MTD device structure
2502 * @instr: erase instruction
2503 *
2504 * Erase one ore more blocks
2505 */
2506 static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
2507 {
2508 return nand_erase_nand(mtd, instr, 0);
2509 }
2510
2511 #define BBT_PAGE_MASK 0xffffff3f
2512 /**
2513 * nand_erase_nand - [Internal] erase block(s)
2514 * @mtd: MTD device structure
2515 * @instr: erase instruction
2516 * @allowbbt: allow erasing the bbt area
2517 *
2518 * Erase one ore more blocks
2519 */
2520 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
2521 int allowbbt)
2522 {
2523 int page, status, pages_per_block, ret, chipnr;
2524 struct nand_chip *chip = mtd->priv;
2525 loff_t rewrite_bbt[NAND_MAX_CHIPS] = {0};
2526 unsigned int bbt_masked_page = 0xffffffff;
2527 loff_t len;
2528
2529 DEBUG(MTD_DEBUG_LEVEL3, "%s: start = 0x%012llx, len = %llu\n",
2530 __func__, (unsigned long long)instr->addr,
2531 (unsigned long long)instr->len);
2532
2533 if (check_offs_len(mtd, instr->addr, instr->len))
2534 return -EINVAL;
2535
2536 instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
2537
2538 /* Grab the lock and see if the device is available */
2539 nand_get_device(chip, mtd, FL_ERASING);
2540
2541 /* Shift to get first page */
2542 page = (int)(instr->addr >> chip->page_shift);
2543 chipnr = (int)(instr->addr >> chip->chip_shift);
2544
2545 /* Calculate pages in each block */
2546 pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2547
2548 /* Select the NAND device */
2549 chip->select_chip(mtd, chipnr);
2550
2551 /* Check, if it is write protected */
2552 if (nand_check_wp(mtd)) {
2553 DEBUG(MTD_DEBUG_LEVEL0, "%s: Device is write protected!!!\n",
2554 __func__);
2555 instr->state = MTD_ERASE_FAILED;
2556 goto erase_exit;
2557 }
2558
2559 /*
2560 * If BBT requires refresh, set the BBT page mask to see if the BBT
2561 * should be rewritten. Otherwise the mask is set to 0xffffffff which
2562 * can not be matched. This is also done when the bbt is actually
2563 * erased to avoid recusrsive updates
2564 */
2565 if (chip->options & BBT_AUTO_REFRESH && !allowbbt)
2566 bbt_masked_page = chip->bbt_td->pages[chipnr] & BBT_PAGE_MASK;
2567
2568 /* Loop through the pages */
2569 len = instr->len;
2570
2571 instr->state = MTD_ERASING;
2572
2573 while (len) {
2574 /*
2575 * heck if we have a bad block, we do not erase bad blocks !
2576 */
2577 if (nand_block_checkbad(mtd, ((loff_t) page) <<
2578 chip->page_shift, 0, allowbbt)) {
2579 printk(KERN_WARNING "%s: attempt to erase a bad block "
2580 "at page 0x%08x\n", __func__, page);
2581 instr->state = MTD_ERASE_FAILED;
2582 goto erase_exit;
2583 }
2584
2585 /*
2586 * Invalidate the page cache, if we erase the block which
2587 * contains the current cached page
2588 */
2589 if (page <= chip->pagebuf && chip->pagebuf <
2590 (page + pages_per_block))
2591 chip->pagebuf = -1;
2592
2593 chip->erase_cmd(mtd, page & chip->pagemask);
2594
2595 status = chip->waitfunc(mtd, chip);
2596
2597 /*
2598 * See if operation failed and additional status checks are
2599 * available
2600 */
2601 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2602 status = chip->errstat(mtd, chip, FL_ERASING,
2603 status, page);
2604
2605 /* See if block erase succeeded */
2606 if (status & NAND_STATUS_FAIL) {
2607 DEBUG(MTD_DEBUG_LEVEL0, "%s: Failed erase, "
2608 "page 0x%08x\n", __func__, page);
2609 instr->state = MTD_ERASE_FAILED;
2610 instr->fail_addr =
2611 ((loff_t)page << chip->page_shift);
2612 goto erase_exit;
2613 }
2614
2615 /*
2616 * If BBT requires refresh, set the BBT rewrite flag to the
2617 * page being erased
2618 */
2619 if (bbt_masked_page != 0xffffffff &&
2620 (page & BBT_PAGE_MASK) == bbt_masked_page)
2621 rewrite_bbt[chipnr] =
2622 ((loff_t)page << chip->page_shift);
2623
2624 /* Increment page address and decrement length */
2625 len -= (1 << chip->phys_erase_shift);
2626 page += pages_per_block;
2627
2628 /* Check, if we cross a chip boundary */
2629 if (len && !(page & chip->pagemask)) {
2630 chipnr++;
2631 chip->select_chip(mtd, -1);
2632 chip->select_chip(mtd, chipnr);
2633
2634 /*
2635 * If BBT requires refresh and BBT-PERCHIP, set the BBT
2636 * page mask to see if this BBT should be rewritten
2637 */
2638 if (bbt_masked_page != 0xffffffff &&
2639 (chip->bbt_td->options & NAND_BBT_PERCHIP))
2640 bbt_masked_page = chip->bbt_td->pages[chipnr] &
2641 BBT_PAGE_MASK;
2642 }
2643 }
2644 instr->state = MTD_ERASE_DONE;
2645
2646 erase_exit:
2647
2648 ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
2649
2650 /* Deselect and wake up anyone waiting on the device */
2651 nand_release_device(mtd);
2652
2653 /* Do call back function */
2654 if (!ret)
2655 mtd_erase_callback(instr);
2656
2657 /*
2658 * If BBT requires refresh and erase was successful, rewrite any
2659 * selected bad block tables
2660 */
2661 if (bbt_masked_page == 0xffffffff || ret)
2662 return ret;
2663
2664 for (chipnr = 0; chipnr < chip->numchips; chipnr++) {
2665 if (!rewrite_bbt[chipnr])
2666 continue;
2667 /* update the BBT for chip */
2668 DEBUG(MTD_DEBUG_LEVEL0, "%s: nand_update_bbt "
2669 "(%d:0x%0llx 0x%0x)\n", __func__, chipnr,
2670 rewrite_bbt[chipnr], chip->bbt_td->pages[chipnr]);
2671 nand_update_bbt(mtd, rewrite_bbt[chipnr]);
2672 }
2673
2674 /* Return more or less happy */
2675 return ret;
2676 }
2677
2678 /**
2679 * nand_sync - [MTD Interface] sync
2680 * @mtd: MTD device structure
2681 *
2682 * Sync is actually a wait for chip ready function
2683 */
2684 static void nand_sync(struct mtd_info *mtd)
2685 {
2686 struct nand_chip *chip = mtd->priv;
2687
2688 DEBUG(MTD_DEBUG_LEVEL3, "%s: called\n", __func__);
2689
2690 /* Grab the lock and see if the device is available */
2691 nand_get_device(chip, mtd, FL_SYNCING);
2692 /* Release it and go back */
2693 nand_release_device(mtd);
2694 }
2695
2696 /**
2697 * nand_block_isbad - [MTD Interface] Check if block at offset is bad
2698 * @mtd: MTD device structure
2699 * @offs: offset relative to mtd start
2700 */
2701 static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
2702 {
2703 /* Check for invalid offset */
2704 if (offs > mtd->size)
2705 return -EINVAL;
2706
2707 return nand_block_checkbad(mtd, offs, 1, 0);
2708 }
2709
2710 /**
2711 * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
2712 * @mtd: MTD device structure
2713 * @ofs: offset relative to mtd start
2714 */
2715 static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
2716 {
2717 struct nand_chip *chip = mtd->priv;
2718 int ret;
2719
2720 ret = nand_block_isbad(mtd, ofs);
2721 if (ret) {
2722 /* If it was bad already, return success and do nothing. */
2723 if (ret > 0)
2724 return 0;
2725 return ret;
2726 }
2727
2728 return chip->block_markbad(mtd, ofs);
2729 }
2730
2731 /**
2732 * nand_suspend - [MTD Interface] Suspend the NAND flash
2733 * @mtd: MTD device structure
2734 */
2735 static int nand_suspend(struct mtd_info *mtd)
2736 {
2737 struct nand_chip *chip = mtd->priv;
2738
2739 return nand_get_device(chip, mtd, FL_PM_SUSPENDED);
2740 }
2741
2742 /**
2743 * nand_resume - [MTD Interface] Resume the NAND flash
2744 * @mtd: MTD device structure
2745 */
2746 static void nand_resume(struct mtd_info *mtd)
2747 {
2748 struct nand_chip *chip = mtd->priv;
2749
2750 if (chip->state == FL_PM_SUSPENDED)
2751 nand_release_device(mtd);
2752 else
2753 printk(KERN_ERR "%s called for a chip which is not "
2754 "in suspended state\n", __func__);
2755 }
2756
2757 /*
2758 * Set default functions
2759 */
2760 static void nand_set_defaults(struct nand_chip *chip, int busw)
2761 {
2762 /* check for proper chip_delay setup, set 20us if not */
2763 if (!chip->chip_delay)
2764 chip->chip_delay = 20;
2765
2766 /* check, if a user supplied command function given */
2767 if (chip->cmdfunc == NULL)
2768 chip->cmdfunc = nand_command;
2769
2770 /* check, if a user supplied wait function given */
2771 if (chip->waitfunc == NULL)
2772 chip->waitfunc = nand_wait;
2773
2774 if (!chip->select_chip)
2775 chip->select_chip = nand_select_chip;
2776 if (!chip->read_byte)
2777 chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
2778 if (!chip->read_word)
2779 chip->read_word = nand_read_word;
2780 if (!chip->block_bad)
2781 chip->block_bad = nand_block_bad;
2782 if (!chip->block_markbad)
2783 chip->block_markbad = nand_default_block_markbad;
2784 if (!chip->write_buf)
2785 chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
2786 if (!chip->read_buf)
2787 chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
2788 if (!chip->verify_buf)
2789 chip->verify_buf = busw ? nand_verify_buf16 : nand_verify_buf;
2790 if (!chip->scan_bbt)
2791 chip->scan_bbt = nand_default_bbt;
2792
2793 if (!chip->controller) {
2794 chip->controller = &chip->hwcontrol;
2795 spin_lock_init(&chip->controller->lock);
2796 init_waitqueue_head(&chip->controller->wq);
2797 }
2798
2799 }
2800
2801 /*
2802 * sanitize ONFI strings so we can safely print them
2803 */
2804 static void sanitize_string(uint8_t *s, size_t len)
2805 {
2806 ssize_t i;
2807
2808 /* null terminate */
2809 s[len - 1] = 0;
2810
2811 /* remove non printable chars */
2812 for (i = 0; i < len - 1; i++) {
2813 if (s[i] < ' ' || s[i] > 127)
2814 s[i] = '?';
2815 }
2816
2817 /* remove trailing spaces */
2818 strim(s);
2819 }
2820
2821 static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
2822 {
2823 int i;
2824 while (len--) {
2825 crc ^= *p++ << 8;
2826 for (i = 0; i < 8; i++)
2827 crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
2828 }
2829
2830 return crc;
2831 }
2832
2833 /*
2834 * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise
2835 */
2836 static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
2837 int busw)
2838 {
2839 struct nand_onfi_params *p = &chip->onfi_params;
2840 int i;
2841 int val;
2842
2843 /* try ONFI for unknow chip or LP */
2844 chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
2845 if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
2846 chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
2847 return 0;
2848
2849 printk(KERN_INFO "ONFI flash detected\n");
2850 chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
2851 for (i = 0; i < 3; i++) {
2852 chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
2853 if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
2854 le16_to_cpu(p->crc)) {
2855 printk(KERN_INFO "ONFI param page %d valid\n", i);
2856 break;
2857 }
2858 }
2859
2860 if (i == 3)
2861 return 0;
2862
2863 /* check version */
2864 val = le16_to_cpu(p->revision);
2865 if (val & (1 << 5))
2866 chip->onfi_version = 23;
2867 else if (val & (1 << 4))
2868 chip->onfi_version = 22;
2869 else if (val & (1 << 3))
2870 chip->onfi_version = 21;
2871 else if (val & (1 << 2))
2872 chip->onfi_version = 20;
2873 else if (val & (1 << 1))
2874 chip->onfi_version = 10;
2875 else
2876 chip->onfi_version = 0;
2877
2878 if (!chip->onfi_version) {
2879 printk(KERN_INFO "%s: unsupported ONFI version: %d\n",
2880 __func__, val);
2881 return 0;
2882 }
2883
2884 sanitize_string(p->manufacturer, sizeof(p->manufacturer));
2885 sanitize_string(p->model, sizeof(p->model));
2886 if (!mtd->name)
2887 mtd->name = p->model;
2888 mtd->writesize = le32_to_cpu(p->byte_per_page);
2889 mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
2890 mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
2891 chip->chipsize = (uint64_t)le32_to_cpu(p->blocks_per_lun) * mtd->erasesize;
2892 busw = 0;
2893 if (le16_to_cpu(p->features) & 1)
2894 busw = NAND_BUSWIDTH_16;
2895
2896 chip->options &= ~NAND_CHIPOPTIONS_MSK;
2897 chip->options |= (NAND_NO_READRDY |
2898 NAND_NO_AUTOINCR) & NAND_CHIPOPTIONS_MSK;
2899
2900 return 1;
2901 }
2902
2903 /*
2904 * Get the flash and manufacturer id and lookup if the type is supported
2905 */
2906 static struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
2907 struct nand_chip *chip,
2908 int busw,
2909 int *maf_id, int *dev_id,
2910 struct nand_flash_dev *type)
2911 {
2912 int i, maf_idx;
2913 u8 id_data[8];
2914 int ret;
2915
2916 /* Select the device */
2917 chip->select_chip(mtd, 0);
2918
2919 /*
2920 * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
2921 * after power-up
2922 */
2923 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2924
2925 /* Send the command for reading device ID */
2926 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2927
2928 /* Read manufacturer and device IDs */
2929 *maf_id = chip->read_byte(mtd);
2930 *dev_id = chip->read_byte(mtd);
2931
2932 /* Try again to make sure, as some systems the bus-hold or other
2933 * interface concerns can cause random data which looks like a
2934 * possibly credible NAND flash to appear. If the two results do
2935 * not match, ignore the device completely.
2936 */
2937
2938 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2939
2940 for (i = 0; i < 2; i++)
2941 id_data[i] = chip->read_byte(mtd);
2942
2943 if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
2944 printk(KERN_INFO "%s: second ID read did not match "
2945 "%02x,%02x against %02x,%02x\n", __func__,
2946 *maf_id, *dev_id, id_data[0], id_data[1]);
2947 return ERR_PTR(-ENODEV);
2948 }
2949
2950 if (!type)
2951 type = nand_flash_ids;
2952
2953 for (; type->name != NULL; type++)
2954 if (*dev_id == type->id)
2955 break;
2956
2957 chip->onfi_version = 0;
2958 if (!type->name || !type->pagesize) {
2959 /* Check is chip is ONFI compliant */
2960 ret = nand_flash_detect_onfi(mtd, chip, busw);
2961 if (ret)
2962 goto ident_done;
2963 }
2964
2965 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
2966
2967 /* Read entire ID string */
2968
2969 for (i = 0; i < 8; i++)
2970 id_data[i] = chip->read_byte(mtd);
2971
2972 if (!type->name)
2973 return ERR_PTR(-ENODEV);
2974
2975 if (!mtd->name)
2976 mtd->name = type->name;
2977
2978 chip->chipsize = (uint64_t)type->chipsize << 20;
2979
2980 if (!type->pagesize && chip->init_size) {
2981 /* set the pagesize, oobsize, erasesize by the driver*/
2982 busw = chip->init_size(mtd, chip, id_data);
2983 } else if (!type->pagesize) {
2984 int extid;
2985 /* The 3rd id byte holds MLC / multichip data */
2986 chip->cellinfo = id_data[2];
2987 /* The 4th id byte is the important one */
2988 extid = id_data[3];
2989
2990 /*
2991 * Field definitions are in the following datasheets:
2992 * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
2993 * New style (6 byte ID): Samsung K9GBG08U0M (p.40)
2994 *
2995 * Check for wraparound + Samsung ID + nonzero 6th byte
2996 * to decide what to do.
2997 */
2998 if (id_data[0] == id_data[6] && id_data[1] == id_data[7] &&
2999 id_data[0] == NAND_MFR_SAMSUNG &&
3000 (chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3001 id_data[5] != 0x00) {
3002 /* Calc pagesize */
3003 mtd->writesize = 2048 << (extid & 0x03);
3004 extid >>= 2;
3005 /* Calc oobsize */
3006 switch (extid & 0x03) {
3007 case 1:
3008 mtd->oobsize = 128;
3009 break;
3010 case 2:
3011 mtd->oobsize = 218;
3012 break;
3013 case 3:
3014 mtd->oobsize = 400;
3015 break;
3016 default:
3017 mtd->oobsize = 436;
3018 break;
3019 }
3020 extid >>= 2;
3021 /* Calc blocksize */
3022 mtd->erasesize = (128 * 1024) <<
3023 (((extid >> 1) & 0x04) | (extid & 0x03));
3024 busw = 0;
3025 } else {
3026 /* Calc pagesize */
3027 mtd->writesize = 1024 << (extid & 0x03);
3028 extid >>= 2;
3029 /* Calc oobsize */
3030 mtd->oobsize = (8 << (extid & 0x01)) *
3031 (mtd->writesize >> 9);
3032 extid >>= 2;
3033 /* Calc blocksize. Blocksize is multiples of 64KiB */
3034 mtd->erasesize = (64 * 1024) << (extid & 0x03);
3035 extid >>= 2;
3036 /* Get buswidth information */
3037 busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
3038 }
3039 } else {
3040 /*
3041 * Old devices have chip data hardcoded in the device id table
3042 */
3043 mtd->erasesize = type->erasesize;
3044 mtd->writesize = type->pagesize;
3045 mtd->oobsize = mtd->writesize / 32;
3046 busw = type->options & NAND_BUSWIDTH_16;
3047
3048 /*
3049 * Check for Spansion/AMD ID + repeating 5th, 6th byte since
3050 * some Spansion chips have erasesize that conflicts with size
3051 * listed in nand_ids table
3052 * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
3053 */
3054 if (*maf_id == NAND_MFR_AMD && id_data[4] != 0x00 &&
3055 id_data[5] == 0x00 && id_data[6] == 0x00 &&
3056 id_data[7] == 0x00 && mtd->writesize == 512) {
3057 mtd->erasesize = 128 * 1024;
3058 mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
3059 }
3060 }
3061 /* Get chip options, preserve non chip based options */
3062 chip->options &= ~NAND_CHIPOPTIONS_MSK;
3063 chip->options |= type->options & NAND_CHIPOPTIONS_MSK;
3064
3065 /* Check if chip is a not a samsung device. Do not clear the
3066 * options for chips which are not having an extended id.
3067 */
3068 if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
3069 chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
3070 ident_done:
3071
3072 /*
3073 * Set chip as a default. Board drivers can override it, if necessary
3074 */
3075 chip->options |= NAND_NO_AUTOINCR;
3076
3077 /* Try to identify manufacturer */
3078 for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
3079 if (nand_manuf_ids[maf_idx].id == *maf_id)
3080 break;
3081 }
3082
3083 /*
3084 * Check, if buswidth is correct. Hardware drivers should set
3085 * chip correct !
3086 */
3087 if (busw != (chip->options & NAND_BUSWIDTH_16)) {
3088 printk(KERN_INFO "NAND device: Manufacturer ID:"
3089 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
3090 *dev_id, nand_manuf_ids[maf_idx].name, mtd->name);
3091 printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
3092 (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
3093 busw ? 16 : 8);
3094 return ERR_PTR(-EINVAL);
3095 }
3096
3097 /* Calculate the address shift from the page size */
3098 chip->page_shift = ffs(mtd->writesize) - 1;
3099 /* Convert chipsize to number of pages per chip -1. */
3100 chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
3101
3102 chip->bbt_erase_shift = chip->phys_erase_shift =
3103 ffs(mtd->erasesize) - 1;
3104 if (chip->chipsize & 0xffffffff)
3105 chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
3106 else {
3107 chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
3108 chip->chip_shift += 32 - 1;
3109 }
3110
3111 chip->badblockbits = 8;
3112
3113 /* Set the bad block position */
3114 if (mtd->writesize > 512 || (busw & NAND_BUSWIDTH_16))
3115 chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
3116 else
3117 chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
3118
3119 /*
3120 * Bad block marker is stored in the last page of each block
3121 * on Samsung and Hynix MLC devices; stored in first two pages
3122 * of each block on Micron devices with 2KiB pages and on
3123 * SLC Samsung, Hynix, Toshiba and AMD/Spansion. All others scan
3124 * only the first page.
3125 */
3126 if ((chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3127 (*maf_id == NAND_MFR_SAMSUNG ||
3128 *maf_id == NAND_MFR_HYNIX))
3129 chip->options |= NAND_BBT_SCANLASTPAGE;
3130 else if ((!(chip->cellinfo & NAND_CI_CELLTYPE_MSK) &&
3131 (*maf_id == NAND_MFR_SAMSUNG ||
3132 *maf_id == NAND_MFR_HYNIX ||
3133 *maf_id == NAND_MFR_TOSHIBA ||
3134 *maf_id == NAND_MFR_AMD)) ||
3135 (mtd->writesize == 2048 &&
3136 *maf_id == NAND_MFR_MICRON))
3137 chip->options |= NAND_BBT_SCAN2NDPAGE;
3138
3139 /*
3140 * Numonyx/ST 2K pages, x8 bus use BOTH byte 1 and 6
3141 */
3142 if (!(busw & NAND_BUSWIDTH_16) &&
3143 *maf_id == NAND_MFR_STMICRO &&
3144 mtd->writesize == 2048) {
3145 chip->options |= NAND_BBT_SCANBYTE1AND6;
3146 chip->badblockpos = 0;
3147 }
3148
3149 /* Check for AND chips with 4 page planes */
3150 if (chip->options & NAND_4PAGE_ARRAY)
3151 chip->erase_cmd = multi_erase_cmd;
3152 else
3153 chip->erase_cmd = single_erase_cmd;
3154
3155 /* Do not replace user supplied command function ! */
3156 if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
3157 chip->cmdfunc = nand_command_lp;
3158
3159 /* TODO onfi flash name */
3160 printk(KERN_INFO "NAND device: Manufacturer ID:"
3161 " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, *dev_id,
3162 nand_manuf_ids[maf_idx].name,
3163 chip->onfi_version ? chip->onfi_params.model : type->name);
3164
3165 return type;
3166 }
3167
3168 /**
3169 * nand_scan_ident - [NAND Interface] Scan for the NAND device
3170 * @mtd: MTD device structure
3171 * @maxchips: Number of chips to scan for
3172 * @table: Alternative NAND ID table
3173 *
3174 * This is the first phase of the normal nand_scan() function. It
3175 * reads the flash ID and sets up MTD fields accordingly.
3176 *
3177 * The mtd->owner field must be set to the module of the caller.
3178 */
3179 int nand_scan_ident(struct mtd_info *mtd, int maxchips,
3180 struct nand_flash_dev *table)
3181 {
3182 int i, busw, nand_maf_id, nand_dev_id;
3183 struct nand_chip *chip = mtd->priv;
3184 struct nand_flash_dev *type;
3185
3186 /* Get buswidth to select the correct functions */
3187 busw = chip->options & NAND_BUSWIDTH_16;
3188 /* Set the default functions */
3189 nand_set_defaults(chip, busw);
3190
3191 /* Read the flash type */
3192 type = nand_get_flash_type(mtd, chip, busw,
3193 &nand_maf_id, &nand_dev_id, table);
3194
3195 if (IS_ERR(type)) {
3196 if (!(chip->options & NAND_SCAN_SILENT_NODEV))
3197 printk(KERN_WARNING "No NAND device found.\n");
3198 chip->select_chip(mtd, -1);
3199 return PTR_ERR(type);
3200 }
3201
3202 /* Check for a chip array */
3203 for (i = 1; i < maxchips; i++) {
3204 chip->select_chip(mtd, i);
3205 /* See comment in nand_get_flash_type for reset */
3206 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3207 /* Send the command for reading device ID */
3208 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3209 /* Read manufacturer and device IDs */
3210 if (nand_maf_id != chip->read_byte(mtd) ||
3211 nand_dev_id != chip->read_byte(mtd))
3212 break;
3213 }
3214 if (i > 1)
3215 printk(KERN_INFO "%d NAND chips detected\n", i);
3216
3217 /* Store the number of chips and calc total size for mtd */
3218 chip->numchips = i;
3219 mtd->size = i * chip->chipsize;
3220
3221 return 0;
3222 }
3223 EXPORT_SYMBOL(nand_scan_ident);
3224
3225
3226 /**
3227 * nand_scan_tail - [NAND Interface] Scan for the NAND device
3228 * @mtd: MTD device structure
3229 *
3230 * This is the second phase of the normal nand_scan() function. It
3231 * fills out all the uninitialized function pointers with the defaults
3232 * and scans for a bad block table if appropriate.
3233 */
3234 int nand_scan_tail(struct mtd_info *mtd)
3235 {
3236 int i;
3237 struct nand_chip *chip = mtd->priv;
3238
3239 if (!(chip->options & NAND_OWN_BUFFERS))
3240 chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL);
3241 if (!chip->buffers)
3242 return -ENOMEM;
3243
3244 /* Set the internal oob buffer location, just after the page data */
3245 chip->oob_poi = chip->buffers->databuf + mtd->writesize;
3246
3247 /*
3248 * If no default placement scheme is given, select an appropriate one
3249 */
3250 if (!chip->ecc.layout && (chip->ecc.mode != NAND_ECC_SOFT_BCH)) {
3251 switch (mtd->oobsize) {
3252 case 8:
3253 chip->ecc.layout = &nand_oob_8;
3254 break;
3255 case 16:
3256 chip->ecc.layout = &nand_oob_16;
3257 break;
3258 case 64:
3259 chip->ecc.layout = &nand_oob_64;
3260 break;
3261 case 128:
3262 chip->ecc.layout = &nand_oob_128;
3263 break;
3264 default:
3265 printk(KERN_WARNING "No oob scheme defined for "
3266 "oobsize %d\n", mtd->oobsize);
3267 BUG();
3268 }
3269 }
3270
3271 if (!chip->write_page)
3272 chip->write_page = nand_write_page;
3273
3274 /*
3275 * check ECC mode, default to software if 3byte/512byte hardware ECC is
3276 * selected and we have 256 byte pagesize fallback to software ECC
3277 */
3278
3279 switch (chip->ecc.mode) {
3280 case NAND_ECC_HW_OOB_FIRST:
3281 /* Similar to NAND_ECC_HW, but a separate read_page handle */
3282 if (!chip->ecc.calculate || !chip->ecc.correct ||
3283 !chip->ecc.hwctl) {
3284 printk(KERN_WARNING "No ECC functions supplied; "
3285 "Hardware ECC not possible\n");
3286 BUG();
3287 }
3288 if (!chip->ecc.read_page)
3289 chip->ecc.read_page = nand_read_page_hwecc_oob_first;
3290
3291 case NAND_ECC_HW:
3292 /* Use standard hwecc read page function ? */
3293 if (!chip->ecc.read_page)
3294 chip->ecc.read_page = nand_read_page_hwecc;
3295 if (!chip->ecc.write_page)
3296 chip->ecc.write_page = nand_write_page_hwecc;
3297 if (!chip->ecc.read_page_raw)
3298 chip->ecc.read_page_raw = nand_read_page_raw;
3299 if (!chip->ecc.write_page_raw)
3300 chip->ecc.write_page_raw = nand_write_page_raw;
3301 if (!chip->ecc.read_oob)
3302 chip->ecc.read_oob = nand_read_oob_std;
3303 if (!chip->ecc.write_oob)
3304 chip->ecc.write_oob = nand_write_oob_std;
3305
3306 case NAND_ECC_HW_SYNDROME:
3307 if ((!chip->ecc.calculate || !chip->ecc.correct ||
3308 !chip->ecc.hwctl) &&
3309 (!chip->ecc.read_page ||
3310 chip->ecc.read_page == nand_read_page_hwecc ||
3311 !chip->ecc.write_page ||
3312 chip->ecc.write_page == nand_write_page_hwecc)) {
3313 printk(KERN_WARNING "No ECC functions supplied; "
3314 "Hardware ECC not possible\n");
3315 BUG();
3316 }
3317 /* Use standard syndrome read/write page function ? */
3318 if (!chip->ecc.read_page)
3319 chip->ecc.read_page = nand_read_page_syndrome;
3320 if (!chip->ecc.write_page)
3321 chip->ecc.write_page = nand_write_page_syndrome;
3322 if (!chip->ecc.read_page_raw)
3323 chip->ecc.read_page_raw = nand_read_page_raw_syndrome;
3324 if (!chip->ecc.write_page_raw)
3325 chip->ecc.write_page_raw = nand_write_page_raw_syndrome;
3326 if (!chip->ecc.read_oob)
3327 chip->ecc.read_oob = nand_read_oob_syndrome;
3328 if (!chip->ecc.write_oob)
3329 chip->ecc.write_oob = nand_write_oob_syndrome;
3330
3331 if (mtd->writesize >= chip->ecc.size)
3332 break;
3333 printk(KERN_WARNING "%d byte HW ECC not possible on "
3334 "%d byte page size, fallback to SW ECC\n",
3335 chip->ecc.size, mtd->writesize);
3336 chip->ecc.mode = NAND_ECC_SOFT;
3337
3338 case NAND_ECC_SOFT:
3339 chip->ecc.calculate = nand_calculate_ecc;
3340 chip->ecc.correct = nand_correct_data;
3341 chip->ecc.read_page = nand_read_page_swecc;
3342 chip->ecc.read_subpage = nand_read_subpage;
3343 chip->ecc.write_page = nand_write_page_swecc;
3344 chip->ecc.read_page_raw = nand_read_page_raw;
3345 chip->ecc.write_page_raw = nand_write_page_raw;
3346 chip->ecc.read_oob = nand_read_oob_std;
3347 chip->ecc.write_oob = nand_write_oob_std;
3348 if (!chip->ecc.size)
3349 chip->ecc.size = 256;
3350 chip->ecc.bytes = 3;
3351 break;
3352
3353 case NAND_ECC_SOFT_BCH:
3354 if (!mtd_nand_has_bch()) {
3355 printk(KERN_WARNING "CONFIG_MTD_ECC_BCH not enabled\n");
3356 BUG();
3357 }
3358 chip->ecc.calculate = nand_bch_calculate_ecc;
3359 chip->ecc.correct = nand_bch_correct_data;
3360 chip->ecc.read_page = nand_read_page_swecc;
3361 chip->ecc.read_subpage = nand_read_subpage;
3362 chip->ecc.write_page = nand_write_page_swecc;
3363 chip->ecc.read_page_raw = nand_read_page_raw;
3364 chip->ecc.write_page_raw = nand_write_page_raw;
3365 chip->ecc.read_oob = nand_read_oob_std;
3366 chip->ecc.write_oob = nand_write_oob_std;
3367 /*
3368 * Board driver should supply ecc.size and ecc.bytes values to
3369 * select how many bits are correctable; see nand_bch_init()
3370 * for details.
3371 * Otherwise, default to 4 bits for large page devices
3372 */
3373 if (!chip->ecc.size && (mtd->oobsize >= 64)) {
3374 chip->ecc.size = 512;
3375 chip->ecc.bytes = 7;
3376 }
3377 chip->ecc.priv = nand_bch_init(mtd,
3378 chip->ecc.size,
3379 chip->ecc.bytes,
3380 &chip->ecc.layout);
3381 if (!chip->ecc.priv) {
3382 printk(KERN_WARNING "BCH ECC initialization failed!\n");
3383 BUG();
3384 }
3385 break;
3386
3387 case NAND_ECC_NONE:
3388 printk(KERN_WARNING "NAND_ECC_NONE selected by board driver. "
3389 "This is not recommended !!\n");
3390 chip->ecc.read_page = nand_read_page_raw;
3391 chip->ecc.write_page = nand_write_page_raw;
3392 chip->ecc.read_oob = nand_read_oob_std;
3393 chip->ecc.read_page_raw = nand_read_page_raw;
3394 chip->ecc.write_page_raw = nand_write_page_raw;
3395 chip->ecc.write_oob = nand_write_oob_std;
3396 chip->ecc.size = mtd->writesize;
3397 chip->ecc.bytes = 0;
3398 break;
3399
3400 default:
3401 printk(KERN_WARNING "Invalid NAND_ECC_MODE %d\n",
3402 chip->ecc.mode);
3403 BUG();
3404 }
3405
3406 /*
3407 * The number of bytes available for a client to place data into
3408 * the out of band area
3409 */
3410 chip->ecc.layout->oobavail = 0;
3411 for (i = 0; chip->ecc.layout->oobfree[i].length
3412 && i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
3413 chip->ecc.layout->oobavail +=
3414 chip->ecc.layout->oobfree[i].length;
3415 mtd->oobavail = chip->ecc.layout->oobavail;
3416
3417 /*
3418 * Set the number of read / write steps for one page depending on ECC
3419 * mode
3420 */
3421 chip->ecc.steps = mtd->writesize / chip->ecc.size;
3422 if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
3423 printk(KERN_WARNING "Invalid ecc parameters\n");
3424 BUG();
3425 }
3426 chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
3427
3428 /*
3429 * Allow subpage writes up to ecc.steps. Not possible for MLC
3430 * FLASH.
3431 */
3432 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
3433 !(chip->cellinfo & NAND_CI_CELLTYPE_MSK)) {
3434 switch (chip->ecc.steps) {
3435 case 2:
3436 mtd->subpage_sft = 1;
3437 break;
3438 case 4:
3439 case 8:
3440 case 16:
3441 mtd->subpage_sft = 2;
3442 break;
3443 }
3444 }
3445 chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
3446
3447 /* Initialize state */
3448 chip->state = FL_READY;
3449
3450 /* De-select the device */
3451 chip->select_chip(mtd, -1);
3452
3453 /* Invalidate the pagebuffer reference */
3454 chip->pagebuf = -1;
3455
3456 /* Fill in remaining MTD driver data */
3457 mtd->type = MTD_NANDFLASH;
3458 mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
3459 MTD_CAP_NANDFLASH;
3460 mtd->erase = nand_erase;
3461 mtd->point = NULL;
3462 mtd->unpoint = NULL;
3463 mtd->read = nand_read;
3464 mtd->write = nand_write;
3465 mtd->panic_write = panic_nand_write;
3466 mtd->read_oob = nand_read_oob;
3467 mtd->write_oob = nand_write_oob;
3468 mtd->sync = nand_sync;
3469 mtd->lock = NULL;
3470 mtd->unlock = NULL;
3471 mtd->suspend = nand_suspend;
3472 mtd->resume = nand_resume;
3473 mtd->block_isbad = nand_block_isbad;
3474 mtd->block_markbad = nand_block_markbad;
3475 mtd->writebufsize = mtd->writesize;
3476
3477 /* propagate ecc.layout to mtd_info */
3478 mtd->ecclayout = chip->ecc.layout;
3479
3480 /* Check, if we should skip the bad block table scan */
3481 if (chip->options & NAND_SKIP_BBTSCAN)
3482 return 0;
3483
3484 /* Build bad block table */
3485 return chip->scan_bbt(mtd);
3486 }
3487 EXPORT_SYMBOL(nand_scan_tail);
3488
3489 /* is_module_text_address() isn't exported, and it's mostly a pointless
3490 * test if this is a module _anyway_ -- they'd have to try _really_ hard
3491 * to call us from in-kernel code if the core NAND support is modular. */
3492 #ifdef MODULE
3493 #define caller_is_module() (1)
3494 #else
3495 #define caller_is_module() \
3496 is_module_text_address((unsigned long)__builtin_return_address(0))
3497 #endif
3498
3499 /**
3500 * nand_scan - [NAND Interface] Scan for the NAND device
3501 * @mtd: MTD device structure
3502 * @maxchips: Number of chips to scan for
3503 *
3504 * This fills out all the uninitialized function pointers
3505 * with the defaults.
3506 * The flash ID is read and the mtd/chip structures are
3507 * filled with the appropriate values.
3508 * The mtd->owner field must be set to the module of the caller
3509 *
3510 */
3511 int nand_scan(struct mtd_info *mtd, int maxchips)
3512 {
3513 int ret;
3514
3515 /* Many callers got this wrong, so check for it for a while... */
3516 if (!mtd->owner && caller_is_module()) {
3517 printk(KERN_CRIT "%s called with NULL mtd->owner!\n",
3518 __func__);
3519 BUG();
3520 }
3521
3522 ret = nand_scan_ident(mtd, maxchips, NULL);
3523 if (!ret)
3524 ret = nand_scan_tail(mtd);
3525 return ret;
3526 }
3527 EXPORT_SYMBOL(nand_scan);
3528
3529 /**
3530 * nand_release - [NAND Interface] Free resources held by the NAND device
3531 * @mtd: MTD device structure
3532 */
3533 void nand_release(struct mtd_info *mtd)
3534 {
3535 struct nand_chip *chip = mtd->priv;
3536
3537 if (chip->ecc.mode == NAND_ECC_SOFT_BCH)
3538 nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
3539
3540 mtd_device_unregister(mtd);
3541
3542 /* Free bad block table memory */
3543 kfree(chip->bbt);
3544 if (!(chip->options & NAND_OWN_BUFFERS))
3545 kfree(chip->buffers);
3546
3547 /* Free bad block descriptor memory */
3548 if (chip->badblock_pattern && chip->badblock_pattern->options
3549 & NAND_BBT_DYNAMICSTRUCT)
3550 kfree(chip->badblock_pattern);
3551 }
3552 EXPORT_SYMBOL_GPL(nand_release);
3553
3554 static int __init nand_base_init(void)
3555 {
3556 led_trigger_register_simple("nand-disk", &nand_led_trigger);
3557 return 0;
3558 }
3559
3560 static void __exit nand_base_exit(void)
3561 {
3562 led_trigger_unregister_simple(nand_led_trigger);
3563 }
3564
3565 module_init(nand_base_init);
3566 module_exit(nand_base_exit);
3567
3568 MODULE_LICENSE("GPL");
3569 MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
3570 MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
3571 MODULE_DESCRIPTION("Generic NAND flash driver code");
Linux with added FPC-III support