?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / net / 8139cp.c
bloba8b82da3956ef81a6f3e52dc6159916a96b06d5a
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/delay.h>
66 #include <linux/ethtool.h>
67 #include <linux/gfp.h>
68 #include <linux/mii.h>
69 #include <linux/if_vlan.h>
70 #include <linux/crc32.h>
71 #include <linux/in.h>
72 #include <linux/ip.h>
73 #include <linux/tcp.h>
74 #include <linux/udp.h>
75 #include <linux/cache.h>
76 #include <asm/io.h>
77 #include <asm/irq.h>
78 #include <asm/uaccess.h>
79
80 /* VLAN tagging feature enable/disable */
81 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
82 #define CP_VLAN_TAG_USED 1
83 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
84 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
85 #else
86 #define CP_VLAN_TAG_USED 0
87 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
88 do { (tx_desc)->opts2 = 0; } while (0)
89 #endif
90
91 /* These identify the driver base version and may not be removed. */
92 static char version[] =
93 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
94
95 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
96 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
97 MODULE_VERSION(DRV_VERSION);
98 MODULE_LICENSE("GPL");
99
100 static int debug = -1;
101 module_param(debug, int, 0);
102 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
103
104 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
105 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
106 static int multicast_filter_limit = 32;
107 module_param(multicast_filter_limit, int, 0);
108 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
109
110 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
111 NETIF_MSG_PROBE | \
112 NETIF_MSG_LINK)
113 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
114 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
115 #define CP_REGS_SIZE (0xff + 1)
116 #define CP_REGS_VER 1 /* version 1 */
117 #define CP_RX_RING_SIZE 64
118 #define CP_TX_RING_SIZE 64
119 #define CP_RING_BYTES \
120 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
121 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
122 CP_STATS_SIZE)
123 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
124 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
125 #define TX_BUFFS_AVAIL(CP) \
126 (((CP)->tx_tail <= (CP)->tx_head) ? \
127 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
128 (CP)->tx_tail - (CP)->tx_head - 1)
129
130 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
131 #define CP_INTERNAL_PHY 32
132
133 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
134 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
135 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
136 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
137 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
138
139 /* Time in jiffies before concluding the transmitter is hung. */
140 #define TX_TIMEOUT (6*HZ)
141
142 /* hardware minimum and maximum for a single frame's data payload */
143 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
144 #define CP_MAX_MTU 4096
145
146 enum {
147 /* NIC register offsets */
148 MAC0 = 0x00, /* Ethernet hardware address. */
149 MAR0 = 0x08, /* Multicast filter. */
150 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
151 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
152 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
153 Cmd = 0x37, /* Command register */
154 IntrMask = 0x3C, /* Interrupt mask */
155 IntrStatus = 0x3E, /* Interrupt status */
156 TxConfig = 0x40, /* Tx configuration */
157 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
158 RxConfig = 0x44, /* Rx configuration */
159 RxMissed = 0x4C, /* 24 bits valid, write clears */
160 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
161 Config1 = 0x52, /* Config1 */
162 Config3 = 0x59, /* Config3 */
163 Config4 = 0x5A, /* Config4 */
164 MultiIntr = 0x5C, /* Multiple interrupt select */
165 BasicModeCtrl = 0x62, /* MII BMCR */
166 BasicModeStatus = 0x64, /* MII BMSR */
167 NWayAdvert = 0x66, /* MII ADVERTISE */
168 NWayLPAR = 0x68, /* MII LPA */
169 NWayExpansion = 0x6A, /* MII Expansion */
170 Config5 = 0xD8, /* Config5 */
171 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
172 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
173 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
174 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
175 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
176 TxThresh = 0xEC, /* Early Tx threshold */
177 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
178 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
179
180 /* Tx and Rx status descriptors */
181 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
182 RingEnd = (1 << 30), /* End of descriptor ring */
183 FirstFrag = (1 << 29), /* First segment of a packet */
184 LastFrag = (1 << 28), /* Final segment of a packet */
185 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
186 MSSShift = 16, /* MSS value position */
187 MSSMask = 0xfff, /* MSS value: 11 bits */
188 TxError = (1 << 23), /* Tx error summary */
189 RxError = (1 << 20), /* Rx error summary */
190 IPCS = (1 << 18), /* Calculate IP checksum */
191 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
192 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
193 TxVlanTag = (1 << 17), /* Add VLAN tag */
194 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
195 IPFail = (1 << 15), /* IP checksum failed */
196 UDPFail = (1 << 14), /* UDP/IP checksum failed */
197 TCPFail = (1 << 13), /* TCP/IP checksum failed */
198 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
199 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
200 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
201 RxProtoTCP = 1,
202 RxProtoUDP = 2,
203 RxProtoIP = 3,
204 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
205 TxOWC = (1 << 22), /* Tx Out-of-window collision */
206 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
207 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
208 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
209 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
210 RxErrFrame = (1 << 27), /* Rx frame alignment error */
211 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
212 RxErrCRC = (1 << 18), /* Rx CRC error */
213 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
214 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
215 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
216
217 /* StatsAddr register */
218 DumpStats = (1 << 3), /* Begin stats dump */
219
220 /* RxConfig register */
221 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
222 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
223 AcceptErr = 0x20, /* Accept packets with CRC errors */
224 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
225 AcceptBroadcast = 0x08, /* Accept broadcast packets */
226 AcceptMulticast = 0x04, /* Accept multicast packets */
227 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
228 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
229
230 /* IntrMask / IntrStatus registers */
231 PciErr = (1 << 15), /* System error on the PCI bus */
232 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
233 LenChg = (1 << 13), /* Cable length change */
234 SWInt = (1 << 8), /* Software-requested interrupt */
235 TxEmpty = (1 << 7), /* No Tx descriptors available */
236 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
237 LinkChg = (1 << 5), /* Packet underrun, or link change */
238 RxEmpty = (1 << 4), /* No Rx descriptors available */
239 TxErr = (1 << 3), /* Tx error */
240 TxOK = (1 << 2), /* Tx packet sent */
241 RxErr = (1 << 1), /* Rx error */
242 RxOK = (1 << 0), /* Rx packet received */
243 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
244 but hardware likes to raise it */
245
246 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
247 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
248 RxErr | RxOK | IntrResvd,
249
250 /* C mode command register */
251 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
252 RxOn = (1 << 3), /* Rx mode enable */
253 TxOn = (1 << 2), /* Tx mode enable */
254
255 /* C+ mode command register */
256 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
257 RxChkSum = (1 << 5), /* Rx checksum offload enable */
258 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
259 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
260 CpRxOn = (1 << 1), /* Rx mode enable */
261 CpTxOn = (1 << 0), /* Tx mode enable */
262
263 /* Cfg9436 EEPROM control register */
264 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
265 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
266
267 /* TxConfig register */
268 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
269 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
270
271 /* Early Tx Threshold register */
272 TxThreshMask = 0x3f, /* Mask bits 5-0 */
273 TxThreshMax = 2048, /* Max early Tx threshold */
274
275 /* Config1 register */
276 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
277 LWACT = (1 << 4), /* LWAKE active mode */
278 PMEnable = (1 << 0), /* Enable various PM features of chip */
279
280 /* Config3 register */
281 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
282 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
283 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
284
285 /* Config4 register */
286 LWPTN = (1 << 1), /* LWAKE Pattern */
287 LWPME = (1 << 4), /* LANWAKE vs PMEB */
288
289 /* Config5 register */
290 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
291 MWF = (1 << 5), /* Accept Multicast wakeup frame */
292 UWF = (1 << 4), /* Accept Unicast wakeup frame */
293 LANWake = (1 << 1), /* Enable LANWake signal */
294 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
295
296 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
297 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
298 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
299 };
300
301 static const unsigned int cp_rx_config =
302 (RX_FIFO_THRESH << RxCfgFIFOShift) |
303 (RX_DMA_BURST << RxCfgDMAShift);
304
305 struct cp_desc {
306 __le32 opts1;
307 __le32 opts2;
308 __le64 addr;
309 };
310
311 struct cp_dma_stats {
312 __le64 tx_ok;
313 __le64 rx_ok;
314 __le64 tx_err;
315 __le32 rx_err;
316 __le16 rx_fifo;
317 __le16 frame_align;
318 __le32 tx_ok_1col;
319 __le32 tx_ok_mcol;
320 __le64 rx_ok_phys;
321 __le64 rx_ok_bcast;
322 __le32 rx_ok_mcast;
323 __le16 tx_abort;
324 __le16 tx_underrun;
325 } __packed;
326
327 struct cp_extra_stats {
328 unsigned long rx_frags;
329 };
330
331 struct cp_private {
332 void __iomem *regs;
333 struct net_device *dev;
334 spinlock_t lock;
335 u32 msg_enable;
336
337 struct napi_struct napi;
338
339 struct pci_dev *pdev;
340 u32 rx_config;
341 u16 cpcmd;
342
343 struct cp_extra_stats cp_stats;
344
345 unsigned rx_head ____cacheline_aligned;
346 unsigned rx_tail;
347 struct cp_desc *rx_ring;
348 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
349
350 unsigned tx_head ____cacheline_aligned;
351 unsigned tx_tail;
352 struct cp_desc *tx_ring;
353 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
354
355 unsigned rx_buf_sz;
356 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
357
358 #if CP_VLAN_TAG_USED
359 struct vlan_group *vlgrp;
360 #endif
361 dma_addr_t ring_dma;
362
363 struct mii_if_info mii_if;
364 };
365
366 #define cpr8(reg) readb(cp->regs + (reg))
367 #define cpr16(reg) readw(cp->regs + (reg))
368 #define cpr32(reg) readl(cp->regs + (reg))
369 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
370 #define cpw16(reg,val) writew((val), cp->regs + (reg))
371 #define cpw32(reg,val) writel((val), cp->regs + (reg))
372 #define cpw8_f(reg,val) do { \
373 writeb((val), cp->regs + (reg)); \
374 readb(cp->regs + (reg)); \
375 } while (0)
376 #define cpw16_f(reg,val) do { \
377 writew((val), cp->regs + (reg)); \
378 readw(cp->regs + (reg)); \
379 } while (0)
380 #define cpw32_f(reg,val) do { \
381 writel((val), cp->regs + (reg)); \
382 readl(cp->regs + (reg)); \
383 } while (0)
384
385
386 static void __cp_set_rx_mode (struct net_device *dev);
387 static void cp_tx (struct cp_private *cp);
388 static void cp_clean_rings (struct cp_private *cp);
389 #ifdef CONFIG_NET_POLL_CONTROLLER
390 static void cp_poll_controller(struct net_device *dev);
391 #endif
392 static int cp_get_eeprom_len(struct net_device *dev);
393 static int cp_get_eeprom(struct net_device *dev,
394 struct ethtool_eeprom *eeprom, u8 *data);
395 static int cp_set_eeprom(struct net_device *dev,
396 struct ethtool_eeprom *eeprom, u8 *data);
397
398 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
399 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
400 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
401 { },
402 };
403 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
404
405 static struct {
406 const char str[ETH_GSTRING_LEN];
407 } ethtool_stats_keys[] = {
408 { "tx_ok" },
409 { "rx_ok" },
410 { "tx_err" },
411 { "rx_err" },
412 { "rx_fifo" },
413 { "frame_align" },
414 { "tx_ok_1col" },
415 { "tx_ok_mcol" },
416 { "rx_ok_phys" },
417 { "rx_ok_bcast" },
418 { "rx_ok_mcast" },
419 { "tx_abort" },
420 { "tx_underrun" },
421 { "rx_frags" },
422 };
423
424
425 #if CP_VLAN_TAG_USED
426 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
427 {
428 struct cp_private *cp = netdev_priv(dev);
429 unsigned long flags;
430
431 spin_lock_irqsave(&cp->lock, flags);
432 cp->vlgrp = grp;
433 if (grp)
434 cp->cpcmd |= RxVlanOn;
435 else
436 cp->cpcmd &= ~RxVlanOn;
437
438 cpw16(CpCmd, cp->cpcmd);
439 spin_unlock_irqrestore(&cp->lock, flags);
440 }
441 #endif /* CP_VLAN_TAG_USED */
442
443 static inline void cp_set_rxbufsize (struct cp_private *cp)
444 {
445 unsigned int mtu = cp->dev->mtu;
446
447 if (mtu > ETH_DATA_LEN)
448 /* MTU + ethernet header + FCS + optional VLAN tag */
449 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
450 else
451 cp->rx_buf_sz = PKT_BUF_SZ;
452 }
453
454 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
455 struct cp_desc *desc)
456 {
457 skb->protocol = eth_type_trans (skb, cp->dev);
458
459 cp->dev->stats.rx_packets++;
460 cp->dev->stats.rx_bytes += skb->len;
461
462 #if CP_VLAN_TAG_USED
463 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
464 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
465 swab16(le32_to_cpu(desc->opts2) & 0xffff));
466 } else
467 #endif
468 netif_receive_skb(skb);
469 }
470
471 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
472 u32 status, u32 len)
473 {
474 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
475 rx_tail, status, len);
476 cp->dev->stats.rx_errors++;
477 if (status & RxErrFrame)
478 cp->dev->stats.rx_frame_errors++;
479 if (status & RxErrCRC)
480 cp->dev->stats.rx_crc_errors++;
481 if ((status & RxErrRunt) || (status & RxErrLong))
482 cp->dev->stats.rx_length_errors++;
483 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
484 cp->dev->stats.rx_length_errors++;
485 if (status & RxErrFIFO)
486 cp->dev->stats.rx_fifo_errors++;
487 }
488
489 static inline unsigned int cp_rx_csum_ok (u32 status)
490 {
491 unsigned int protocol = (status >> 16) & 0x3;
492
493 if (((protocol == RxProtoTCP) && !(status & TCPFail)) ||
494 ((protocol == RxProtoUDP) && !(status & UDPFail)))
495 return 1;
496 else
497 return 0;
498 }
499
500 static int cp_rx_poll(struct napi_struct *napi, int budget)
501 {
502 struct cp_private *cp = container_of(napi, struct cp_private, napi);
503 struct net_device *dev = cp->dev;
504 unsigned int rx_tail = cp->rx_tail;
505 int rx;
506
507 rx_status_loop:
508 rx = 0;
509 cpw16(IntrStatus, cp_rx_intr_mask);
510
511 while (1) {
512 u32 status, len;
513 dma_addr_t mapping;
514 struct sk_buff *skb, *new_skb;
515 struct cp_desc *desc;
516 const unsigned buflen = cp->rx_buf_sz;
517
518 skb = cp->rx_skb[rx_tail];
519 BUG_ON(!skb);
520
521 desc = &cp->rx_ring[rx_tail];
522 status = le32_to_cpu(desc->opts1);
523 if (status & DescOwn)
524 break;
525
526 len = (status & 0x1fff) - 4;
527 mapping = le64_to_cpu(desc->addr);
528
529 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
530 /* we don't support incoming fragmented frames.
531 * instead, we attempt to ensure that the
532 * pre-allocated RX skbs are properly sized such
533 * that RX fragments are never encountered
534 */
535 cp_rx_err_acct(cp, rx_tail, status, len);
536 dev->stats.rx_dropped++;
537 cp->cp_stats.rx_frags++;
538 goto rx_next;
539 }
540
541 if (status & (RxError | RxErrFIFO)) {
542 cp_rx_err_acct(cp, rx_tail, status, len);
543 goto rx_next;
544 }
545
546 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
547 rx_tail, status, len);
548
549 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
550 if (!new_skb) {
551 dev->stats.rx_dropped++;
552 goto rx_next;
553 }
554
555 dma_unmap_single(&cp->pdev->dev, mapping,
556 buflen, PCI_DMA_FROMDEVICE);
557
558 /* Handle checksum offloading for incoming packets. */
559 if (cp_rx_csum_ok(status))
560 skb->ip_summed = CHECKSUM_UNNECESSARY;
561 else
562 skb_checksum_none_assert(skb);
563
564 skb_put(skb, len);
565
566 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
567 PCI_DMA_FROMDEVICE);
568 cp->rx_skb[rx_tail] = new_skb;
569
570 cp_rx_skb(cp, skb, desc);
571 rx++;
572
573 rx_next:
574 cp->rx_ring[rx_tail].opts2 = 0;
575 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
576 if (rx_tail == (CP_RX_RING_SIZE - 1))
577 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
578 cp->rx_buf_sz);
579 else
580 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
581 rx_tail = NEXT_RX(rx_tail);
582
583 if (rx >= budget)
584 break;
585 }
586
587 cp->rx_tail = rx_tail;
588
589 /* if we did not reach work limit, then we're done with
590 * this round of polling
591 */
592 if (rx < budget) {
593 unsigned long flags;
594
595 if (cpr16(IntrStatus) & cp_rx_intr_mask)
596 goto rx_status_loop;
597
598 spin_lock_irqsave(&cp->lock, flags);
599 __napi_complete(napi);
600 cpw16_f(IntrMask, cp_intr_mask);
601 spin_unlock_irqrestore(&cp->lock, flags);
602 }
603
604 return rx;
605 }
606
607 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
608 {
609 struct net_device *dev = dev_instance;
610 struct cp_private *cp;
611 u16 status;
612
613 if (unlikely(dev == NULL))
614 return IRQ_NONE;
615 cp = netdev_priv(dev);
616
617 status = cpr16(IntrStatus);
618 if (!status || (status == 0xFFFF))
619 return IRQ_NONE;
620
621 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
622 status, cpr8(Cmd), cpr16(CpCmd));
623
624 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
625
626 spin_lock(&cp->lock);
627
628 /* close possible race's with dev_close */
629 if (unlikely(!netif_running(dev))) {
630 cpw16(IntrMask, 0);
631 spin_unlock(&cp->lock);
632 return IRQ_HANDLED;
633 }
634
635 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
636 if (napi_schedule_prep(&cp->napi)) {
637 cpw16_f(IntrMask, cp_norx_intr_mask);
638 __napi_schedule(&cp->napi);
639 }
640
641 if (status & (TxOK | TxErr | TxEmpty | SWInt))
642 cp_tx(cp);
643 if (status & LinkChg)
644 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
645
646 spin_unlock(&cp->lock);
647
648 if (status & PciErr) {
649 u16 pci_status;
650
651 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
652 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
653 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
654 status, pci_status);
655
656 /* TODO: reset hardware */
657 }
658
659 return IRQ_HANDLED;
660 }
661
662 #ifdef CONFIG_NET_POLL_CONTROLLER
663 /*
664 * Polling receive - used by netconsole and other diagnostic tools
665 * to allow network i/o with interrupts disabled.
666 */
667 static void cp_poll_controller(struct net_device *dev)
668 {
669 disable_irq(dev->irq);
670 cp_interrupt(dev->irq, dev);
671 enable_irq(dev->irq);
672 }
673 #endif
674
675 static void cp_tx (struct cp_private *cp)
676 {
677 unsigned tx_head = cp->tx_head;
678 unsigned tx_tail = cp->tx_tail;
679
680 while (tx_tail != tx_head) {
681 struct cp_desc *txd = cp->tx_ring + tx_tail;
682 struct sk_buff *skb;
683 u32 status;
684
685 rmb();
686 status = le32_to_cpu(txd->opts1);
687 if (status & DescOwn)
688 break;
689
690 skb = cp->tx_skb[tx_tail];
691 BUG_ON(!skb);
692
693 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
694 le32_to_cpu(txd->opts1) & 0xffff,
695 PCI_DMA_TODEVICE);
696
697 if (status & LastFrag) {
698 if (status & (TxError | TxFIFOUnder)) {
699 netif_dbg(cp, tx_err, cp->dev,
700 "tx err, status 0x%x\n", status);
701 cp->dev->stats.tx_errors++;
702 if (status & TxOWC)
703 cp->dev->stats.tx_window_errors++;
704 if (status & TxMaxCol)
705 cp->dev->stats.tx_aborted_errors++;
706 if (status & TxLinkFail)
707 cp->dev->stats.tx_carrier_errors++;
708 if (status & TxFIFOUnder)
709 cp->dev->stats.tx_fifo_errors++;
710 } else {
711 cp->dev->stats.collisions +=
712 ((status >> TxColCntShift) & TxColCntMask);
713 cp->dev->stats.tx_packets++;
714 cp->dev->stats.tx_bytes += skb->len;
715 netif_dbg(cp, tx_done, cp->dev,
716 "tx done, slot %d\n", tx_tail);
717 }
718 dev_kfree_skb_irq(skb);
719 }
720
721 cp->tx_skb[tx_tail] = NULL;
722
723 tx_tail = NEXT_TX(tx_tail);
724 }
725
726 cp->tx_tail = tx_tail;
727
728 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
729 netif_wake_queue(cp->dev);
730 }
731
732 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
733 struct net_device *dev)
734 {
735 struct cp_private *cp = netdev_priv(dev);
736 unsigned entry;
737 u32 eor, flags;
738 unsigned long intr_flags;
739 #if CP_VLAN_TAG_USED
740 u32 vlan_tag = 0;
741 #endif
742 int mss = 0;
743
744 spin_lock_irqsave(&cp->lock, intr_flags);
745
746 /* This is a hard error, log it. */
747 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
748 netif_stop_queue(dev);
749 spin_unlock_irqrestore(&cp->lock, intr_flags);
750 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
751 return NETDEV_TX_BUSY;
752 }
753
754 #if CP_VLAN_TAG_USED
755 if (vlan_tx_tag_present(skb))
756 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
757 #endif
758
759 entry = cp->tx_head;
760 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
761 mss = skb_shinfo(skb)->gso_size;
762
763 if (skb_shinfo(skb)->nr_frags == 0) {
764 struct cp_desc *txd = &cp->tx_ring[entry];
765 u32 len;
766 dma_addr_t mapping;
767
768 len = skb->len;
769 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
770 CP_VLAN_TX_TAG(txd, vlan_tag);
771 txd->addr = cpu_to_le64(mapping);
772 wmb();
773
774 flags = eor | len | DescOwn | FirstFrag | LastFrag;
775
776 if (mss)
777 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
778 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
779 const struct iphdr *ip = ip_hdr(skb);
780 if (ip->protocol == IPPROTO_TCP)
781 flags |= IPCS | TCPCS;
782 else if (ip->protocol == IPPROTO_UDP)
783 flags |= IPCS | UDPCS;
784 else
785 WARN_ON(1); /* we need a WARN() */
786 }
787
788 txd->opts1 = cpu_to_le32(flags);
789 wmb();
790
791 cp->tx_skb[entry] = skb;
792 entry = NEXT_TX(entry);
793 } else {
794 struct cp_desc *txd;
795 u32 first_len, first_eor;
796 dma_addr_t first_mapping;
797 int frag, first_entry = entry;
798 const struct iphdr *ip = ip_hdr(skb);
799
800 /* We must give this initial chunk to the device last.
801 * Otherwise we could race with the device.
802 */
803 first_eor = eor;
804 first_len = skb_headlen(skb);
805 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
806 first_len, PCI_DMA_TODEVICE);
807 cp->tx_skb[entry] = skb;
808 entry = NEXT_TX(entry);
809
810 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
811 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
812 u32 len;
813 u32 ctrl;
814 dma_addr_t mapping;
815
816 len = this_frag->size;
817 mapping = dma_map_single(&cp->pdev->dev,
818 ((void *) page_address(this_frag->page) +
819 this_frag->page_offset),
820 len, PCI_DMA_TODEVICE);
821 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
822
823 ctrl = eor | len | DescOwn;
824
825 if (mss)
826 ctrl |= LargeSend |
827 ((mss & MSSMask) << MSSShift);
828 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
829 if (ip->protocol == IPPROTO_TCP)
830 ctrl |= IPCS | TCPCS;
831 else if (ip->protocol == IPPROTO_UDP)
832 ctrl |= IPCS | UDPCS;
833 else
834 BUG();
835 }
836
837 if (frag == skb_shinfo(skb)->nr_frags - 1)
838 ctrl |= LastFrag;
839
840 txd = &cp->tx_ring[entry];
841 CP_VLAN_TX_TAG(txd, vlan_tag);
842 txd->addr = cpu_to_le64(mapping);
843 wmb();
844
845 txd->opts1 = cpu_to_le32(ctrl);
846 wmb();
847
848 cp->tx_skb[entry] = skb;
849 entry = NEXT_TX(entry);
850 }
851
852 txd = &cp->tx_ring[first_entry];
853 CP_VLAN_TX_TAG(txd, vlan_tag);
854 txd->addr = cpu_to_le64(first_mapping);
855 wmb();
856
857 if (skb->ip_summed == CHECKSUM_PARTIAL) {
858 if (ip->protocol == IPPROTO_TCP)
859 txd->opts1 = cpu_to_le32(first_eor | first_len |
860 FirstFrag | DescOwn |
861 IPCS | TCPCS);
862 else if (ip->protocol == IPPROTO_UDP)
863 txd->opts1 = cpu_to_le32(first_eor | first_len |
864 FirstFrag | DescOwn |
865 IPCS | UDPCS);
866 else
867 BUG();
868 } else
869 txd->opts1 = cpu_to_le32(first_eor | first_len |
870 FirstFrag | DescOwn);
871 wmb();
872 }
873 cp->tx_head = entry;
874 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
875 entry, skb->len);
876 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
877 netif_stop_queue(dev);
878
879 spin_unlock_irqrestore(&cp->lock, intr_flags);
880
881 cpw8(TxPoll, NormalTxPoll);
882
883 return NETDEV_TX_OK;
884 }
885
886 /* Set or clear the multicast filter for this adaptor.
887 This routine is not state sensitive and need not be SMP locked. */
888
889 static void __cp_set_rx_mode (struct net_device *dev)
890 {
891 struct cp_private *cp = netdev_priv(dev);
892 u32 mc_filter[2]; /* Multicast hash filter */
893 int rx_mode;
894 u32 tmp;
895
896 /* Note: do not reorder, GCC is clever about common statements. */
897 if (dev->flags & IFF_PROMISC) {
898 /* Unconditionally log net taps. */
899 rx_mode =
900 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
901 AcceptAllPhys;
902 mc_filter[1] = mc_filter[0] = 0xffffffff;
903 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
904 (dev->flags & IFF_ALLMULTI)) {
905 /* Too many to filter perfectly -- accept all multicasts. */
906 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
907 mc_filter[1] = mc_filter[0] = 0xffffffff;
908 } else {
909 struct netdev_hw_addr *ha;
910 rx_mode = AcceptBroadcast | AcceptMyPhys;
911 mc_filter[1] = mc_filter[0] = 0;
912 netdev_for_each_mc_addr(ha, dev) {
913 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
914
915 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
916 rx_mode |= AcceptMulticast;
917 }
918 }
919
920 /* We can safely update without stopping the chip. */
921 tmp = cp_rx_config | rx_mode;
922 if (cp->rx_config != tmp) {
923 cpw32_f (RxConfig, tmp);
924 cp->rx_config = tmp;
925 }
926 cpw32_f (MAR0 + 0, mc_filter[0]);
927 cpw32_f (MAR0 + 4, mc_filter[1]);
928 }
929
930 static void cp_set_rx_mode (struct net_device *dev)
931 {
932 unsigned long flags;
933 struct cp_private *cp = netdev_priv(dev);
934
935 spin_lock_irqsave (&cp->lock, flags);
936 __cp_set_rx_mode(dev);
937 spin_unlock_irqrestore (&cp->lock, flags);
938 }
939
940 static void __cp_get_stats(struct cp_private *cp)
941 {
942 /* only lower 24 bits valid; write any value to clear */
943 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
944 cpw32 (RxMissed, 0);
945 }
946
947 static struct net_device_stats *cp_get_stats(struct net_device *dev)
948 {
949 struct cp_private *cp = netdev_priv(dev);
950 unsigned long flags;
951
952 /* The chip only need report frame silently dropped. */
953 spin_lock_irqsave(&cp->lock, flags);
954 if (netif_running(dev) && netif_device_present(dev))
955 __cp_get_stats(cp);
956 spin_unlock_irqrestore(&cp->lock, flags);
957
958 return &dev->stats;
959 }
960
961 static void cp_stop_hw (struct cp_private *cp)
962 {
963 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
964 cpw16_f(IntrMask, 0);
965 cpw8(Cmd, 0);
966 cpw16_f(CpCmd, 0);
967 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
968
969 cp->rx_tail = 0;
970 cp->tx_head = cp->tx_tail = 0;
971 }
972
973 static void cp_reset_hw (struct cp_private *cp)
974 {
975 unsigned work = 1000;
976
977 cpw8(Cmd, CmdReset);
978
979 while (work--) {
980 if (!(cpr8(Cmd) & CmdReset))
981 return;
982
983 schedule_timeout_uninterruptible(10);
984 }
985
986 netdev_err(cp->dev, "hardware reset timeout\n");
987 }
988
989 static inline void cp_start_hw (struct cp_private *cp)
990 {
991 cpw16(CpCmd, cp->cpcmd);
992 cpw8(Cmd, RxOn | TxOn);
993 }
994
995 static void cp_enable_irq(struct cp_private *cp)
996 {
997 cpw16_f(IntrMask, cp_intr_mask);
998 }
999
1000 static void cp_init_hw (struct cp_private *cp)
1001 {
1002 struct net_device *dev = cp->dev;
1003 dma_addr_t ring_dma;
1004
1005 cp_reset_hw(cp);
1006
1007 cpw8_f (Cfg9346, Cfg9346_Unlock);
1008
1009 /* Restore our idea of the MAC address. */
1010 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1011 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1012
1013 cp_start_hw(cp);
1014 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1015
1016 __cp_set_rx_mode(dev);
1017 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1018
1019 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1020 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1021 cpw8(Config3, PARMEnable);
1022 cp->wol_enabled = 0;
1023
1024 cpw8(Config5, cpr8(Config5) & PMEStatus);
1025
1026 cpw32_f(HiTxRingAddr, 0);
1027 cpw32_f(HiTxRingAddr + 4, 0);
1028
1029 ring_dma = cp->ring_dma;
1030 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1031 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1032
1033 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1034 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1035 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1036
1037 cpw16(MultiIntr, 0);
1038
1039 cpw8_f(Cfg9346, Cfg9346_Lock);
1040 }
1041
1042 static int cp_refill_rx(struct cp_private *cp)
1043 {
1044 struct net_device *dev = cp->dev;
1045 unsigned i;
1046
1047 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1048 struct sk_buff *skb;
1049 dma_addr_t mapping;
1050
1051 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1052 if (!skb)
1053 goto err_out;
1054
1055 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1056 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1057 cp->rx_skb[i] = skb;
1058
1059 cp->rx_ring[i].opts2 = 0;
1060 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1061 if (i == (CP_RX_RING_SIZE - 1))
1062 cp->rx_ring[i].opts1 =
1063 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1064 else
1065 cp->rx_ring[i].opts1 =
1066 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1067 }
1068
1069 return 0;
1070
1071 err_out:
1072 cp_clean_rings(cp);
1073 return -ENOMEM;
1074 }
1075
1076 static void cp_init_rings_index (struct cp_private *cp)
1077 {
1078 cp->rx_tail = 0;
1079 cp->tx_head = cp->tx_tail = 0;
1080 }
1081
1082 static int cp_init_rings (struct cp_private *cp)
1083 {
1084 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1085 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1086
1087 cp_init_rings_index(cp);
1088
1089 return cp_refill_rx (cp);
1090 }
1091
1092 static int cp_alloc_rings (struct cp_private *cp)
1093 {
1094 void *mem;
1095
1096 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1097 &cp->ring_dma, GFP_KERNEL);
1098 if (!mem)
1099 return -ENOMEM;
1100
1101 cp->rx_ring = mem;
1102 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1103
1104 return cp_init_rings(cp);
1105 }
1106
1107 static void cp_clean_rings (struct cp_private *cp)
1108 {
1109 struct cp_desc *desc;
1110 unsigned i;
1111
1112 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1113 if (cp->rx_skb[i]) {
1114 desc = cp->rx_ring + i;
1115 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1116 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1117 dev_kfree_skb(cp->rx_skb[i]);
1118 }
1119 }
1120
1121 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1122 if (cp->tx_skb[i]) {
1123 struct sk_buff *skb = cp->tx_skb[i];
1124
1125 desc = cp->tx_ring + i;
1126 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1127 le32_to_cpu(desc->opts1) & 0xffff,
1128 PCI_DMA_TODEVICE);
1129 if (le32_to_cpu(desc->opts1) & LastFrag)
1130 dev_kfree_skb(skb);
1131 cp->dev->stats.tx_dropped++;
1132 }
1133 }
1134
1135 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1136 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1137
1138 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1139 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1140 }
1141
1142 static void cp_free_rings (struct cp_private *cp)
1143 {
1144 cp_clean_rings(cp);
1145 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1146 cp->ring_dma);
1147 cp->rx_ring = NULL;
1148 cp->tx_ring = NULL;
1149 }
1150
1151 static int cp_open (struct net_device *dev)
1152 {
1153 struct cp_private *cp = netdev_priv(dev);
1154 int rc;
1155
1156 netif_dbg(cp, ifup, dev, "enabling interface\n");
1157
1158 rc = cp_alloc_rings(cp);
1159 if (rc)
1160 return rc;
1161
1162 napi_enable(&cp->napi);
1163
1164 cp_init_hw(cp);
1165
1166 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1167 if (rc)
1168 goto err_out_hw;
1169
1170 cp_enable_irq(cp);
1171
1172 netif_carrier_off(dev);
1173 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1174 netif_start_queue(dev);
1175
1176 return 0;
1177
1178 err_out_hw:
1179 napi_disable(&cp->napi);
1180 cp_stop_hw(cp);
1181 cp_free_rings(cp);
1182 return rc;
1183 }
1184
1185 static int cp_close (struct net_device *dev)
1186 {
1187 struct cp_private *cp = netdev_priv(dev);
1188 unsigned long flags;
1189
1190 napi_disable(&cp->napi);
1191
1192 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1193
1194 spin_lock_irqsave(&cp->lock, flags);
1195
1196 netif_stop_queue(dev);
1197 netif_carrier_off(dev);
1198
1199 cp_stop_hw(cp);
1200
1201 spin_unlock_irqrestore(&cp->lock, flags);
1202
1203 free_irq(dev->irq, dev);
1204
1205 cp_free_rings(cp);
1206 return 0;
1207 }
1208
1209 static void cp_tx_timeout(struct net_device *dev)
1210 {
1211 struct cp_private *cp = netdev_priv(dev);
1212 unsigned long flags;
1213 int rc;
1214
1215 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1216 cpr8(Cmd), cpr16(CpCmd),
1217 cpr16(IntrStatus), cpr16(IntrMask));
1218
1219 spin_lock_irqsave(&cp->lock, flags);
1220
1221 cp_stop_hw(cp);
1222 cp_clean_rings(cp);
1223 rc = cp_init_rings(cp);
1224 cp_start_hw(cp);
1225
1226 netif_wake_queue(dev);
1227
1228 spin_unlock_irqrestore(&cp->lock, flags);
1229 }
1230
1231 #ifdef BROKEN
1232 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1233 {
1234 struct cp_private *cp = netdev_priv(dev);
1235 int rc;
1236 unsigned long flags;
1237
1238 /* check for invalid MTU, according to hardware limits */
1239 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1240 return -EINVAL;
1241
1242 /* if network interface not up, no need for complexity */
1243 if (!netif_running(dev)) {
1244 dev->mtu = new_mtu;
1245 cp_set_rxbufsize(cp); /* set new rx buf size */
1246 return 0;
1247 }
1248
1249 spin_lock_irqsave(&cp->lock, flags);
1250
1251 cp_stop_hw(cp); /* stop h/w and free rings */
1252 cp_clean_rings(cp);
1253
1254 dev->mtu = new_mtu;
1255 cp_set_rxbufsize(cp); /* set new rx buf size */
1256
1257 rc = cp_init_rings(cp); /* realloc and restart h/w */
1258 cp_start_hw(cp);
1259
1260 spin_unlock_irqrestore(&cp->lock, flags);
1261
1262 return rc;
1263 }
1264 #endif /* BROKEN */
1265
1266 static const char mii_2_8139_map[8] = {
1267 BasicModeCtrl,
1268 BasicModeStatus,
1269 0,
1270 0,
1271 NWayAdvert,
1272 NWayLPAR,
1273 NWayExpansion,
1274 0
1275 };
1276
1277 static int mdio_read(struct net_device *dev, int phy_id, int location)
1278 {
1279 struct cp_private *cp = netdev_priv(dev);
1280
1281 return location < 8 && mii_2_8139_map[location] ?
1282 readw(cp->regs + mii_2_8139_map[location]) : 0;
1283 }
1284
1285
1286 static void mdio_write(struct net_device *dev, int phy_id, int location,
1287 int value)
1288 {
1289 struct cp_private *cp = netdev_priv(dev);
1290
1291 if (location == 0) {
1292 cpw8(Cfg9346, Cfg9346_Unlock);
1293 cpw16(BasicModeCtrl, value);
1294 cpw8(Cfg9346, Cfg9346_Lock);
1295 } else if (location < 8 && mii_2_8139_map[location])
1296 cpw16(mii_2_8139_map[location], value);
1297 }
1298
1299 /* Set the ethtool Wake-on-LAN settings */
1300 static int netdev_set_wol (struct cp_private *cp,
1301 const struct ethtool_wolinfo *wol)
1302 {
1303 u8 options;
1304
1305 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1306 /* If WOL is being disabled, no need for complexity */
1307 if (wol->wolopts) {
1308 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1309 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1310 }
1311
1312 cpw8 (Cfg9346, Cfg9346_Unlock);
1313 cpw8 (Config3, options);
1314 cpw8 (Cfg9346, Cfg9346_Lock);
1315
1316 options = 0; /* Paranoia setting */
1317 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1318 /* If WOL is being disabled, no need for complexity */
1319 if (wol->wolopts) {
1320 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1321 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1322 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1323 }
1324
1325 cpw8 (Config5, options);
1326
1327 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1328
1329 return 0;
1330 }
1331
1332 /* Get the ethtool Wake-on-LAN settings */
1333 static void netdev_get_wol (struct cp_private *cp,
1334 struct ethtool_wolinfo *wol)
1335 {
1336 u8 options;
1337
1338 wol->wolopts = 0; /* Start from scratch */
1339 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1340 WAKE_MCAST | WAKE_UCAST;
1341 /* We don't need to go on if WOL is disabled */
1342 if (!cp->wol_enabled) return;
1343
1344 options = cpr8 (Config3);
1345 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1346 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1347
1348 options = 0; /* Paranoia setting */
1349 options = cpr8 (Config5);
1350 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1351 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1352 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1353 }
1354
1355 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1356 {
1357 struct cp_private *cp = netdev_priv(dev);
1358
1359 strcpy (info->driver, DRV_NAME);
1360 strcpy (info->version, DRV_VERSION);
1361 strcpy (info->bus_info, pci_name(cp->pdev));
1362 }
1363
1364 static int cp_get_regs_len(struct net_device *dev)
1365 {
1366 return CP_REGS_SIZE;
1367 }
1368
1369 static int cp_get_sset_count (struct net_device *dev, int sset)
1370 {
1371 switch (sset) {
1372 case ETH_SS_STATS:
1373 return CP_NUM_STATS;
1374 default:
1375 return -EOPNOTSUPP;
1376 }
1377 }
1378
1379 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1380 {
1381 struct cp_private *cp = netdev_priv(dev);
1382 int rc;
1383 unsigned long flags;
1384
1385 spin_lock_irqsave(&cp->lock, flags);
1386 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1387 spin_unlock_irqrestore(&cp->lock, flags);
1388
1389 return rc;
1390 }
1391
1392 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1393 {
1394 struct cp_private *cp = netdev_priv(dev);
1395 int rc;
1396 unsigned long flags;
1397
1398 spin_lock_irqsave(&cp->lock, flags);
1399 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1400 spin_unlock_irqrestore(&cp->lock, flags);
1401
1402 return rc;
1403 }
1404
1405 static int cp_nway_reset(struct net_device *dev)
1406 {
1407 struct cp_private *cp = netdev_priv(dev);
1408 return mii_nway_restart(&cp->mii_if);
1409 }
1410
1411 static u32 cp_get_msglevel(struct net_device *dev)
1412 {
1413 struct cp_private *cp = netdev_priv(dev);
1414 return cp->msg_enable;
1415 }
1416
1417 static void cp_set_msglevel(struct net_device *dev, u32 value)
1418 {
1419 struct cp_private *cp = netdev_priv(dev);
1420 cp->msg_enable = value;
1421 }
1422
1423 static int cp_set_features(struct net_device *dev, u32 features)
1424 {
1425 struct cp_private *cp = netdev_priv(dev);
1426 unsigned long flags;
1427
1428 if (!((dev->features ^ features) & NETIF_F_RXCSUM))
1429 return 0;
1430
1431 spin_lock_irqsave(&cp->lock, flags);
1432
1433 if (features & NETIF_F_RXCSUM)
1434 cp->cpcmd |= RxChkSum;
1435 else
1436 cp->cpcmd &= ~RxChkSum;
1437
1438 cpw16_f(CpCmd, cp->cpcmd);
1439 spin_unlock_irqrestore(&cp->lock, flags);
1440
1441 return 0;
1442 }
1443
1444 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1445 void *p)
1446 {
1447 struct cp_private *cp = netdev_priv(dev);
1448 unsigned long flags;
1449
1450 if (regs->len < CP_REGS_SIZE)
1451 return /* -EINVAL */;
1452
1453 regs->version = CP_REGS_VER;
1454
1455 spin_lock_irqsave(&cp->lock, flags);
1456 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1457 spin_unlock_irqrestore(&cp->lock, flags);
1458 }
1459
1460 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1461 {
1462 struct cp_private *cp = netdev_priv(dev);
1463 unsigned long flags;
1464
1465 spin_lock_irqsave (&cp->lock, flags);
1466 netdev_get_wol (cp, wol);
1467 spin_unlock_irqrestore (&cp->lock, flags);
1468 }
1469
1470 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1471 {
1472 struct cp_private *cp = netdev_priv(dev);
1473 unsigned long flags;
1474 int rc;
1475
1476 spin_lock_irqsave (&cp->lock, flags);
1477 rc = netdev_set_wol (cp, wol);
1478 spin_unlock_irqrestore (&cp->lock, flags);
1479
1480 return rc;
1481 }
1482
1483 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1484 {
1485 switch (stringset) {
1486 case ETH_SS_STATS:
1487 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1488 break;
1489 default:
1490 BUG();
1491 break;
1492 }
1493 }
1494
1495 static void cp_get_ethtool_stats (struct net_device *dev,
1496 struct ethtool_stats *estats, u64 *tmp_stats)
1497 {
1498 struct cp_private *cp = netdev_priv(dev);
1499 struct cp_dma_stats *nic_stats;
1500 dma_addr_t dma;
1501 int i;
1502
1503 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1504 &dma, GFP_KERNEL);
1505 if (!nic_stats)
1506 return;
1507
1508 /* begin NIC statistics dump */
1509 cpw32(StatsAddr + 4, (u64)dma >> 32);
1510 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1511 cpr32(StatsAddr);
1512
1513 for (i = 0; i < 1000; i++) {
1514 if ((cpr32(StatsAddr) & DumpStats) == 0)
1515 break;
1516 udelay(10);
1517 }
1518 cpw32(StatsAddr, 0);
1519 cpw32(StatsAddr + 4, 0);
1520 cpr32(StatsAddr);
1521
1522 i = 0;
1523 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1524 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1525 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1526 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1527 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1528 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1529 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1530 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1531 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1532 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1533 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1534 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1535 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1536 tmp_stats[i++] = cp->cp_stats.rx_frags;
1537 BUG_ON(i != CP_NUM_STATS);
1538
1539 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1540 }
1541
1542 static const struct ethtool_ops cp_ethtool_ops = {
1543 .get_drvinfo = cp_get_drvinfo,
1544 .get_regs_len = cp_get_regs_len,
1545 .get_sset_count = cp_get_sset_count,
1546 .get_settings = cp_get_settings,
1547 .set_settings = cp_set_settings,
1548 .nway_reset = cp_nway_reset,
1549 .get_link = ethtool_op_get_link,
1550 .get_msglevel = cp_get_msglevel,
1551 .set_msglevel = cp_set_msglevel,
1552 .get_regs = cp_get_regs,
1553 .get_wol = cp_get_wol,
1554 .set_wol = cp_set_wol,
1555 .get_strings = cp_get_strings,
1556 .get_ethtool_stats = cp_get_ethtool_stats,
1557 .get_eeprom_len = cp_get_eeprom_len,
1558 .get_eeprom = cp_get_eeprom,
1559 .set_eeprom = cp_set_eeprom,
1560 };
1561
1562 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1563 {
1564 struct cp_private *cp = netdev_priv(dev);
1565 int rc;
1566 unsigned long flags;
1567
1568 if (!netif_running(dev))
1569 return -EINVAL;
1570
1571 spin_lock_irqsave(&cp->lock, flags);
1572 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1573 spin_unlock_irqrestore(&cp->lock, flags);
1574 return rc;
1575 }
1576
1577 static int cp_set_mac_address(struct net_device *dev, void *p)
1578 {
1579 struct cp_private *cp = netdev_priv(dev);
1580 struct sockaddr *addr = p;
1581
1582 if (!is_valid_ether_addr(addr->sa_data))
1583 return -EADDRNOTAVAIL;
1584
1585 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1586
1587 spin_lock_irq(&cp->lock);
1588
1589 cpw8_f(Cfg9346, Cfg9346_Unlock);
1590 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1591 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1592 cpw8_f(Cfg9346, Cfg9346_Lock);
1593
1594 spin_unlock_irq(&cp->lock);
1595
1596 return 0;
1597 }
1598
1599 /* Serial EEPROM section. */
1600
1601 /* EEPROM_Ctrl bits. */
1602 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1603 #define EE_CS 0x08 /* EEPROM chip select. */
1604 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1605 #define EE_WRITE_0 0x00
1606 #define EE_WRITE_1 0x02
1607 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1608 #define EE_ENB (0x80 | EE_CS)
1609
1610 /* Delay between EEPROM clock transitions.
1611 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1612 */
1613
1614 #define eeprom_delay() readl(ee_addr)
1615
1616 /* The EEPROM commands include the alway-set leading bit. */
1617 #define EE_EXTEND_CMD (4)
1618 #define EE_WRITE_CMD (5)
1619 #define EE_READ_CMD (6)
1620 #define EE_ERASE_CMD (7)
1621
1622 #define EE_EWDS_ADDR (0)
1623 #define EE_WRAL_ADDR (1)
1624 #define EE_ERAL_ADDR (2)
1625 #define EE_EWEN_ADDR (3)
1626
1627 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1628
1629 static void eeprom_cmd_start(void __iomem *ee_addr)
1630 {
1631 writeb (EE_ENB & ~EE_CS, ee_addr);
1632 writeb (EE_ENB, ee_addr);
1633 eeprom_delay ();
1634 }
1635
1636 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1637 {
1638 int i;
1639
1640 /* Shift the command bits out. */
1641 for (i = cmd_len - 1; i >= 0; i--) {
1642 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1643 writeb (EE_ENB | dataval, ee_addr);
1644 eeprom_delay ();
1645 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1646 eeprom_delay ();
1647 }
1648 writeb (EE_ENB, ee_addr);
1649 eeprom_delay ();
1650 }
1651
1652 static void eeprom_cmd_end(void __iomem *ee_addr)
1653 {
1654 writeb (~EE_CS, ee_addr);
1655 eeprom_delay ();
1656 }
1657
1658 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1659 int addr_len)
1660 {
1661 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1662
1663 eeprom_cmd_start(ee_addr);
1664 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1665 eeprom_cmd_end(ee_addr);
1666 }
1667
1668 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1669 {
1670 int i;
1671 u16 retval = 0;
1672 void __iomem *ee_addr = ioaddr + Cfg9346;
1673 int read_cmd = location | (EE_READ_CMD << addr_len);
1674
1675 eeprom_cmd_start(ee_addr);
1676 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1677
1678 for (i = 16; i > 0; i--) {
1679 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1680 eeprom_delay ();
1681 retval =
1682 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1683 0);
1684 writeb (EE_ENB, ee_addr);
1685 eeprom_delay ();
1686 }
1687
1688 eeprom_cmd_end(ee_addr);
1689
1690 return retval;
1691 }
1692
1693 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1694 int addr_len)
1695 {
1696 int i;
1697 void __iomem *ee_addr = ioaddr + Cfg9346;
1698 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1699
1700 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1701
1702 eeprom_cmd_start(ee_addr);
1703 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1704 eeprom_cmd(ee_addr, val, 16);
1705 eeprom_cmd_end(ee_addr);
1706
1707 eeprom_cmd_start(ee_addr);
1708 for (i = 0; i < 20000; i++)
1709 if (readb(ee_addr) & EE_DATA_READ)
1710 break;
1711 eeprom_cmd_end(ee_addr);
1712
1713 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1714 }
1715
1716 static int cp_get_eeprom_len(struct net_device *dev)
1717 {
1718 struct cp_private *cp = netdev_priv(dev);
1719 int size;
1720
1721 spin_lock_irq(&cp->lock);
1722 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1723 spin_unlock_irq(&cp->lock);
1724
1725 return size;
1726 }
1727
1728 static int cp_get_eeprom(struct net_device *dev,
1729 struct ethtool_eeprom *eeprom, u8 *data)
1730 {
1731 struct cp_private *cp = netdev_priv(dev);
1732 unsigned int addr_len;
1733 u16 val;
1734 u32 offset = eeprom->offset >> 1;
1735 u32 len = eeprom->len;
1736 u32 i = 0;
1737
1738 eeprom->magic = CP_EEPROM_MAGIC;
1739
1740 spin_lock_irq(&cp->lock);
1741
1742 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1743
1744 if (eeprom->offset & 1) {
1745 val = read_eeprom(cp->regs, offset, addr_len);
1746 data[i++] = (u8)(val >> 8);
1747 offset++;
1748 }
1749
1750 while (i < len - 1) {
1751 val = read_eeprom(cp->regs, offset, addr_len);
1752 data[i++] = (u8)val;
1753 data[i++] = (u8)(val >> 8);
1754 offset++;
1755 }
1756
1757 if (i < len) {
1758 val = read_eeprom(cp->regs, offset, addr_len);
1759 data[i] = (u8)val;
1760 }
1761
1762 spin_unlock_irq(&cp->lock);
1763 return 0;
1764 }
1765
1766 static int cp_set_eeprom(struct net_device *dev,
1767 struct ethtool_eeprom *eeprom, u8 *data)
1768 {
1769 struct cp_private *cp = netdev_priv(dev);
1770 unsigned int addr_len;
1771 u16 val;
1772 u32 offset = eeprom->offset >> 1;
1773 u32 len = eeprom->len;
1774 u32 i = 0;
1775
1776 if (eeprom->magic != CP_EEPROM_MAGIC)
1777 return -EINVAL;
1778
1779 spin_lock_irq(&cp->lock);
1780
1781 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1782
1783 if (eeprom->offset & 1) {
1784 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1785 val |= (u16)data[i++] << 8;
1786 write_eeprom(cp->regs, offset, val, addr_len);
1787 offset++;
1788 }
1789
1790 while (i < len - 1) {
1791 val = (u16)data[i++];
1792 val |= (u16)data[i++] << 8;
1793 write_eeprom(cp->regs, offset, val, addr_len);
1794 offset++;
1795 }
1796
1797 if (i < len) {
1798 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1799 val |= (u16)data[i];
1800 write_eeprom(cp->regs, offset, val, addr_len);
1801 }
1802
1803 spin_unlock_irq(&cp->lock);
1804 return 0;
1805 }
1806
1807 /* Put the board into D3cold state and wait for WakeUp signal */
1808 static void cp_set_d3_state (struct cp_private *cp)
1809 {
1810 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1811 pci_set_power_state (cp->pdev, PCI_D3hot);
1812 }
1813
1814 static const struct net_device_ops cp_netdev_ops = {
1815 .ndo_open = cp_open,
1816 .ndo_stop = cp_close,
1817 .ndo_validate_addr = eth_validate_addr,
1818 .ndo_set_mac_address = cp_set_mac_address,
1819 .ndo_set_multicast_list = cp_set_rx_mode,
1820 .ndo_get_stats = cp_get_stats,
1821 .ndo_do_ioctl = cp_ioctl,
1822 .ndo_start_xmit = cp_start_xmit,
1823 .ndo_tx_timeout = cp_tx_timeout,
1824 .ndo_set_features = cp_set_features,
1825 #if CP_VLAN_TAG_USED
1826 .ndo_vlan_rx_register = cp_vlan_rx_register,
1827 #endif
1828 #ifdef BROKEN
1829 .ndo_change_mtu = cp_change_mtu,
1830 #endif
1831
1832 #ifdef CONFIG_NET_POLL_CONTROLLER
1833 .ndo_poll_controller = cp_poll_controller,
1834 #endif
1835 };
1836
1837 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1838 {
1839 struct net_device *dev;
1840 struct cp_private *cp;
1841 int rc;
1842 void __iomem *regs;
1843 resource_size_t pciaddr;
1844 unsigned int addr_len, i, pci_using_dac;
1845
1846 #ifndef MODULE
1847 static int version_printed;
1848 if (version_printed++ == 0)
1849 pr_info("%s", version);
1850 #endif
1851
1852 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1853 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1854 dev_info(&pdev->dev,
1855 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1856 pdev->vendor, pdev->device, pdev->revision);
1857 return -ENODEV;
1858 }
1859
1860 dev = alloc_etherdev(sizeof(struct cp_private));
1861 if (!dev)
1862 return -ENOMEM;
1863 SET_NETDEV_DEV(dev, &pdev->dev);
1864
1865 cp = netdev_priv(dev);
1866 cp->pdev = pdev;
1867 cp->dev = dev;
1868 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1869 spin_lock_init (&cp->lock);
1870 cp->mii_if.dev = dev;
1871 cp->mii_if.mdio_read = mdio_read;
1872 cp->mii_if.mdio_write = mdio_write;
1873 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1874 cp->mii_if.phy_id_mask = 0x1f;
1875 cp->mii_if.reg_num_mask = 0x1f;
1876 cp_set_rxbufsize(cp);
1877
1878 rc = pci_enable_device(pdev);
1879 if (rc)
1880 goto err_out_free;
1881
1882 rc = pci_set_mwi(pdev);
1883 if (rc)
1884 goto err_out_disable;
1885
1886 rc = pci_request_regions(pdev, DRV_NAME);
1887 if (rc)
1888 goto err_out_mwi;
1889
1890 pciaddr = pci_resource_start(pdev, 1);
1891 if (!pciaddr) {
1892 rc = -EIO;
1893 dev_err(&pdev->dev, "no MMIO resource\n");
1894 goto err_out_res;
1895 }
1896 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1897 rc = -EIO;
1898 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1899 (unsigned long long)pci_resource_len(pdev, 1));
1900 goto err_out_res;
1901 }
1902
1903 /* Configure DMA attributes. */
1904 if ((sizeof(dma_addr_t) > 4) &&
1905 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1906 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1907 pci_using_dac = 1;
1908 } else {
1909 pci_using_dac = 0;
1910
1911 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1912 if (rc) {
1913 dev_err(&pdev->dev,
1914 "No usable DMA configuration, aborting\n");
1915 goto err_out_res;
1916 }
1917 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1918 if (rc) {
1919 dev_err(&pdev->dev,
1920 "No usable consistent DMA configuration, aborting\n");
1921 goto err_out_res;
1922 }
1923 }
1924
1925 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1926 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1927
1928 dev->features |= NETIF_F_RXCSUM;
1929 dev->hw_features |= NETIF_F_RXCSUM;
1930
1931 regs = ioremap(pciaddr, CP_REGS_SIZE);
1932 if (!regs) {
1933 rc = -EIO;
1934 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1935 (unsigned long long)pci_resource_len(pdev, 1),
1936 (unsigned long long)pciaddr);
1937 goto err_out_res;
1938 }
1939 dev->base_addr = (unsigned long) regs;
1940 cp->regs = regs;
1941
1942 cp_stop_hw(cp);
1943
1944 /* read MAC address from EEPROM */
1945 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1946 for (i = 0; i < 3; i++)
1947 ((__le16 *) (dev->dev_addr))[i] =
1948 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1949 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1950
1951 dev->netdev_ops = &cp_netdev_ops;
1952 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1953 dev->ethtool_ops = &cp_ethtool_ops;
1954 dev->watchdog_timeo = TX_TIMEOUT;
1955
1956 #if CP_VLAN_TAG_USED
1957 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1958 #endif
1959
1960 if (pci_using_dac)
1961 dev->features |= NETIF_F_HIGHDMA;
1962
1963 /* disabled by default until verified */
1964 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
1965
1966 dev->irq = pdev->irq;
1967
1968 rc = register_netdev(dev);
1969 if (rc)
1970 goto err_out_iomap;
1971
1972 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1973 dev->base_addr, dev->dev_addr, dev->irq);
1974
1975 pci_set_drvdata(pdev, dev);
1976
1977 /* enable busmastering and memory-write-invalidate */
1978 pci_set_master(pdev);
1979
1980 if (cp->wol_enabled)
1981 cp_set_d3_state (cp);
1982
1983 return 0;
1984
1985 err_out_iomap:
1986 iounmap(regs);
1987 err_out_res:
1988 pci_release_regions(pdev);
1989 err_out_mwi:
1990 pci_clear_mwi(pdev);
1991 err_out_disable:
1992 pci_disable_device(pdev);
1993 err_out_free:
1994 free_netdev(dev);
1995 return rc;
1996 }
1997
1998 static void cp_remove_one (struct pci_dev *pdev)
1999 {
2000 struct net_device *dev = pci_get_drvdata(pdev);
2001 struct cp_private *cp = netdev_priv(dev);
2002
2003 unregister_netdev(dev);
2004 iounmap(cp->regs);
2005 if (cp->wol_enabled)
2006 pci_set_power_state (pdev, PCI_D0);
2007 pci_release_regions(pdev);
2008 pci_clear_mwi(pdev);
2009 pci_disable_device(pdev);
2010 pci_set_drvdata(pdev, NULL);
2011 free_netdev(dev);
2012 }
2013
2014 #ifdef CONFIG_PM
2015 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2016 {
2017 struct net_device *dev = pci_get_drvdata(pdev);
2018 struct cp_private *cp = netdev_priv(dev);
2019 unsigned long flags;
2020
2021 if (!netif_running(dev))
2022 return 0;
2023
2024 netif_device_detach (dev);
2025 netif_stop_queue (dev);
2026
2027 spin_lock_irqsave (&cp->lock, flags);
2028
2029 /* Disable Rx and Tx */
2030 cpw16 (IntrMask, 0);
2031 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2032
2033 spin_unlock_irqrestore (&cp->lock, flags);
2034
2035 pci_save_state(pdev);
2036 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2037 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2038
2039 return 0;
2040 }
2041
2042 static int cp_resume (struct pci_dev *pdev)
2043 {
2044 struct net_device *dev = pci_get_drvdata (pdev);
2045 struct cp_private *cp = netdev_priv(dev);
2046 unsigned long flags;
2047
2048 if (!netif_running(dev))
2049 return 0;
2050
2051 netif_device_attach (dev);
2052
2053 pci_set_power_state(pdev, PCI_D0);
2054 pci_restore_state(pdev);
2055 pci_enable_wake(pdev, PCI_D0, 0);
2056
2057 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2058 cp_init_rings_index (cp);
2059 cp_init_hw (cp);
2060 cp_enable_irq(cp);
2061 netif_start_queue (dev);
2062
2063 spin_lock_irqsave (&cp->lock, flags);
2064
2065 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2066
2067 spin_unlock_irqrestore (&cp->lock, flags);
2068
2069 return 0;
2070 }
2071 #endif /* CONFIG_PM */
2072
2073 static struct pci_driver cp_driver = {
2074 .name = DRV_NAME,
2075 .id_table = cp_pci_tbl,
2076 .probe = cp_init_one,
2077 .remove = cp_remove_one,
2078 #ifdef CONFIG_PM
2079 .resume = cp_resume,
2080 .suspend = cp_suspend,
2081 #endif
2082 };
2083
2084 static int __init cp_init (void)
2085 {
2086 #ifdef MODULE
2087 pr_info("%s", version);
2088 #endif
2089 return pci_register_driver(&cp_driver);
2090 }
2091
2092 static void __exit cp_exit (void)
2093 {
2094 pci_unregister_driver (&cp_driver);
2095 }
2096
2097 module_init(cp_init);
2098 module_exit(cp_exit);
Linux with added FPC-III support