ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / net / arm / am79c961a.h
blobfd634d32756bddcfcbe7b1d79f1b1b3105d32162
1 /*
2 * linux/drivers/net/arm/am79c961a.h
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
9 #ifndef _LINUX_am79c961a_H
10 #define _LINUX_am79c961a_H
12 /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
13 #define DEBUG_TX 2
14 #define DEBUG_RX 4
15 #define DEBUG_INT 8
16 #define DEBUG_IC 16
17 #ifndef NET_DEBUG
18 #define NET_DEBUG 0
19 #endif
21 #define NET_UID 0
22 #define NET_RDP 0x10
23 #define NET_RAP 0x12
24 #define NET_RESET 0x14
25 #define NET_IDP 0x16
28 * RAP registers
30 #define CSR0 0
31 #define CSR0_INIT 0x0001
32 #define CSR0_STRT 0x0002
33 #define CSR0_STOP 0x0004
34 #define CSR0_TDMD 0x0008
35 #define CSR0_TXON 0x0010
36 #define CSR0_RXON 0x0020
37 #define CSR0_IENA 0x0040
38 #define CSR0_INTR 0x0080
39 #define CSR0_IDON 0x0100
40 #define CSR0_TINT 0x0200
41 #define CSR0_RINT 0x0400
42 #define CSR0_MERR 0x0800
43 #define CSR0_MISS 0x1000
44 #define CSR0_CERR 0x2000
45 #define CSR0_BABL 0x4000
46 #define CSR0_ERR 0x8000
48 #define CSR3 3
49 #define CSR3_EMBA 0x0008
50 #define CSR3_DXMT2PD 0x0010
51 #define CSR3_LAPPEN 0x0020
52 #define CSR3_DXSUFLO 0x0040
53 #define CSR3_IDONM 0x0100
54 #define CSR3_TINTM 0x0200
55 #define CSR3_RINTM 0x0400
56 #define CSR3_MERRM 0x0800
57 #define CSR3_MISSM 0x1000
58 #define CSR3_BABLM 0x4000
59 #define CSR3_MASKALL 0x5F00
61 #define CSR4 4
62 #define CSR4_JABM 0x0001
63 #define CSR4_JAB 0x0002
64 #define CSR4_TXSTRTM 0x0004
65 #define CSR4_TXSTRT 0x0008
66 #define CSR4_RCVCCOM 0x0010
67 #define CSR4_RCVCCO 0x0020
68 #define CSR4_MFCOM 0x0100
69 #define CSR4_MFCO 0x0200
70 #define CSR4_ASTRP_RCV 0x0400
71 #define CSR4_APAD_XMIT 0x0800
73 #define CTRL1 5
74 #define CTRL1_SPND 0x0001
76 #define LADRL 8
77 #define LADRM1 9
78 #define LADRM2 10
79 #define LADRH 11
80 #define PADRL 12
81 #define PADRM 13
82 #define PADRH 14
84 #define MODE 15
85 #define MODE_DISRX 0x0001
86 #define MODE_DISTX 0x0002
87 #define MODE_LOOP 0x0004
88 #define MODE_DTCRC 0x0008
89 #define MODE_COLL 0x0010
90 #define MODE_DRETRY 0x0020
91 #define MODE_INTLOOP 0x0040
92 #define MODE_PORT_AUI 0x0000
93 #define MODE_PORT_10BT 0x0080
94 #define MODE_DRXPA 0x2000
95 #define MODE_DRXBA 0x4000
96 #define MODE_PROMISC 0x8000
98 #define BASERXL 24
99 #define BASERXH 25
100 #define BASETXL 30
101 #define BASETXH 31
103 #define POLLINT 47
105 #define SIZERXR 76
106 #define SIZETXR 78
108 #define CSR_MFC 112
110 #define RMD_ENP 0x0100
111 #define RMD_STP 0x0200
112 #define RMD_CRC 0x0800
113 #define RMD_FRAM 0x2000
114 #define RMD_ERR 0x4000
115 #define RMD_OWN 0x8000
117 #define TMD_ENP 0x0100
118 #define TMD_STP 0x0200
119 #define TMD_MORE 0x1000
120 #define TMD_ERR 0x4000
121 #define TMD_OWN 0x8000
123 #define TST_RTRY 0x0400
124 #define TST_LCAR 0x0800
125 #define TST_LCOL 0x1000
126 #define TST_UFLO 0x4000
127 #define TST_BUFF 0x8000
129 #define ISALED0 0x0004
130 #define ISALED0_LNKST 0x8000
132 struct dev_priv {
133 unsigned long rxbuffer[RX_BUFFERS];
134 unsigned long txbuffer[TX_BUFFERS];
135 unsigned char txhead;
136 unsigned char txtail;
137 unsigned char rxhead;
138 unsigned char rxtail;
139 unsigned long rxhdr;
140 unsigned long txhdr;
141 spinlock_t chip_lock;
142 struct timer_list timer;
145 #endif