ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / net / benet / be_hw.h
blob53d658afea2af48a958c0357f6ad51e0a5c7dbde
1 /*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
18 /********* Mailbox door bell *************/
19 /* Used for driver communication with the FW.
20 * The software must write this register twice to post any command. First,
21 * it writes the register with hi=1 and the upper bits of the physical address
22 * for the MAILBOX structure. Software must poll the ready bit until this
23 * is acknowledged. Then, sotware writes the register with hi=0 with the lower
24 * bits in the address. It must poll the ready bit until the command is
25 * complete. Upon completion, the MAILBOX will contain a valid completion
26 * queue entry.
28 #define MPU_MAILBOX_DB_OFFSET 0x160
29 #define MPU_MAILBOX_DB_RDY_MASK 0x1 /* bit 0 */
30 #define MPU_MAILBOX_DB_HI_MASK 0x2 /* bit 1 */
32 #define MPU_EP_CONTROL 0
34 /********** MPU semphore ******************/
35 #define MPU_EP_SEMAPHORE_OFFSET 0xac
36 #define MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET 0x400
37 #define EP_SEMAPHORE_POST_STAGE_MASK 0x0000FFFF
38 #define EP_SEMAPHORE_POST_ERR_MASK 0x1
39 #define EP_SEMAPHORE_POST_ERR_SHIFT 31
41 /* MPU semphore POST stage values */
42 #define POST_STAGE_AWAITING_HOST_RDY 0x1 /* FW awaiting goahead from host */
43 #define POST_STAGE_HOST_RDY 0x2 /* Host has given go-ahed to FW */
44 #define POST_STAGE_BE_RESET 0x3 /* Host wants to reset chip */
45 #define POST_STAGE_ARMFW_RDY 0xc000 /* FW is done with POST */
48 /* Lancer SLIPORT_CONTROL SLIPORT_STATUS registers */
49 #define SLIPORT_STATUS_OFFSET 0x404
50 #define SLIPORT_CONTROL_OFFSET 0x408
52 #define SLIPORT_STATUS_ERR_MASK 0x80000000
53 #define SLIPORT_STATUS_RN_MASK 0x01000000
54 #define SLIPORT_STATUS_RDY_MASK 0x00800000
57 #define SLI_PORT_CONTROL_IP_MASK 0x08000000
59 /********* Memory BAR register ************/
60 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
61 /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
62 * Disable" may still globally block interrupts in addition to individual
63 * interrupt masks; a mechanism for the device driver to block all interrupts
64 * atomically without having to arbitrate for the PCI Interrupt Disable bit
65 * with the OS.
67 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
69 /********* Power management (WOL) **********/
70 #define PCICFG_PM_CONTROL_OFFSET 0x44
71 #define PCICFG_PM_CONTROL_MASK 0x108 /* bits 3 & 8 */
73 /********* Online Control Registers *******/
74 #define PCICFG_ONLINE0 0xB0
75 #define PCICFG_ONLINE1 0xB4
77 /********* UE Status and Mask Registers ***/
78 #define PCICFG_UE_STATUS_LOW 0xA0
79 #define PCICFG_UE_STATUS_HIGH 0xA4
80 #define PCICFG_UE_STATUS_LOW_MASK 0xA8
81 #define PCICFG_UE_STATUS_HI_MASK 0xAC
83 /******** SLI_INTF ***********************/
84 #define SLI_INTF_REG_OFFSET 0x58
85 #define SLI_INTF_VALID_MASK 0xE0000000
86 #define SLI_INTF_VALID 0xC0000000
87 #define SLI_INTF_HINT2_MASK 0x1F000000
88 #define SLI_INTF_HINT2_SHIFT 24
89 #define SLI_INTF_HINT1_MASK 0x00FF0000
90 #define SLI_INTF_HINT1_SHIFT 16
91 #define SLI_INTF_FAMILY_MASK 0x00000F00
92 #define SLI_INTF_FAMILY_SHIFT 8
93 #define SLI_INTF_IF_TYPE_MASK 0x0000F000
94 #define SLI_INTF_IF_TYPE_SHIFT 12
95 #define SLI_INTF_REV_MASK 0x000000F0
96 #define SLI_INTF_REV_SHIFT 4
97 #define SLI_INTF_FT_MASK 0x00000001
100 /* SLI family */
101 #define BE_SLI_FAMILY 0x0
102 #define LANCER_A0_SLI_FAMILY 0xA
105 /********* ISR0 Register offset **********/
106 #define CEV_ISR0_OFFSET 0xC18
107 #define CEV_ISR_SIZE 4
109 /********* Event Q door bell *************/
110 #define DB_EQ_OFFSET DB_CQ_OFFSET
111 #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
112 #define DB_EQ_RING_ID_EXT_MASK 0x3e00 /* bits 9-13 */
113 #define DB_EQ_RING_ID_EXT_MASK_SHIFT (2) /* qid bits 9-13 placing at 11-15 */
115 /* Clear the interrupt for this eq */
116 #define DB_EQ_CLR_SHIFT (9) /* bit 9 */
117 /* Must be 1 */
118 #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
119 /* Number of event entries processed */
120 #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
121 /* Rearm bit */
122 #define DB_EQ_REARM_SHIFT (29) /* bit 29 */
124 /********* Compl Q door bell *************/
125 #define DB_CQ_OFFSET 0x120
126 #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
127 #define DB_CQ_RING_ID_EXT_MASK 0x7C00 /* bits 10-14 */
128 #define DB_CQ_RING_ID_EXT_MASK_SHIFT (1) /* qid bits 10-14
129 placing at 11-15 */
131 /* Number of event entries processed */
132 #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
133 /* Rearm bit */
134 #define DB_CQ_REARM_SHIFT (29) /* bit 29 */
136 /********** TX ULP door bell *************/
137 #define DB_TXULP1_OFFSET 0x60
138 #define DB_TXULP_RING_ID_MASK 0x7FF /* bits 0 - 10 */
139 /* Number of tx entries posted */
140 #define DB_TXULP_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
141 #define DB_TXULP_NUM_POSTED_MASK 0x3FFF /* bits 16 - 29 */
143 /********** RQ(erx) door bell ************/
144 #define DB_RQ_OFFSET 0x100
145 #define DB_RQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
146 /* Number of rx frags posted */
147 #define DB_RQ_NUM_POSTED_SHIFT (24) /* bits 24 - 31 */
149 /********** MCC door bell ************/
150 #define DB_MCCQ_OFFSET 0x140
151 #define DB_MCCQ_RING_ID_MASK 0x7FF /* bits 0 - 10 */
152 /* Number of entries posted */
153 #define DB_MCCQ_NUM_POSTED_SHIFT (16) /* bits 16 - 29 */
155 /********** SRIOV VF PCICFG OFFSET ********/
156 #define SRIOV_VF_PCICFG_OFFSET (4096)
158 /********** FAT TABLE ********/
159 #define RETRIEVE_FAT 0
160 #define QUERY_FAT 1
162 /* Flashrom related descriptors */
163 #define IMAGE_TYPE_FIRMWARE 160
164 #define IMAGE_TYPE_BOOTCODE 224
165 #define IMAGE_TYPE_OPTIONROM 32
167 #define NUM_FLASHDIR_ENTRIES 32
169 #define IMG_TYPE_ISCSI_ACTIVE 0
170 #define IMG_TYPE_REDBOOT 1
171 #define IMG_TYPE_BIOS 2
172 #define IMG_TYPE_PXE_BIOS 3
173 #define IMG_TYPE_FCOE_BIOS 8
174 #define IMG_TYPE_ISCSI_BACKUP 9
175 #define IMG_TYPE_FCOE_FW_ACTIVE 10
176 #define IMG_TYPE_FCOE_FW_BACKUP 11
177 #define IMG_TYPE_NCSI_FW 13
179 #define FLASHROM_OPER_FLASH 1
180 #define FLASHROM_OPER_SAVE 2
181 #define FLASHROM_OPER_REPORT 4
183 #define FLASH_IMAGE_MAX_SIZE_g2 (1310720) /* Max firmware image sz */
184 #define FLASH_BIOS_IMAGE_MAX_SIZE_g2 (262144) /* Max OPTION ROM img sz */
185 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g2 (262144) /* Max Redboot image sz */
186 #define FLASH_IMAGE_MAX_SIZE_g3 (2097152) /* Max fw image size */
187 #define FLASH_BIOS_IMAGE_MAX_SIZE_g3 (524288) /* Max OPTION ROM img sz */
188 #define FLASH_REDBOOT_IMAGE_MAX_SIZE_g3 (1048576) /* Max Redboot image sz */
189 #define FLASH_NCSI_IMAGE_MAX_SIZE_g3 (262144) /* Max NSCI image sz */
191 #define FLASH_NCSI_MAGIC (0x16032009)
192 #define FLASH_NCSI_DISABLED (0)
193 #define FLASH_NCSI_ENABLED (1)
195 #define FLASH_NCSI_BITFILE_HDR_OFFSET (0x600000)
197 /* Offsets for components on Flash. */
198 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g2 (1048576)
199 #define FLASH_iSCSI_BACKUP_IMAGE_START_g2 (2359296)
200 #define FLASH_FCoE_PRIMARY_IMAGE_START_g2 (3670016)
201 #define FLASH_FCoE_BACKUP_IMAGE_START_g2 (4980736)
202 #define FLASH_iSCSI_BIOS_START_g2 (7340032)
203 #define FLASH_PXE_BIOS_START_g2 (7864320)
204 #define FLASH_FCoE_BIOS_START_g2 (524288)
205 #define FLASH_REDBOOT_START_g2 (0)
207 #define FLASH_NCSI_START_g3 (15990784)
208 #define FLASH_iSCSI_PRIMARY_IMAGE_START_g3 (2097152)
209 #define FLASH_iSCSI_BACKUP_IMAGE_START_g3 (4194304)
210 #define FLASH_FCoE_PRIMARY_IMAGE_START_g3 (6291456)
211 #define FLASH_FCoE_BACKUP_IMAGE_START_g3 (8388608)
212 #define FLASH_iSCSI_BIOS_START_g3 (12582912)
213 #define FLASH_PXE_BIOS_START_g3 (13107200)
214 #define FLASH_FCoE_BIOS_START_g3 (13631488)
215 #define FLASH_REDBOOT_START_g3 (262144)
217 /************* Rx Packet Type Encoding **************/
218 #define BE_UNICAST_PACKET 0
219 #define BE_MULTICAST_PACKET 1
220 #define BE_BROADCAST_PACKET 2
221 #define BE_RSVD_PACKET 3
224 * BE descriptors: host memory data structures whose formats
225 * are hardwired in BE silicon.
227 /* Event Queue Descriptor */
228 #define EQ_ENTRY_VALID_MASK 0x1 /* bit 0 */
229 #define EQ_ENTRY_RES_ID_MASK 0xFFFF /* bits 16 - 31 */
230 #define EQ_ENTRY_RES_ID_SHIFT 16
232 struct be_eq_entry {
233 u32 evt;
236 /* TX Queue Descriptor */
237 #define ETH_WRB_FRAG_LEN_MASK 0xFFFF
238 struct be_eth_wrb {
239 u32 frag_pa_hi; /* dword 0 */
240 u32 frag_pa_lo; /* dword 1 */
241 u32 rsvd0; /* dword 2 */
242 u32 frag_len; /* dword 3: bits 0 - 15 */
243 } __packed;
245 /* Pseudo amap definition for eth_hdr_wrb in which each bit of the
246 * actual structure is defined as a byte : used to calculate
247 * offset/shift/mask of each field */
248 struct amap_eth_hdr_wrb {
249 u8 rsvd0[32]; /* dword 0 */
250 u8 rsvd1[32]; /* dword 1 */
251 u8 complete; /* dword 2 */
252 u8 event;
253 u8 crc;
254 u8 forward;
255 u8 lso6;
256 u8 mgmt;
257 u8 ipcs;
258 u8 udpcs;
259 u8 tcpcs;
260 u8 lso;
261 u8 vlan;
262 u8 gso[2];
263 u8 num_wrb[5];
264 u8 lso_mss[14];
265 u8 len[16]; /* dword 3 */
266 u8 vlan_tag[16];
267 } __packed;
269 struct be_eth_hdr_wrb {
270 u32 dw[4];
273 /* TX Compl Queue Descriptor */
275 /* Pseudo amap definition for eth_tx_compl in which each bit of the
276 * actual structure is defined as a byte: used to calculate
277 * offset/shift/mask of each field */
278 struct amap_eth_tx_compl {
279 u8 wrb_index[16]; /* dword 0 */
280 u8 ct[2]; /* dword 0 */
281 u8 port[2]; /* dword 0 */
282 u8 rsvd0[8]; /* dword 0 */
283 u8 status[4]; /* dword 0 */
284 u8 user_bytes[16]; /* dword 1 */
285 u8 nwh_bytes[8]; /* dword 1 */
286 u8 lso; /* dword 1 */
287 u8 cast_enc[2]; /* dword 1 */
288 u8 rsvd1[5]; /* dword 1 */
289 u8 rsvd2[32]; /* dword 2 */
290 u8 pkts[16]; /* dword 3 */
291 u8 ringid[11]; /* dword 3 */
292 u8 hash_val[4]; /* dword 3 */
293 u8 valid; /* dword 3 */
294 } __packed;
296 struct be_eth_tx_compl {
297 u32 dw[4];
300 /* RX Queue Descriptor */
301 struct be_eth_rx_d {
302 u32 fragpa_hi;
303 u32 fragpa_lo;
306 /* RX Compl Queue Descriptor */
308 /* Pseudo amap definition for BE2 and BE3 legacy mode eth_rx_compl in which
309 * each bit of the actual structure is defined as a byte: used to calculate
310 * offset/shift/mask of each field */
311 struct amap_eth_rx_compl_v0 {
312 u8 vlan_tag[16]; /* dword 0 */
313 u8 pktsize[14]; /* dword 0 */
314 u8 port; /* dword 0 */
315 u8 ip_opt; /* dword 0 */
316 u8 err; /* dword 1 */
317 u8 rsshp; /* dword 1 */
318 u8 ipf; /* dword 1 */
319 u8 tcpf; /* dword 1 */
320 u8 udpf; /* dword 1 */
321 u8 ipcksm; /* dword 1 */
322 u8 l4_cksm; /* dword 1 */
323 u8 ip_version; /* dword 1 */
324 u8 macdst[6]; /* dword 1 */
325 u8 vtp; /* dword 1 */
326 u8 rsvd0; /* dword 1 */
327 u8 fragndx[10]; /* dword 1 */
328 u8 ct[2]; /* dword 1 */
329 u8 sw; /* dword 1 */
330 u8 numfrags[3]; /* dword 1 */
331 u8 rss_flush; /* dword 2 */
332 u8 cast_enc[2]; /* dword 2 */
333 u8 vtm; /* dword 2 */
334 u8 rss_bank; /* dword 2 */
335 u8 rsvd1[23]; /* dword 2 */
336 u8 lro_pkt; /* dword 2 */
337 u8 rsvd2[2]; /* dword 2 */
338 u8 valid; /* dword 2 */
339 u8 rsshash[32]; /* dword 3 */
340 } __packed;
342 /* Pseudo amap definition for BE3 native mode eth_rx_compl in which
343 * each bit of the actual structure is defined as a byte: used to calculate
344 * offset/shift/mask of each field */
345 struct amap_eth_rx_compl_v1 {
346 u8 vlan_tag[16]; /* dword 0 */
347 u8 pktsize[14]; /* dword 0 */
348 u8 vtp; /* dword 0 */
349 u8 ip_opt; /* dword 0 */
350 u8 err; /* dword 1 */
351 u8 rsshp; /* dword 1 */
352 u8 ipf; /* dword 1 */
353 u8 tcpf; /* dword 1 */
354 u8 udpf; /* dword 1 */
355 u8 ipcksm; /* dword 1 */
356 u8 l4_cksm; /* dword 1 */
357 u8 ip_version; /* dword 1 */
358 u8 macdst[7]; /* dword 1 */
359 u8 rsvd0; /* dword 1 */
360 u8 fragndx[10]; /* dword 1 */
361 u8 ct[2]; /* dword 1 */
362 u8 sw; /* dword 1 */
363 u8 numfrags[3]; /* dword 1 */
364 u8 rss_flush; /* dword 2 */
365 u8 cast_enc[2]; /* dword 2 */
366 u8 vtm; /* dword 2 */
367 u8 rss_bank; /* dword 2 */
368 u8 port[2]; /* dword 2 */
369 u8 vntagp; /* dword 2 */
370 u8 header_len[8]; /* dword 2 */
371 u8 header_split[2]; /* dword 2 */
372 u8 rsvd1[13]; /* dword 2 */
373 u8 valid; /* dword 2 */
374 u8 rsshash[32]; /* dword 3 */
375 } __packed;
377 struct be_eth_rx_compl {
378 u32 dw[4];
381 struct mgmt_hba_attribs {
382 u8 flashrom_version_string[32];
383 u8 manufacturer_name[32];
384 u32 supported_modes;
385 u32 rsvd0[3];
386 u8 ncsi_ver_string[12];
387 u32 default_extended_timeout;
388 u8 controller_model_number[32];
389 u8 controller_description[64];
390 u8 controller_serial_number[32];
391 u8 ip_version_string[32];
392 u8 firmware_version_string[32];
393 u8 bios_version_string[32];
394 u8 redboot_version_string[32];
395 u8 driver_version_string[32];
396 u8 fw_on_flash_version_string[32];
397 u32 functionalities_supported;
398 u16 max_cdblength;
399 u8 asic_revision;
400 u8 generational_guid[16];
401 u8 hba_port_count;
402 u16 default_link_down_timeout;
403 u8 iscsi_ver_min_max;
404 u8 multifunction_device;
405 u8 cache_valid;
406 u8 hba_status;
407 u8 max_domains_supported;
408 u8 phy_port;
409 u32 firmware_post_status;
410 u32 hba_mtu[8];
411 u32 rsvd1[4];
414 struct mgmt_controller_attrib {
415 struct mgmt_hba_attribs hba_attribs;
416 u16 pci_vendor_id;
417 u16 pci_device_id;
418 u16 pci_sub_vendor_id;
419 u16 pci_sub_system_id;
420 u8 pci_bus_number;
421 u8 pci_device_number;
422 u8 pci_function_number;
423 u8 interface_type;
424 u64 unique_identifier;
425 u32 rsvd0[5];
428 struct controller_id {
429 u32 vendor;
430 u32 device;
431 u32 subvendor;
432 u32 subdevice;
435 struct flash_comp {
436 unsigned long offset;
437 int optype;
438 int size;
441 struct image_hdr {
442 u32 imageid;
443 u32 imageoffset;
444 u32 imagelength;
445 u32 image_checksum;
446 u8 image_version[32];
448 struct flash_file_hdr_g2 {
449 u8 sign[32];
450 u32 cksum;
451 u32 antidote;
452 struct controller_id cont_id;
453 u32 file_len;
454 u32 chunk_num;
455 u32 total_chunks;
456 u32 num_imgs;
457 u8 build[24];
460 struct flash_file_hdr_g3 {
461 u8 sign[52];
462 u8 ufi_version[4];
463 u32 file_len;
464 u32 cksum;
465 u32 antidote;
466 u32 num_imgs;
467 u8 build[24];
468 u8 rsvd[32];
471 struct flash_section_hdr {
472 u32 format_rev;
473 u32 cksum;
474 u32 antidote;
475 u32 build_no;
476 u8 id_string[64];
477 u32 active_entry_mask;
478 u32 valid_entry_mask;
479 u32 org_content_mask;
480 u32 rsvd0;
481 u32 rsvd1;
482 u32 rsvd2;
483 u32 rsvd3;
484 u32 rsvd4;
487 struct flash_section_entry {
488 u32 type;
489 u32 offset;
490 u32 pad_size;
491 u32 image_size;
492 u32 cksum;
493 u32 entry_point;
494 u32 rsvd0;
495 u32 rsvd1;
496 u8 ver_data[32];
499 struct flash_section_info {
500 u8 cookie[32];
501 struct flash_section_hdr fsec_hdr;
502 struct flash_section_entry fsec_entry[32];