ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / net / enic / cq_enet_desc.h
blobc2c0680a1146793c2bf4393dbd746835f6395aa9
1 /*
2 * Copyright 2008-2010 Cisco Systems, Inc. All rights reserved.
3 * Copyright 2007 Nuova Systems, Inc. All rights reserved.
5 * This program is free software; you may redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
16 * SOFTWARE.
20 #ifndef _CQ_ENET_DESC_H_
21 #define _CQ_ENET_DESC_H_
23 #include "cq_desc.h"
25 /* Ethernet completion queue descriptor: 16B */
26 struct cq_enet_wq_desc {
27 __le16 completed_index;
28 __le16 q_number;
29 u8 reserved[11];
30 u8 type_color;
33 static inline void cq_enet_wq_desc_dec(struct cq_enet_wq_desc *desc,
34 u8 *type, u8 *color, u16 *q_number, u16 *completed_index)
36 cq_desc_dec((struct cq_desc *)desc, type,
37 color, q_number, completed_index);
40 /* Completion queue descriptor: Ethernet receive queue, 16B */
41 struct cq_enet_rq_desc {
42 __le16 completed_index_flags;
43 __le16 q_number_rss_type_flags;
44 __le32 rss_hash;
45 __le16 bytes_written_flags;
46 __le16 vlan;
47 __le16 checksum_fcoe;
48 u8 flags;
49 u8 type_color;
52 #define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT (0x1 << 12)
53 #define CQ_ENET_RQ_DESC_FLAGS_FCOE (0x1 << 13)
54 #define CQ_ENET_RQ_DESC_FLAGS_EOP (0x1 << 14)
55 #define CQ_ENET_RQ_DESC_FLAGS_SOP (0x1 << 15)
57 #define CQ_ENET_RQ_DESC_RSS_TYPE_BITS 4
58 #define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \
59 ((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1)
60 #define CQ_ENET_RQ_DESC_RSS_TYPE_NONE 0
61 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4 1
62 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4 2
63 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6 3
64 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6 4
65 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX 5
66 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX 6
68 #define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC (0x1 << 14)
70 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS 14
71 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \
72 ((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)
73 #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED (0x1 << 14)
74 #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED (0x1 << 15)
76 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS 12
77 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_MASK \
78 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS) - 1)
79 #define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK (0x1 << 12)
80 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS 3
81 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_MASK \
82 ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS) - 1)
83 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_SHIFT 13
85 #define CQ_ENET_RQ_DESC_FCOE_SOF_BITS 8
86 #define CQ_ENET_RQ_DESC_FCOE_SOF_MASK \
87 ((1 << CQ_ENET_RQ_DESC_FCOE_SOF_BITS) - 1)
88 #define CQ_ENET_RQ_DESC_FCOE_EOF_BITS 8
89 #define CQ_ENET_RQ_DESC_FCOE_EOF_MASK \
90 ((1 << CQ_ENET_RQ_DESC_FCOE_EOF_BITS) - 1)
91 #define CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT 8
93 #define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK (0x1 << 0)
94 #define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK (0x1 << 0)
95 #define CQ_ENET_RQ_DESC_FLAGS_UDP (0x1 << 1)
96 #define CQ_ENET_RQ_DESC_FCOE_ENC_ERROR (0x1 << 1)
97 #define CQ_ENET_RQ_DESC_FLAGS_TCP (0x1 << 2)
98 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK (0x1 << 3)
99 #define CQ_ENET_RQ_DESC_FLAGS_IPV6 (0x1 << 4)
100 #define CQ_ENET_RQ_DESC_FLAGS_IPV4 (0x1 << 5)
101 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT (0x1 << 6)
102 #define CQ_ENET_RQ_DESC_FLAGS_FCS_OK (0x1 << 7)
104 static inline void cq_enet_rq_desc_dec(struct cq_enet_rq_desc *desc,
105 u8 *type, u8 *color, u16 *q_number, u16 *completed_index,
106 u8 *ingress_port, u8 *fcoe, u8 *eop, u8 *sop, u8 *rss_type,
107 u8 *csum_not_calc, u32 *rss_hash, u16 *bytes_written, u8 *packet_error,
108 u8 *vlan_stripped, u16 *vlan_tci, u16 *checksum, u8 *fcoe_sof,
109 u8 *fcoe_fc_crc_ok, u8 *fcoe_enc_error, u8 *fcoe_eof,
110 u8 *tcp_udp_csum_ok, u8 *udp, u8 *tcp, u8 *ipv4_csum_ok,
111 u8 *ipv6, u8 *ipv4, u8 *ipv4_fragment, u8 *fcs_ok)
113 u16 completed_index_flags;
114 u16 q_number_rss_type_flags;
115 u16 bytes_written_flags;
117 cq_desc_dec((struct cq_desc *)desc, type,
118 color, q_number, completed_index);
120 completed_index_flags = le16_to_cpu(desc->completed_index_flags);
121 q_number_rss_type_flags =
122 le16_to_cpu(desc->q_number_rss_type_flags);
123 bytes_written_flags = le16_to_cpu(desc->bytes_written_flags);
125 *ingress_port = (completed_index_flags &
126 CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT) ? 1 : 0;
127 *fcoe = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_FCOE) ?
128 1 : 0;
129 *eop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_EOP) ?
130 1 : 0;
131 *sop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_SOP) ?
132 1 : 0;
134 *rss_type = (u8)((q_number_rss_type_flags >> CQ_DESC_Q_NUM_BITS) &
135 CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
136 *csum_not_calc = (q_number_rss_type_flags &
137 CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ? 1 : 0;
139 *rss_hash = le32_to_cpu(desc->rss_hash);
141 *bytes_written = bytes_written_flags &
142 CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
143 *packet_error = (bytes_written_flags &
144 CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ? 1 : 0;
145 *vlan_stripped = (bytes_written_flags &
146 CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) ? 1 : 0;
149 * Tag Control Information(16) = user_priority(3) + cfi(1) + vlan(12)
151 *vlan_tci = le16_to_cpu(desc->vlan);
153 if (*fcoe) {
154 *fcoe_sof = (u8)(le16_to_cpu(desc->checksum_fcoe) &
155 CQ_ENET_RQ_DESC_FCOE_SOF_MASK);
156 *fcoe_fc_crc_ok = (desc->flags &
157 CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK) ? 1 : 0;
158 *fcoe_enc_error = (desc->flags &
159 CQ_ENET_RQ_DESC_FCOE_ENC_ERROR) ? 1 : 0;
160 *fcoe_eof = (u8)((desc->checksum_fcoe >>
161 CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT) &
162 CQ_ENET_RQ_DESC_FCOE_EOF_MASK);
163 *checksum = 0;
164 } else {
165 *fcoe_sof = 0;
166 *fcoe_fc_crc_ok = 0;
167 *fcoe_enc_error = 0;
168 *fcoe_eof = 0;
169 *checksum = le16_to_cpu(desc->checksum_fcoe);
172 *tcp_udp_csum_ok =
173 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ? 1 : 0;
174 *udp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_UDP) ? 1 : 0;
175 *tcp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP) ? 1 : 0;
176 *ipv4_csum_ok =
177 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ? 1 : 0;
178 *ipv6 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV6) ? 1 : 0;
179 *ipv4 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4) ? 1 : 0;
180 *ipv4_fragment =
181 (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT) ? 1 : 0;
182 *fcs_ok = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_FCS_OK) ? 1 : 0;
185 #endif /* _CQ_ENET_DESC_H_ */