2 * drivers/net/ibm_newemac/emac.h
4 * Register definitions for PowerPC 4xx on-chip ethernet contoller
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
9 * Based on the arch/ppc version of the driver:
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
14 * Based on original work by
15 * Matt Porter <mporter@kernel.crashing.org>
16 * Armin Kuster <akuster@mvista.com>
17 * Copyright 2002-2004 MontaVista Software Inc.
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
25 #ifndef __IBM_NEWEMAC_H
26 #define __IBM_NEWEMAC_H
28 #include <linux/types.h>
30 /* EMAC registers Write Access rules */
32 /* Common registers across all EMAC implementations. */
33 u32 mr0
; /* Special */
35 u32 tmr0
; /* Special */
36 u32 tmr1
; /* Special */
40 u32 iahr
; /* Reset, R, T */
41 u32 ialr
; /* Reset, R, T */
42 u32 vtpid
; /* Reset, R, T */
43 u32 vtci
; /* Reset, R, T */
44 u32 ptr
; /* Reset, T */
46 /* Registers unique to EMAC4 implementations */
48 u32 iaht1
; /* Reset, R */
49 u32 iaht2
; /* Reset, R */
50 u32 iaht3
; /* Reset, R */
51 u32 iaht4
; /* Reset, R */
52 u32 gaht1
; /* Reset, R */
53 u32 gaht2
; /* Reset, R */
54 u32 gaht3
; /* Reset, R */
55 u32 gaht4
; /* Reset, R */
57 /* Registers unique to EMAC4SYNC implementations */
59 u32 mahr
; /* Reset, R, T */
60 u32 malr
; /* Reset, R, T */
61 u32 mmahr
; /* Reset, R, T */
62 u32 mmalr
; /* Reset, R, T */
66 /* Common registers across all EMAC implementations. */
69 u32 ipgvr
; /* Reset, T */
70 u32 stacr
; /* Special */
71 u32 trtr
; /* Special */
76 /* Registers unique to EMAC4 implementations */
80 /* Registers unique to EMAC4SYNC implementations */
85 u32 iaht1
; /* Reset, R */
86 u32 iaht2
; /* Reset, R */
87 u32 iaht3
; /* Reset, R */
88 u32 iaht4
; /* Reset, R */
89 u32 iaht5
; /* Reset, R */
90 u32 iaht6
; /* Reset, R */
91 u32 iaht7
; /* Reset, R */
92 u32 iaht8
; /* Reset, R */
93 u32 gaht1
; /* Reset, R */
94 u32 gaht2
; /* Reset, R */
95 u32 gaht3
; /* Reset, R */
96 u32 gaht4
; /* Reset, R */
97 u32 gaht5
; /* Reset, R */
98 u32 gaht6
; /* Reset, R */
99 u32 gaht7
; /* Reset, R */
100 u32 gaht8
; /* Reset, R */
101 u32 tpc
; /* Reset, T */
107 * PHY mode settings (EMAC <-> ZMII/RGMII bridge <-> PHY)
109 #define PHY_MODE_NA 0
110 #define PHY_MODE_MII 1
111 #define PHY_MODE_RMII 2
112 #define PHY_MODE_SMII 3
113 #define PHY_MODE_RGMII 4
114 #define PHY_MODE_TBI 5
115 #define PHY_MODE_GMII 6
116 #define PHY_MODE_RTBI 7
117 #define PHY_MODE_SGMII 8
120 #define EMAC_MR0_RXI 0x80000000
121 #define EMAC_MR0_TXI 0x40000000
122 #define EMAC_MR0_SRST 0x20000000
123 #define EMAC_MR0_TXE 0x10000000
124 #define EMAC_MR0_RXE 0x08000000
125 #define EMAC_MR0_WKE 0x04000000
128 #define EMAC_MR1_FDE 0x80000000
129 #define EMAC_MR1_ILE 0x40000000
130 #define EMAC_MR1_VLE 0x20000000
131 #define EMAC_MR1_EIFC 0x10000000
132 #define EMAC_MR1_APP 0x08000000
133 #define EMAC_MR1_IST 0x01000000
135 #define EMAC_MR1_MF_MASK 0x00c00000
136 #define EMAC_MR1_MF_10 0x00000000
137 #define EMAC_MR1_MF_100 0x00400000
138 #define EMAC_MR1_MF_1000 0x00800000
139 #define EMAC_MR1_MF_1000GPCS 0x00c00000
140 #define EMAC_MR1_MF_IPPA(id) (((id) & 0x1f) << 6)
142 #define EMAC_MR1_RFS_4K 0x00300000
143 #define EMAC_MR1_RFS_16K 0x00000000
144 #define EMAC_MR1_TFS_2K 0x00080000
145 #define EMAC_MR1_TR0_MULT 0x00008000
146 #define EMAC_MR1_JPSM 0x00000000
147 #define EMAC_MR1_MWSW_001 0x00000000
148 #define EMAC_MR1_BASE(opb) (EMAC_MR1_TFS_2K | EMAC_MR1_TR0_MULT)
151 #define EMAC4_MR1_RFS_2K 0x00100000
152 #define EMAC4_MR1_RFS_4K 0x00180000
153 #define EMAC4_MR1_RFS_16K 0x00280000
154 #define EMAC4_MR1_TFS_2K 0x00020000
155 #define EMAC4_MR1_TFS_4K 0x00030000
156 #define EMAC4_MR1_TFS_16K 0x00050000
157 #define EMAC4_MR1_TR 0x00008000
158 #define EMAC4_MR1_MWSW_001 0x00001000
159 #define EMAC4_MR1_JPSM 0x00000800
160 #define EMAC4_MR1_OBCI_MASK 0x00000038
161 #define EMAC4_MR1_OBCI_50 0x00000000
162 #define EMAC4_MR1_OBCI_66 0x00000008
163 #define EMAC4_MR1_OBCI_83 0x00000010
164 #define EMAC4_MR1_OBCI_100 0x00000018
165 #define EMAC4_MR1_OBCI_100P 0x00000020
166 #define EMAC4_MR1_OBCI(freq) ((freq) <= 50 ? EMAC4_MR1_OBCI_50 : \
167 (freq) <= 66 ? EMAC4_MR1_OBCI_66 : \
168 (freq) <= 83 ? EMAC4_MR1_OBCI_83 : \
169 (freq) <= 100 ? EMAC4_MR1_OBCI_100 : \
173 #define EMAC_TMR0_GNP 0x80000000
174 #define EMAC_TMR0_DEFAULT 0x00000000
175 #define EMAC4_TMR0_TFAE_2_32 0x00000001
176 #define EMAC4_TMR0_TFAE_4_64 0x00000002
177 #define EMAC4_TMR0_TFAE_8_128 0x00000003
178 #define EMAC4_TMR0_TFAE_16_256 0x00000004
179 #define EMAC4_TMR0_TFAE_32_512 0x00000005
180 #define EMAC4_TMR0_TFAE_64_1024 0x00000006
181 #define EMAC4_TMR0_TFAE_128_2048 0x00000007
182 #define EMAC4_TMR0_DEFAULT EMAC4_TMR0_TFAE_2_32
183 #define EMAC_TMR0_XMIT (EMAC_TMR0_GNP | EMAC_TMR0_DEFAULT)
184 #define EMAC4_TMR0_XMIT (EMAC_TMR0_GNP | EMAC4_TMR0_DEFAULT)
188 #define EMAC_TMR1(l,h) (((l) << 27) | (((h) & 0xff) << 16))
189 #define EMAC4_TMR1(l,h) (((l) << 27) | (((h) & 0x3ff) << 14))
192 #define EMAC_RMR_SP 0x80000000
193 #define EMAC_RMR_SFCS 0x40000000
194 #define EMAC_RMR_RRP 0x20000000
195 #define EMAC_RMR_RFP 0x10000000
196 #define EMAC_RMR_ROP 0x08000000
197 #define EMAC_RMR_RPIR 0x04000000
198 #define EMAC_RMR_PPP 0x02000000
199 #define EMAC_RMR_PME 0x01000000
200 #define EMAC_RMR_PMME 0x00800000
201 #define EMAC_RMR_IAE 0x00400000
202 #define EMAC_RMR_MIAE 0x00200000
203 #define EMAC_RMR_BAE 0x00100000
204 #define EMAC_RMR_MAE 0x00080000
205 #define EMAC_RMR_BASE 0x00000000
206 #define EMAC4_RMR_RFAF_2_32 0x00000001
207 #define EMAC4_RMR_RFAF_4_64 0x00000002
208 #define EMAC4_RMR_RFAF_8_128 0x00000003
209 #define EMAC4_RMR_RFAF_16_256 0x00000004
210 #define EMAC4_RMR_RFAF_32_512 0x00000005
211 #define EMAC4_RMR_RFAF_64_1024 0x00000006
212 #define EMAC4_RMR_RFAF_128_2048 0x00000007
213 #define EMAC4_RMR_BASE EMAC4_RMR_RFAF_128_2048
215 /* EMACx_ISR & EMACx_ISER */
216 #define EMAC4_ISR_TXPE 0x20000000
217 #define EMAC4_ISR_RXPE 0x10000000
218 #define EMAC4_ISR_TXUE 0x08000000
219 #define EMAC4_ISR_RXOE 0x04000000
220 #define EMAC_ISR_OVR 0x02000000
221 #define EMAC_ISR_PP 0x01000000
222 #define EMAC_ISR_BP 0x00800000
223 #define EMAC_ISR_RP 0x00400000
224 #define EMAC_ISR_SE 0x00200000
225 #define EMAC_ISR_ALE 0x00100000
226 #define EMAC_ISR_BFCS 0x00080000
227 #define EMAC_ISR_PTLE 0x00040000
228 #define EMAC_ISR_ORE 0x00020000
229 #define EMAC_ISR_IRE 0x00010000
230 #define EMAC_ISR_SQE 0x00000080
231 #define EMAC_ISR_TE 0x00000040
232 #define EMAC_ISR_MOS 0x00000002
233 #define EMAC_ISR_MOF 0x00000001
236 #define EMAC_STACR_PHYD_MASK 0xffff
237 #define EMAC_STACR_PHYD_SHIFT 16
238 #define EMAC_STACR_OC 0x00008000
239 #define EMAC_STACR_PHYE 0x00004000
240 #define EMAC_STACR_STAC_MASK 0x00003000
241 #define EMAC_STACR_STAC_READ 0x00001000
242 #define EMAC_STACR_STAC_WRITE 0x00002000
243 #define EMAC_STACR_OPBC_MASK 0x00000C00
244 #define EMAC_STACR_OPBC_50 0x00000000
245 #define EMAC_STACR_OPBC_66 0x00000400
246 #define EMAC_STACR_OPBC_83 0x00000800
247 #define EMAC_STACR_OPBC_100 0x00000C00
248 #define EMAC_STACR_OPBC(freq) ((freq) <= 50 ? EMAC_STACR_OPBC_50 : \
249 (freq) <= 66 ? EMAC_STACR_OPBC_66 : \
250 (freq) <= 83 ? EMAC_STACR_OPBC_83 : EMAC_STACR_OPBC_100)
251 #define EMAC_STACR_BASE(opb) EMAC_STACR_OPBC(opb)
252 #define EMAC4_STACR_BASE(opb) 0x00000000
253 #define EMAC_STACR_PCDA_MASK 0x1f
254 #define EMAC_STACR_PCDA_SHIFT 5
255 #define EMAC_STACR_PRA_MASK 0x1f
256 #define EMACX_STACR_STAC_MASK 0x00003800
257 #define EMACX_STACR_STAC_READ 0x00001000
258 #define EMACX_STACR_STAC_WRITE 0x00000800
259 #define EMACX_STACR_STAC_IND_ADDR 0x00002000
260 #define EMACX_STACR_STAC_IND_READ 0x00003800
261 #define EMACX_STACR_STAC_IND_READINC 0x00003000
262 #define EMACX_STACR_STAC_IND_WRITE 0x00002800
266 #define EMAC_TRTR_SHIFT_EMAC4 24
267 #define EMAC_TRTR_SHIFT 27
269 /* EMAC specific TX descriptor control fields (write access) */
270 #define EMAC_TX_CTRL_GFCS 0x0200
271 #define EMAC_TX_CTRL_GP 0x0100
272 #define EMAC_TX_CTRL_ISA 0x0080
273 #define EMAC_TX_CTRL_RSA 0x0040
274 #define EMAC_TX_CTRL_IVT 0x0020
275 #define EMAC_TX_CTRL_RVT 0x0010
276 #define EMAC_TX_CTRL_TAH_CSUM 0x000e
278 /* EMAC specific TX descriptor status fields (read access) */
279 #define EMAC_TX_ST_BFCS 0x0200
280 #define EMAC_TX_ST_LCS 0x0080
281 #define EMAC_TX_ST_ED 0x0040
282 #define EMAC_TX_ST_EC 0x0020
283 #define EMAC_TX_ST_LC 0x0010
284 #define EMAC_TX_ST_MC 0x0008
285 #define EMAC_TX_ST_SC 0x0004
286 #define EMAC_TX_ST_UR 0x0002
287 #define EMAC_TX_ST_SQE 0x0001
288 #define EMAC_IS_BAD_TX (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
289 EMAC_TX_ST_EC | EMAC_TX_ST_LC | \
290 EMAC_TX_ST_MC | EMAC_TX_ST_UR)
291 #define EMAC_IS_BAD_TX_TAH (EMAC_TX_ST_LCS | EMAC_TX_ST_ED | \
292 EMAC_TX_ST_EC | EMAC_TX_ST_LC)
294 /* EMAC specific RX descriptor status fields (read access) */
295 #define EMAC_RX_ST_OE 0x0200
296 #define EMAC_RX_ST_PP 0x0100
297 #define EMAC_RX_ST_BP 0x0080
298 #define EMAC_RX_ST_RP 0x0040
299 #define EMAC_RX_ST_SE 0x0020
300 #define EMAC_RX_ST_AE 0x0010
301 #define EMAC_RX_ST_BFCS 0x0008
302 #define EMAC_RX_ST_PTL 0x0004
303 #define EMAC_RX_ST_ORE 0x0002
304 #define EMAC_RX_ST_IRE 0x0001
305 #define EMAC_RX_TAH_BAD_CSUM 0x0003
306 #define EMAC_BAD_RX_MASK (EMAC_RX_ST_OE | EMAC_RX_ST_BP | \
307 EMAC_RX_ST_RP | EMAC_RX_ST_SE | \
308 EMAC_RX_ST_AE | EMAC_RX_ST_BFCS | \
309 EMAC_RX_ST_PTL | EMAC_RX_ST_ORE | \
311 #endif /* __IBM_NEWEMAC_H */