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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / net / jme.h
blobfff885e9274e78550b0bf90327ee499c5e6a01e1
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 #ifndef __JME_H_INCLUDED__
26 #define __JME_H_INCLUDED__
27
28 #define DRV_NAME "jme"
29 #define DRV_VERSION "1.0.8"
30 #define PFX DRV_NAME ": "
31
32 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
33 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
34
35 /*
36 * Message related definitions
37 */
38 #define JME_DEF_MSG_ENABLE \
39 (NETIF_MSG_PROBE | \
40 NETIF_MSG_LINK | \
41 NETIF_MSG_RX_ERR | \
42 NETIF_MSG_TX_ERR | \
43 NETIF_MSG_HW)
44
45 #ifdef TX_DEBUG
46 #define tx_dbg(priv, fmt, args...) \
47 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
48 #else
49 #define tx_dbg(priv, fmt, args...) \
50 do { \
51 if (0) \
52 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
53 } while (0)
54 #endif
55
56 /*
57 * Extra PCI Configuration space interface
58 */
59 #define PCI_DCSR_MRRS 0x59
60 #define PCI_DCSR_MRRS_MASK 0x70
61
62 enum pci_dcsr_mrrs_vals {
63 MRRS_128B = 0x00,
64 MRRS_256B = 0x10,
65 MRRS_512B = 0x20,
66 MRRS_1024B = 0x30,
67 MRRS_2048B = 0x40,
68 MRRS_4096B = 0x50,
69 };
70
71 #define PCI_SPI 0xB0
72
73 enum pci_spi_bits {
74 SPI_EN = 0x10,
75 SPI_MISO = 0x08,
76 SPI_MOSI = 0x04,
77 SPI_SCLK = 0x02,
78 SPI_CS = 0x01,
79 };
80
81 struct jme_spi_op {
82 void __user *uwbuf;
83 void __user *urbuf;
84 __u8 wn; /* Number of write actions */
85 __u8 rn; /* Number of read actions */
86 __u8 bitn; /* Number of bits per action */
87 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
88 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
89
90 /* Internal use only */
91 u8 *kwbuf;
92 u8 *krbuf;
93 u8 sr;
94 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
95 };
96
97 enum jme_spi_op_bits {
98 SPI_MODE_CPHA = 0x01,
99 SPI_MODE_CPOL = 0x02,
100 SPI_MODE_DUP = 0x80,
101 };
102
103 #define HALF_US 500 /* 500 ns */
104 #define JMESPIIOCTL SIOCDEVPRIVATE
105
106 #define PCI_PRIV_PE1 0xE4
107
108 enum pci_priv_pe1_bit_masks {
109 PE1_ASPMSUPRT = 0x00000003, /*
110 * RW:
111 * Aspm_support[1:0]
112 * (R/W Port of 5C[11:10])
113 */
114 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
115 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
116 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
117 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
118 PE1_GPREG0 = 0x0000FF00, /*
119 * SRW:
120 * Cfg_gp_reg0
121 * [7:6] phy_giga BG control
122 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
123 * [4:0] Reserved
124 */
125 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
126 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
127 PE1_REVID = 0xFF000000, /* RO: Rev ID */
128 };
129
130 enum pci_priv_pe1_values {
131 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
132 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
133 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
134 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
135 };
136
137 /*
138 * Dynamic(adaptive)/Static PCC values
139 */
140 enum dynamic_pcc_values {
141 PCC_OFF = 0,
142 PCC_P1 = 1,
143 PCC_P2 = 2,
144 PCC_P3 = 3,
145
146 PCC_OFF_TO = 0,
147 PCC_P1_TO = 1,
148 PCC_P2_TO = 64,
149 PCC_P3_TO = 128,
150
151 PCC_OFF_CNT = 0,
152 PCC_P1_CNT = 1,
153 PCC_P2_CNT = 16,
154 PCC_P3_CNT = 32,
155 };
156 struct dynpcc_info {
157 unsigned long last_bytes;
158 unsigned long last_pkts;
159 unsigned long intr_cnt;
160 unsigned char cur;
161 unsigned char attempt;
162 unsigned char cnt;
163 };
164 #define PCC_INTERVAL_US 100000
165 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
166 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
167 #define PCC_P2_THRESHOLD 800
168 #define PCC_INTR_THRESHOLD 800
169 #define PCC_TX_TO 1000
170 #define PCC_TX_CNT 8
171
172 /*
173 * TX/RX Descriptors
174 *
175 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
176 */
177 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
178 #define TX_DESC_SIZE 16
179 #define TX_RING_NR 8
180 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
181
182 struct txdesc {
183 union {
184 __u8 all[16];
185 __le32 dw[4];
186 struct {
187 /* DW0 */
188 __le16 vlan;
189 __u8 rsv1;
190 __u8 flags;
191
192 /* DW1 */
193 __le16 datalen;
194 __le16 mss;
195
196 /* DW2 */
197 __le16 pktsize;
198 __le16 rsv2;
199
200 /* DW3 */
201 __le32 bufaddr;
202 } desc1;
203 struct {
204 /* DW0 */
205 __le16 rsv1;
206 __u8 rsv2;
207 __u8 flags;
208
209 /* DW1 */
210 __le16 datalen;
211 __le16 rsv3;
212
213 /* DW2 */
214 __le32 bufaddrh;
215
216 /* DW3 */
217 __le32 bufaddrl;
218 } desc2;
219 struct {
220 /* DW0 */
221 __u8 ehdrsz;
222 __u8 rsv1;
223 __u8 rsv2;
224 __u8 flags;
225
226 /* DW1 */
227 __le16 trycnt;
228 __le16 segcnt;
229
230 /* DW2 */
231 __le16 pktsz;
232 __le16 rsv3;
233
234 /* DW3 */
235 __le32 bufaddrl;
236 } descwb;
237 };
238 };
239
240 enum jme_txdesc_flags_bits {
241 TXFLAG_OWN = 0x80,
242 TXFLAG_INT = 0x40,
243 TXFLAG_64BIT = 0x20,
244 TXFLAG_TCPCS = 0x10,
245 TXFLAG_UDPCS = 0x08,
246 TXFLAG_IPCS = 0x04,
247 TXFLAG_LSEN = 0x02,
248 TXFLAG_TAGON = 0x01,
249 };
250
251 #define TXDESC_MSS_SHIFT 2
252 enum jme_txwbdesc_flags_bits {
253 TXWBFLAG_OWN = 0x80,
254 TXWBFLAG_INT = 0x40,
255 TXWBFLAG_TMOUT = 0x20,
256 TXWBFLAG_TRYOUT = 0x10,
257 TXWBFLAG_COL = 0x08,
258
259 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
260 TXWBFLAG_TRYOUT |
261 TXWBFLAG_COL,
262 };
263
264 #define RX_DESC_SIZE 16
265 #define RX_RING_NR 4
266 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
267 #define RX_BUF_DMA_ALIGN 8
268 #define RX_PREPAD_SIZE 10
269 #define ETH_CRC_LEN 2
270 #define RX_VLANHDR_LEN 2
271 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
272 ETH_HLEN + \
273 ETH_CRC_LEN + \
274 RX_VLANHDR_LEN + \
275 RX_BUF_DMA_ALIGN)
276
277 struct rxdesc {
278 union {
279 __u8 all[16];
280 __le32 dw[4];
281 struct {
282 /* DW0 */
283 __le16 rsv2;
284 __u8 rsv1;
285 __u8 flags;
286
287 /* DW1 */
288 __le16 datalen;
289 __le16 wbcpl;
290
291 /* DW2 */
292 __le32 bufaddrh;
293
294 /* DW3 */
295 __le32 bufaddrl;
296 } desc1;
297 struct {
298 /* DW0 */
299 __le16 vlan;
300 __le16 flags;
301
302 /* DW1 */
303 __le16 framesize;
304 __u8 errstat;
305 __u8 desccnt;
306
307 /* DW2 */
308 __le32 rsshash;
309
310 /* DW3 */
311 __u8 hashfun;
312 __u8 hashtype;
313 __le16 resrv;
314 } descwb;
315 };
316 };
317
318 enum jme_rxdesc_flags_bits {
319 RXFLAG_OWN = 0x80,
320 RXFLAG_INT = 0x40,
321 RXFLAG_64BIT = 0x20,
322 };
323
324 enum jme_rxwbdesc_flags_bits {
325 RXWBFLAG_OWN = 0x8000,
326 RXWBFLAG_INT = 0x4000,
327 RXWBFLAG_MF = 0x2000,
328 RXWBFLAG_64BIT = 0x2000,
329 RXWBFLAG_TCPON = 0x1000,
330 RXWBFLAG_UDPON = 0x0800,
331 RXWBFLAG_IPCS = 0x0400,
332 RXWBFLAG_TCPCS = 0x0200,
333 RXWBFLAG_UDPCS = 0x0100,
334 RXWBFLAG_TAGON = 0x0080,
335 RXWBFLAG_IPV4 = 0x0040,
336 RXWBFLAG_IPV6 = 0x0020,
337 RXWBFLAG_PAUSE = 0x0010,
338 RXWBFLAG_MAGIC = 0x0008,
339 RXWBFLAG_WAKEUP = 0x0004,
340 RXWBFLAG_DEST = 0x0003,
341 RXWBFLAG_DEST_UNI = 0x0001,
342 RXWBFLAG_DEST_MUL = 0x0002,
343 RXWBFLAG_DEST_BRO = 0x0003,
344 };
345
346 enum jme_rxwbdesc_desccnt_mask {
347 RXWBDCNT_WBCPL = 0x80,
348 RXWBDCNT_DCNT = 0x7F,
349 };
350
351 enum jme_rxwbdesc_errstat_bits {
352 RXWBERR_LIMIT = 0x80,
353 RXWBERR_MIIER = 0x40,
354 RXWBERR_NIBON = 0x20,
355 RXWBERR_COLON = 0x10,
356 RXWBERR_ABORT = 0x08,
357 RXWBERR_SHORT = 0x04,
358 RXWBERR_OVERUN = 0x02,
359 RXWBERR_CRCERR = 0x01,
360 RXWBERR_ALLERR = 0xFF,
361 };
362
363 /*
364 * Buffer information corresponding to ring descriptors.
365 */
366 struct jme_buffer_info {
367 struct sk_buff *skb;
368 dma_addr_t mapping;
369 int len;
370 int nr_desc;
371 unsigned long start_xmit;
372 };
373
374 /*
375 * The structure holding buffer information and ring descriptors all together.
376 */
377 struct jme_ring {
378 void *alloc; /* pointer to allocated memory */
379 void *desc; /* pointer to ring memory */
380 dma_addr_t dmaalloc; /* phys address of ring alloc */
381 dma_addr_t dma; /* phys address for ring dma */
382
383 /* Buffer information corresponding to each descriptor */
384 struct jme_buffer_info *bufinf;
385
386 int next_to_use;
387 atomic_t next_to_clean;
388 atomic_t nr_free;
389 };
390
391 #define NET_STAT(priv) (priv->dev->stats)
392 #define NETDEV_GET_STATS(netdev, fun_ptr)
393 #define DECLARE_NET_DEVICE_STATS
394
395 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
396 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
397 netif_napi_add(dev, napis, pollfn, q);
398 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
399 #define JME_NAPI_WEIGHT(w) int w
400 #define JME_NAPI_WEIGHT_VAL(w) w
401 #define JME_NAPI_WEIGHT_SET(w, r)
402 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
403 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
404 #define JME_NAPI_DISABLE(priv) \
405 if (!napi_disable_pending(&priv->napi)) \
406 napi_disable(&priv->napi);
407 #define JME_RX_SCHEDULE_PREP(priv) \
408 napi_schedule_prep(&priv->napi)
409 #define JME_RX_SCHEDULE(priv) \
410 __napi_schedule(&priv->napi);
411
412 /*
413 * Jmac Adapter Private data
414 */
415 struct jme_adapter {
416 struct pci_dev *pdev;
417 struct net_device *dev;
418 void __iomem *regs;
419 struct mii_if_info mii_if;
420 struct jme_ring rxring[RX_RING_NR];
421 struct jme_ring txring[TX_RING_NR];
422 spinlock_t phy_lock;
423 spinlock_t macaddr_lock;
424 spinlock_t rxmcs_lock;
425 struct tasklet_struct rxempty_task;
426 struct tasklet_struct rxclean_task;
427 struct tasklet_struct txclean_task;
428 struct tasklet_struct linkch_task;
429 struct tasklet_struct pcc_task;
430 unsigned long flags;
431 u32 reg_txcs;
432 u32 reg_txpfc;
433 u32 reg_rxcs;
434 u32 reg_rxmcs;
435 u32 reg_ghc;
436 u32 reg_pmcs;
437 u32 reg_gpreg1;
438 u32 phylink;
439 u32 tx_ring_size;
440 u32 tx_ring_mask;
441 u32 tx_wake_threshold;
442 u32 rx_ring_size;
443 u32 rx_ring_mask;
444 u8 mrrs;
445 unsigned int fpgaver;
446 u8 chiprev;
447 u8 chip_main_rev;
448 u8 chip_sub_rev;
449 u8 pcirev;
450 u32 msg_enable;
451 struct ethtool_cmd old_ecmd;
452 unsigned int old_mtu;
453 struct vlan_group *vlgrp;
454 struct dynpcc_info dpi;
455 atomic_t intr_sem;
456 atomic_t link_changing;
457 atomic_t tx_cleaning;
458 atomic_t rx_cleaning;
459 atomic_t rx_empty;
460 int (*jme_rx)(struct sk_buff *skb);
461 int (*jme_vlan_rx)(struct sk_buff *skb,
462 struct vlan_group *grp,
463 unsigned short vlan_tag);
464 DECLARE_NAPI_STRUCT
465 DECLARE_NET_DEVICE_STATS
466 };
467
468 enum jme_flags_bits {
469 JME_FLAG_MSI = 1,
470 JME_FLAG_SSET = 2,
471 JME_FLAG_POLL = 5,
472 JME_FLAG_SHUTDOWN = 6,
473 };
474
475 #define TX_TIMEOUT (5 * HZ)
476 #define JME_REG_LEN 0x500
477 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
478
479 static inline struct jme_adapter*
480 jme_napi_priv(struct napi_struct *napi)
481 {
482 struct jme_adapter *jme;
483 jme = container_of(napi, struct jme_adapter, napi);
484 return jme;
485 }
486
487 /*
488 * MMaped I/O Resters
489 */
490 enum jme_iomap_offsets {
491 JME_MAC = 0x0000,
492 JME_PHY = 0x0400,
493 JME_MISC = 0x0800,
494 JME_RSS = 0x0C00,
495 };
496
497 enum jme_iomap_lens {
498 JME_MAC_LEN = 0x80,
499 JME_PHY_LEN = 0x58,
500 JME_MISC_LEN = 0x98,
501 JME_RSS_LEN = 0xFF,
502 };
503
504 enum jme_iomap_regs {
505 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
506 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
507 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
508 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
509 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
510 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
511 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
512 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
513
514 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
515 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
516 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
517 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
518 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
519 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
520 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
521 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
522 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
523 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
524 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
525 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
526
527 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
528 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
529 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
530
531
532 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
533 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
534 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
535 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
536 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
537
538
539 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
540 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
541 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
542 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
543 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
544 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
545 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
546 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
547 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
548 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
549 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
550 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
551 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
552 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
553 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
554 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
555 };
556
557 /*
558 * TX Control/Status Bits
559 */
560 enum jme_txcs_bits {
561 TXCS_QUEUE7S = 0x00008000,
562 TXCS_QUEUE6S = 0x00004000,
563 TXCS_QUEUE5S = 0x00002000,
564 TXCS_QUEUE4S = 0x00001000,
565 TXCS_QUEUE3S = 0x00000800,
566 TXCS_QUEUE2S = 0x00000400,
567 TXCS_QUEUE1S = 0x00000200,
568 TXCS_QUEUE0S = 0x00000100,
569 TXCS_FIFOTH = 0x000000C0,
570 TXCS_DMASIZE = 0x00000030,
571 TXCS_BURST = 0x00000004,
572 TXCS_ENABLE = 0x00000001,
573 };
574
575 enum jme_txcs_value {
576 TXCS_FIFOTH_16QW = 0x000000C0,
577 TXCS_FIFOTH_12QW = 0x00000080,
578 TXCS_FIFOTH_8QW = 0x00000040,
579 TXCS_FIFOTH_4QW = 0x00000000,
580
581 TXCS_DMASIZE_64B = 0x00000000,
582 TXCS_DMASIZE_128B = 0x00000010,
583 TXCS_DMASIZE_256B = 0x00000020,
584 TXCS_DMASIZE_512B = 0x00000030,
585
586 TXCS_SELECT_QUEUE0 = 0x00000000,
587 TXCS_SELECT_QUEUE1 = 0x00010000,
588 TXCS_SELECT_QUEUE2 = 0x00020000,
589 TXCS_SELECT_QUEUE3 = 0x00030000,
590 TXCS_SELECT_QUEUE4 = 0x00040000,
591 TXCS_SELECT_QUEUE5 = 0x00050000,
592 TXCS_SELECT_QUEUE6 = 0x00060000,
593 TXCS_SELECT_QUEUE7 = 0x00070000,
594
595 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
596 TXCS_BURST,
597 };
598
599 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
600
601 /*
602 * TX MAC Control/Status Bits
603 */
604 enum jme_txmcs_bit_masks {
605 TXMCS_IFG2 = 0xC0000000,
606 TXMCS_IFG1 = 0x30000000,
607 TXMCS_TTHOLD = 0x00000300,
608 TXMCS_FBURST = 0x00000080,
609 TXMCS_CARRIEREXT = 0x00000040,
610 TXMCS_DEFER = 0x00000020,
611 TXMCS_BACKOFF = 0x00000010,
612 TXMCS_CARRIERSENSE = 0x00000008,
613 TXMCS_COLLISION = 0x00000004,
614 TXMCS_CRC = 0x00000002,
615 TXMCS_PADDING = 0x00000001,
616 };
617
618 enum jme_txmcs_values {
619 TXMCS_IFG2_6_4 = 0x00000000,
620 TXMCS_IFG2_8_5 = 0x40000000,
621 TXMCS_IFG2_10_6 = 0x80000000,
622 TXMCS_IFG2_12_7 = 0xC0000000,
623
624 TXMCS_IFG1_8_4 = 0x00000000,
625 TXMCS_IFG1_12_6 = 0x10000000,
626 TXMCS_IFG1_16_8 = 0x20000000,
627 TXMCS_IFG1_20_10 = 0x30000000,
628
629 TXMCS_TTHOLD_1_8 = 0x00000000,
630 TXMCS_TTHOLD_1_4 = 0x00000100,
631 TXMCS_TTHOLD_1_2 = 0x00000200,
632 TXMCS_TTHOLD_FULL = 0x00000300,
633
634 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
635 TXMCS_IFG1_16_8 |
636 TXMCS_TTHOLD_FULL |
637 TXMCS_DEFER |
638 TXMCS_CRC |
639 TXMCS_PADDING,
640 };
641
642 enum jme_txpfc_bits_masks {
643 TXPFC_VLAN_TAG = 0xFFFF0000,
644 TXPFC_VLAN_EN = 0x00008000,
645 TXPFC_PF_EN = 0x00000001,
646 };
647
648 enum jme_txtrhd_bits_masks {
649 TXTRHD_TXPEN = 0x80000000,
650 TXTRHD_TXP = 0x7FFFFF00,
651 TXTRHD_TXREN = 0x00000080,
652 TXTRHD_TXRL = 0x0000007F,
653 };
654
655 enum jme_txtrhd_shifts {
656 TXTRHD_TXP_SHIFT = 8,
657 TXTRHD_TXRL_SHIFT = 0,
658 };
659
660 enum jme_txtrhd_values {
661 TXTRHD_FULLDUPLEX = 0x00000000,
662 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
663 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
664 TXTRHD_TXREN |
665 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
666 };
667
668 /*
669 * RX Control/Status Bits
670 */
671 enum jme_rxcs_bit_masks {
672 /* FIFO full threshold for transmitting Tx Pause Packet */
673 RXCS_FIFOTHTP = 0x30000000,
674 /* FIFO threshold for processing next packet */
675 RXCS_FIFOTHNP = 0x0C000000,
676 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
677 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
678 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
679 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
680 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
681 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
682 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
683 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
684 RXCS_QST = 0x00000004, /* Receive queue start */
685 RXCS_SUSPEND = 0x00000002,
686 RXCS_ENABLE = 0x00000001,
687 };
688
689 enum jme_rxcs_values {
690 RXCS_FIFOTHTP_16T = 0x00000000,
691 RXCS_FIFOTHTP_32T = 0x10000000,
692 RXCS_FIFOTHTP_64T = 0x20000000,
693 RXCS_FIFOTHTP_128T = 0x30000000,
694
695 RXCS_FIFOTHNP_16QW = 0x00000000,
696 RXCS_FIFOTHNP_32QW = 0x04000000,
697 RXCS_FIFOTHNP_64QW = 0x08000000,
698 RXCS_FIFOTHNP_128QW = 0x0C000000,
699
700 RXCS_DMAREQSZ_16B = 0x00000000,
701 RXCS_DMAREQSZ_32B = 0x01000000,
702 RXCS_DMAREQSZ_64B = 0x02000000,
703 RXCS_DMAREQSZ_128B = 0x03000000,
704
705 RXCS_QUEUESEL_Q0 = 0x00000000,
706 RXCS_QUEUESEL_Q1 = 0x00010000,
707 RXCS_QUEUESEL_Q2 = 0x00020000,
708 RXCS_QUEUESEL_Q3 = 0x00030000,
709
710 RXCS_RETRYGAP_256ns = 0x00000000,
711 RXCS_RETRYGAP_512ns = 0x00001000,
712 RXCS_RETRYGAP_1024ns = 0x00002000,
713 RXCS_RETRYGAP_2048ns = 0x00003000,
714 RXCS_RETRYGAP_4096ns = 0x00004000,
715 RXCS_RETRYGAP_8192ns = 0x00005000,
716 RXCS_RETRYGAP_16384ns = 0x00006000,
717 RXCS_RETRYGAP_32768ns = 0x00007000,
718
719 RXCS_RETRYCNT_0 = 0x00000000,
720 RXCS_RETRYCNT_4 = 0x00000100,
721 RXCS_RETRYCNT_8 = 0x00000200,
722 RXCS_RETRYCNT_12 = 0x00000300,
723 RXCS_RETRYCNT_16 = 0x00000400,
724 RXCS_RETRYCNT_20 = 0x00000500,
725 RXCS_RETRYCNT_24 = 0x00000600,
726 RXCS_RETRYCNT_28 = 0x00000700,
727 RXCS_RETRYCNT_32 = 0x00000800,
728 RXCS_RETRYCNT_36 = 0x00000900,
729 RXCS_RETRYCNT_40 = 0x00000A00,
730 RXCS_RETRYCNT_44 = 0x00000B00,
731 RXCS_RETRYCNT_48 = 0x00000C00,
732 RXCS_RETRYCNT_52 = 0x00000D00,
733 RXCS_RETRYCNT_56 = 0x00000E00,
734 RXCS_RETRYCNT_60 = 0x00000F00,
735
736 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
737 RXCS_FIFOTHNP_16QW |
738 RXCS_DMAREQSZ_128B |
739 RXCS_RETRYGAP_256ns |
740 RXCS_RETRYCNT_32,
741 };
742
743 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
744
745 /*
746 * RX MAC Control/Status Bits
747 */
748 enum jme_rxmcs_bits {
749 RXMCS_ALLFRAME = 0x00000800,
750 RXMCS_BRDFRAME = 0x00000400,
751 RXMCS_MULFRAME = 0x00000200,
752 RXMCS_UNIFRAME = 0x00000100,
753 RXMCS_ALLMULFRAME = 0x00000080,
754 RXMCS_MULFILTERED = 0x00000040,
755 RXMCS_RXCOLLDEC = 0x00000020,
756 RXMCS_FLOWCTRL = 0x00000008,
757 RXMCS_VTAGRM = 0x00000004,
758 RXMCS_PREPAD = 0x00000002,
759 RXMCS_CHECKSUM = 0x00000001,
760
761 RXMCS_DEFAULT = RXMCS_VTAGRM |
762 RXMCS_PREPAD |
763 RXMCS_FLOWCTRL |
764 RXMCS_CHECKSUM,
765 };
766
767 /*
768 * Wakeup Frame setup interface registers
769 */
770 #define WAKEUP_FRAME_NR 8
771 #define WAKEUP_FRAME_MASK_DWNR 4
772
773 enum jme_wfoi_bit_masks {
774 WFOI_MASK_SEL = 0x00000070,
775 WFOI_CRC_SEL = 0x00000008,
776 WFOI_FRAME_SEL = 0x00000007,
777 };
778
779 enum jme_wfoi_shifts {
780 WFOI_MASK_SHIFT = 4,
781 };
782
783 /*
784 * SMI Related definitions
785 */
786 enum jme_smi_bit_mask {
787 SMI_DATA_MASK = 0xFFFF0000,
788 SMI_REG_ADDR_MASK = 0x0000F800,
789 SMI_PHY_ADDR_MASK = 0x000007C0,
790 SMI_OP_WRITE = 0x00000020,
791 /* Set to 1, after req done it'll be cleared to 0 */
792 SMI_OP_REQ = 0x00000010,
793 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
794 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
795 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
796 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
797 };
798
799 enum jme_smi_bit_shift {
800 SMI_DATA_SHIFT = 16,
801 SMI_REG_ADDR_SHIFT = 11,
802 SMI_PHY_ADDR_SHIFT = 6,
803 };
804
805 static inline u32 smi_reg_addr(int x)
806 {
807 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
808 }
809
810 static inline u32 smi_phy_addr(int x)
811 {
812 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
813 }
814
815 #define JME_PHY_TIMEOUT 100 /* 100 msec */
816 #define JME_PHY_REG_NR 32
817
818 /*
819 * Global Host Control
820 */
821 enum jme_ghc_bit_mask {
822 GHC_SWRST = 0x40000000,
823 GHC_TO_CLK_SRC = 0x00C00000,
824 GHC_TXMAC_CLK_SRC = 0x00300000,
825 GHC_DPX = 0x00000040,
826 GHC_SPEED = 0x00000030,
827 GHC_LINK_POLL = 0x00000001,
828 };
829
830 enum jme_ghc_speed_val {
831 GHC_SPEED_10M = 0x00000010,
832 GHC_SPEED_100M = 0x00000020,
833 GHC_SPEED_1000M = 0x00000030,
834 };
835
836 enum jme_ghc_to_clk {
837 GHC_TO_CLK_OFF = 0x00000000,
838 GHC_TO_CLK_GPHY = 0x00400000,
839 GHC_TO_CLK_PCIE = 0x00800000,
840 GHC_TO_CLK_INVALID = 0x00C00000,
841 };
842
843 enum jme_ghc_txmac_clk {
844 GHC_TXMAC_CLK_OFF = 0x00000000,
845 GHC_TXMAC_CLK_GPHY = 0x00100000,
846 GHC_TXMAC_CLK_PCIE = 0x00200000,
847 GHC_TXMAC_CLK_INVALID = 0x00300000,
848 };
849
850 /*
851 * Power management control and status register
852 */
853 enum jme_pmcs_bit_masks {
854 PMCS_WF7DET = 0x80000000,
855 PMCS_WF6DET = 0x40000000,
856 PMCS_WF5DET = 0x20000000,
857 PMCS_WF4DET = 0x10000000,
858 PMCS_WF3DET = 0x08000000,
859 PMCS_WF2DET = 0x04000000,
860 PMCS_WF1DET = 0x02000000,
861 PMCS_WF0DET = 0x01000000,
862 PMCS_LFDET = 0x00040000,
863 PMCS_LRDET = 0x00020000,
864 PMCS_MFDET = 0x00010000,
865 PMCS_WF7EN = 0x00008000,
866 PMCS_WF6EN = 0x00004000,
867 PMCS_WF5EN = 0x00002000,
868 PMCS_WF4EN = 0x00001000,
869 PMCS_WF3EN = 0x00000800,
870 PMCS_WF2EN = 0x00000400,
871 PMCS_WF1EN = 0x00000200,
872 PMCS_WF0EN = 0x00000100,
873 PMCS_LFEN = 0x00000004,
874 PMCS_LREN = 0x00000002,
875 PMCS_MFEN = 0x00000001,
876 };
877
878 /*
879 * New PHY Power Control Register
880 */
881 enum jme_phy_pwr_bit_masks {
882 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
883 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
884 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
885 PHY_PWR_CLKSEL = 0x08000000, /*
886 * XTL_OUT Clock select
887 * (an internal free-running clock)
888 * 0: xtl_out = phy_giga.A_XTL25_O
889 * 1: xtl_out = phy_giga.PD_OSC
890 */
891 };
892
893 /*
894 * Giga PHY Status Registers
895 */
896 enum jme_phy_link_bit_mask {
897 PHY_LINK_SPEED_MASK = 0x0000C000,
898 PHY_LINK_DUPLEX = 0x00002000,
899 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
900 PHY_LINK_UP = 0x00000400,
901 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
902 PHY_LINK_MDI_STAT = 0x00000040,
903 };
904
905 enum jme_phy_link_speed_val {
906 PHY_LINK_SPEED_10M = 0x00000000,
907 PHY_LINK_SPEED_100M = 0x00004000,
908 PHY_LINK_SPEED_1000M = 0x00008000,
909 };
910
911 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
912
913 /*
914 * SMB Control and Status
915 */
916 enum jme_smbcsr_bit_mask {
917 SMBCSR_CNACK = 0x00020000,
918 SMBCSR_RELOAD = 0x00010000,
919 SMBCSR_EEPROMD = 0x00000020,
920 SMBCSR_INITDONE = 0x00000010,
921 SMBCSR_BUSY = 0x0000000F,
922 };
923
924 enum jme_smbintf_bit_mask {
925 SMBINTF_HWDATR = 0xFF000000,
926 SMBINTF_HWDATW = 0x00FF0000,
927 SMBINTF_HWADDR = 0x0000FF00,
928 SMBINTF_HWRWN = 0x00000020,
929 SMBINTF_HWCMD = 0x00000010,
930 SMBINTF_FASTM = 0x00000008,
931 SMBINTF_GPIOSCL = 0x00000004,
932 SMBINTF_GPIOSDA = 0x00000002,
933 SMBINTF_GPIOEN = 0x00000001,
934 };
935
936 enum jme_smbintf_vals {
937 SMBINTF_HWRWN_READ = 0x00000020,
938 SMBINTF_HWRWN_WRITE = 0x00000000,
939 };
940
941 enum jme_smbintf_shifts {
942 SMBINTF_HWDATR_SHIFT = 24,
943 SMBINTF_HWDATW_SHIFT = 16,
944 SMBINTF_HWADDR_SHIFT = 8,
945 };
946
947 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
948 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
949 #define JME_SMB_LEN 256
950 #define JME_EEPROM_MAGIC 0x250
951
952 /*
953 * Timer Control/Status Register
954 */
955 enum jme_tmcsr_bit_masks {
956 TMCSR_SWIT = 0x80000000,
957 TMCSR_EN = 0x01000000,
958 TMCSR_CNT = 0x00FFFFFF,
959 };
960
961 /*
962 * General Purpose REG-0
963 */
964 enum jme_gpreg0_masks {
965 GPREG0_DISSH = 0xFF000000,
966 GPREG0_PCIRLMT = 0x00300000,
967 GPREG0_PCCNOMUTCLR = 0x00040000,
968 GPREG0_LNKINTPOLL = 0x00001000,
969 GPREG0_PCCTMR = 0x00000300,
970 GPREG0_PHYADDR = 0x0000001F,
971 };
972
973 enum jme_gpreg0_vals {
974 GPREG0_DISSH_DW7 = 0x80000000,
975 GPREG0_DISSH_DW6 = 0x40000000,
976 GPREG0_DISSH_DW5 = 0x20000000,
977 GPREG0_DISSH_DW4 = 0x10000000,
978 GPREG0_DISSH_DW3 = 0x08000000,
979 GPREG0_DISSH_DW2 = 0x04000000,
980 GPREG0_DISSH_DW1 = 0x02000000,
981 GPREG0_DISSH_DW0 = 0x01000000,
982 GPREG0_DISSH_ALL = 0xFF000000,
983
984 GPREG0_PCIRLMT_8 = 0x00000000,
985 GPREG0_PCIRLMT_6 = 0x00100000,
986 GPREG0_PCIRLMT_5 = 0x00200000,
987 GPREG0_PCIRLMT_4 = 0x00300000,
988
989 GPREG0_PCCTMR_16ns = 0x00000000,
990 GPREG0_PCCTMR_256ns = 0x00000100,
991 GPREG0_PCCTMR_1us = 0x00000200,
992 GPREG0_PCCTMR_1ms = 0x00000300,
993
994 GPREG0_PHYADDR_1 = 0x00000001,
995
996 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
997 GPREG0_PCCTMR_1us |
998 GPREG0_PHYADDR_1,
999 };
1000
1001 /*
1002 * General Purpose REG-1
1003 */
1004 enum jme_gpreg1_bit_masks {
1005 GPREG1_RXCLKOFF = 0x04000000,
1006 GPREG1_PCREQN = 0x00020000,
1007 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1008 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1009 GPREG1_INTRDELAYUNIT = 0x00000018,
1010 GPREG1_INTRDELAYENABLE = 0x00000007,
1011 };
1012
1013 enum jme_gpreg1_vals {
1014 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1015 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1016 GPREG1_INTDLYUNIT_1US = 0x00000010,
1017 GPREG1_INTDLYUNIT_16US = 0x00000018,
1018
1019 GPREG1_INTDLYEN_1U = 0x00000001,
1020 GPREG1_INTDLYEN_2U = 0x00000002,
1021 GPREG1_INTDLYEN_3U = 0x00000003,
1022 GPREG1_INTDLYEN_4U = 0x00000004,
1023 GPREG1_INTDLYEN_5U = 0x00000005,
1024 GPREG1_INTDLYEN_6U = 0x00000006,
1025 GPREG1_INTDLYEN_7U = 0x00000007,
1026
1027 GPREG1_DEFAULT = GPREG1_PCREQN,
1028 };
1029
1030 /*
1031 * Interrupt Status Bits
1032 */
1033 enum jme_interrupt_bits {
1034 INTR_SWINTR = 0x80000000,
1035 INTR_TMINTR = 0x40000000,
1036 INTR_LINKCH = 0x20000000,
1037 INTR_PAUSERCV = 0x10000000,
1038 INTR_MAGICRCV = 0x08000000,
1039 INTR_WAKERCV = 0x04000000,
1040 INTR_PCCRX0TO = 0x02000000,
1041 INTR_PCCRX1TO = 0x01000000,
1042 INTR_PCCRX2TO = 0x00800000,
1043 INTR_PCCRX3TO = 0x00400000,
1044 INTR_PCCTXTO = 0x00200000,
1045 INTR_PCCRX0 = 0x00100000,
1046 INTR_PCCRX1 = 0x00080000,
1047 INTR_PCCRX2 = 0x00040000,
1048 INTR_PCCRX3 = 0x00020000,
1049 INTR_PCCTX = 0x00010000,
1050 INTR_RX3EMP = 0x00008000,
1051 INTR_RX2EMP = 0x00004000,
1052 INTR_RX1EMP = 0x00002000,
1053 INTR_RX0EMP = 0x00001000,
1054 INTR_RX3 = 0x00000800,
1055 INTR_RX2 = 0x00000400,
1056 INTR_RX1 = 0x00000200,
1057 INTR_RX0 = 0x00000100,
1058 INTR_TX7 = 0x00000080,
1059 INTR_TX6 = 0x00000040,
1060 INTR_TX5 = 0x00000020,
1061 INTR_TX4 = 0x00000010,
1062 INTR_TX3 = 0x00000008,
1063 INTR_TX2 = 0x00000004,
1064 INTR_TX1 = 0x00000002,
1065 INTR_TX0 = 0x00000001,
1066 };
1067
1068 static const u32 INTR_ENABLE = INTR_SWINTR |
1069 INTR_TMINTR |
1070 INTR_LINKCH |
1071 INTR_PCCRX0TO |
1072 INTR_PCCRX0 |
1073 INTR_PCCTXTO |
1074 INTR_PCCTX |
1075 INTR_RX0EMP;
1076
1077 /*
1078 * PCC Control Registers
1079 */
1080 enum jme_pccrx_masks {
1081 PCCRXTO_MASK = 0xFFFF0000,
1082 PCCRX_MASK = 0x0000FF00,
1083 };
1084
1085 enum jme_pcctx_masks {
1086 PCCTXTO_MASK = 0xFFFF0000,
1087 PCCTX_MASK = 0x0000FF00,
1088 PCCTX_QS_MASK = 0x000000FF,
1089 };
1090
1091 enum jme_pccrx_shifts {
1092 PCCRXTO_SHIFT = 16,
1093 PCCRX_SHIFT = 8,
1094 };
1095
1096 enum jme_pcctx_shifts {
1097 PCCTXTO_SHIFT = 16,
1098 PCCTX_SHIFT = 8,
1099 };
1100
1101 enum jme_pcctx_bits {
1102 PCCTXQ0_EN = 0x00000001,
1103 PCCTXQ1_EN = 0x00000002,
1104 PCCTXQ2_EN = 0x00000004,
1105 PCCTXQ3_EN = 0x00000008,
1106 PCCTXQ4_EN = 0x00000010,
1107 PCCTXQ5_EN = 0x00000020,
1108 PCCTXQ6_EN = 0x00000040,
1109 PCCTXQ7_EN = 0x00000080,
1110 };
1111
1112 /*
1113 * Chip Mode Register
1114 */
1115 enum jme_chipmode_bit_masks {
1116 CM_FPGAVER_MASK = 0xFFFF0000,
1117 CM_CHIPREV_MASK = 0x0000FF00,
1118 CM_CHIPMODE_MASK = 0x0000000F,
1119 };
1120
1121 enum jme_chipmode_shifts {
1122 CM_FPGAVER_SHIFT = 16,
1123 CM_CHIPREV_SHIFT = 8,
1124 };
1125
1126 /*
1127 * Aggressive Power Mode Control
1128 */
1129 enum jme_apmc_bits {
1130 JME_APMC_PCIE_SD_EN = 0x40000000,
1131 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1132 JME_APMC_EPIEN = 0x04000000,
1133 JME_APMC_EPIEN_CTRL = 0x03000000,
1134 };
1135
1136 enum jme_apmc_values {
1137 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1138 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1139 };
1140
1141 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1142
1143 #ifdef REG_DEBUG
1144 static char *MAC_REG_NAME[] = {
1145 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1146 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1147 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1148 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1149 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1150 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1151 "JME_PMCS"};
1152
1153 static char *PE_REG_NAME[] = {
1154 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1155 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1156 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1157 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1158 "JME_SMBCSR", "JME_SMBINTF"};
1159
1160 static char *MISC_REG_NAME[] = {
1161 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1162 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1163 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1164 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1165 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1166 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1167 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1168 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1169 "JME_PCCSRX0"};
1170
1171 static inline void reg_dbg(const struct jme_adapter *jme,
1172 const char *msg, u32 val, u32 reg)
1173 {
1174 const char *regname;
1175 switch (reg & 0xF00) {
1176 case 0x000:
1177 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1178 break;
1179 case 0x400:
1180 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1181 break;
1182 case 0x800:
1183 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1184 break;
1185 default:
1186 regname = PE_REG_NAME[0];
1187 }
1188 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1189 msg, val, regname);
1190 }
1191 #else
1192 static inline void reg_dbg(const struct jme_adapter *jme,
1193 const char *msg, u32 val, u32 reg) {}
1194 #endif
1195
1196 /*
1197 * Read/Write MMaped I/O Registers
1198 */
1199 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1200 {
1201 return readl(jme->regs + reg);
1202 }
1203
1204 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1205 {
1206 reg_dbg(jme, "REG WRITE", val, reg);
1207 writel(val, jme->regs + reg);
1208 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1209 }
1210
1211 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1212 {
1213 /*
1214 * Read after write should cause flush
1215 */
1216 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1217 writel(val, jme->regs + reg);
1218 readl(jme->regs + reg);
1219 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1220 }
1221
1222 /*
1223 * PHY Regs
1224 */
1225 enum jme_phy_reg17_bit_masks {
1226 PREG17_SPEED = 0xC000,
1227 PREG17_DUPLEX = 0x2000,
1228 PREG17_SPDRSV = 0x0800,
1229 PREG17_LNKUP = 0x0400,
1230 PREG17_MDI = 0x0040,
1231 };
1232
1233 enum jme_phy_reg17_vals {
1234 PREG17_SPEED_10M = 0x0000,
1235 PREG17_SPEED_100M = 0x4000,
1236 PREG17_SPEED_1000M = 0x8000,
1237 };
1238
1239 #define BMSR_ANCOMP 0x0020
1240
1241 /*
1242 * Workaround
1243 */
1244 static inline int is_buggy250(unsigned short device, u8 chiprev)
1245 {
1246 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1247 }
1248
1249 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1250 {
1251 return chip_main_rev >= 5;
1252 }
1253
1254 /*
1255 * Function prototypes
1256 */
1257 static int jme_set_settings(struct net_device *netdev,
1258 struct ethtool_cmd *ecmd);
1259 static void jme_set_unicastaddr(struct net_device *netdev);
1260 static void jme_set_multi(struct net_device *netdev);
1261
1262 #endif
Linux with added FPC-III support