2 * SuperH Ethernet device driver
4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
23 #include <linux/init.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/platform_device.h>
28 #include <linux/mdio-bitbang.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/cache.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/slab.h>
35 #include <linux/ethtool.h>
36 #include <asm/cacheflush.h>
40 #define SH_ETH_DEF_MSG_ENABLE \
46 /* There is CPU dependent code */
47 #if defined(CONFIG_CPU_SUBTYPE_SH7724)
48 #define SH_ETH_RESET_DEFAULT 1
49 static void sh_eth_set_duplex(struct net_device
*ndev
)
51 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
53 if (mdp
->duplex
) /* Full */
54 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
56 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
59 static void sh_eth_set_rate(struct net_device
*ndev
)
61 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
65 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_RTM
, ECMR
);
67 case 100:/* 100BASE */
68 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_RTM
, ECMR
);
76 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
77 .set_duplex
= sh_eth_set_duplex
,
78 .set_rate
= sh_eth_set_rate
,
80 .ecsr_value
= ECSR_PSRTO
| ECSR_LCHNG
| ECSR_ICD
,
81 .ecsipr_value
= ECSIPR_PSRTOIP
| ECSIPR_LCHNGIP
| ECSIPR_ICDIP
,
82 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x01ff009f,
84 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
85 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
86 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
87 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
94 .rpadir_value
= 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7757)
97 #define SH_ETH_HAS_BOTH_MODULES 1
98 #define SH_ETH_HAS_TSU 1
99 static void sh_eth_set_duplex(struct net_device
*ndev
)
101 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
103 if (mdp
->duplex
) /* Full */
104 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
106 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
109 static void sh_eth_set_rate(struct net_device
*ndev
)
111 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
113 switch (mdp
->speed
) {
114 case 10: /* 10BASE */
115 sh_eth_write(ndev
, 0, RTRATE
);
117 case 100:/* 100BASE */
118 sh_eth_write(ndev
, 1, RTRATE
);
126 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
127 .set_duplex
= sh_eth_set_duplex
,
128 .set_rate
= sh_eth_set_rate
,
130 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
131 .rmcr_value
= 0x00000001,
133 .tx_check
= EESR_FTC
| EESR_CND
| EESR_DLC
| EESR_CD
| EESR_RTO
,
134 .eesr_err_check
= EESR_TWB
| EESR_TABT
| EESR_RABT
| EESR_RDE
|
135 EESR_RFRMER
| EESR_TFE
| EESR_TDE
| EESR_ECI
,
136 .tx_error_check
= EESR_TWB
| EESR_TABT
| EESR_TDE
| EESR_TFE
,
144 .rpadir_value
= 2 << 16,
147 #define SH_GIGA_ETH_BASE 0xfee00000
148 #define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
149 #define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
150 static void sh_eth_chip_reset_giga(struct net_device
*ndev
)
153 unsigned long mahr
[2], malr
[2];
155 /* save MAHR and MALR */
156 for (i
= 0; i
< 2; i
++) {
157 malr
[i
] = readl(GIGA_MALR(i
));
158 mahr
[i
] = readl(GIGA_MAHR(i
));
162 writel(ARSTR_ARSTR
, SH_GIGA_ETH_BASE
+ 0x1800);
165 /* restore MAHR and MALR */
166 for (i
= 0; i
< 2; i
++) {
167 writel(malr
[i
], GIGA_MALR(i
));
168 writel(mahr
[i
], GIGA_MAHR(i
));
172 static int sh_eth_is_gether(struct sh_eth_private
*mdp
);
173 static void sh_eth_reset(struct net_device
*ndev
)
175 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
178 if (sh_eth_is_gether(mdp
)) {
179 sh_eth_write(ndev
, 0x03, EDSR
);
180 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
,
183 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
189 printk(KERN_ERR
"Device reset fail\n");
192 sh_eth_write(ndev
, 0x0, TDLAR
);
193 sh_eth_write(ndev
, 0x0, TDFAR
);
194 sh_eth_write(ndev
, 0x0, TDFXR
);
195 sh_eth_write(ndev
, 0x0, TDFFR
);
196 sh_eth_write(ndev
, 0x0, RDLAR
);
197 sh_eth_write(ndev
, 0x0, RDFAR
);
198 sh_eth_write(ndev
, 0x0, RDFXR
);
199 sh_eth_write(ndev
, 0x0, RDFFR
);
201 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
,
204 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
,
209 static void sh_eth_set_duplex_giga(struct net_device
*ndev
)
211 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
213 if (mdp
->duplex
) /* Full */
214 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
216 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
219 static void sh_eth_set_rate_giga(struct net_device
*ndev
)
221 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
223 switch (mdp
->speed
) {
224 case 10: /* 10BASE */
225 sh_eth_write(ndev
, 0x00000000, GECMR
);
227 case 100:/* 100BASE */
228 sh_eth_write(ndev
, 0x00000010, GECMR
);
230 case 1000: /* 1000BASE */
231 sh_eth_write(ndev
, 0x00000020, GECMR
);
238 /* SH7757(GETHERC) */
239 static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga
= {
240 .chip_reset
= sh_eth_chip_reset_giga
,
241 .set_duplex
= sh_eth_set_duplex_giga
,
242 .set_rate
= sh_eth_set_rate_giga
,
244 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
245 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
246 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
248 .tx_check
= EESR_TC1
| EESR_FTC
,
249 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
250 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
252 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
254 .fdr_value
= 0x0000072f,
255 .rmcr_value
= 0x00000001,
263 .rpadir_value
= 2 << 16,
268 static struct sh_eth_cpu_data
*sh_eth_get_cpu_data(struct sh_eth_private
*mdp
)
270 if (sh_eth_is_gether(mdp
))
271 return &sh_eth_my_cpu_data_giga
;
273 return &sh_eth_my_cpu_data
;
276 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
277 #define SH_ETH_HAS_TSU 1
278 static void sh_eth_chip_reset(struct net_device
*ndev
)
280 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
283 sh_eth_tsu_write(mdp
, ARSTR_ARSTR
, ARSTR
);
287 static void sh_eth_reset(struct net_device
*ndev
)
291 sh_eth_write(ndev
, EDSR_ENALL
, EDSR
);
292 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_GETHER
, EDMR
);
294 if (!(sh_eth_read(ndev
, EDMR
) & 0x3))
300 printk(KERN_ERR
"Device reset fail\n");
303 sh_eth_write(ndev
, 0x0, TDLAR
);
304 sh_eth_write(ndev
, 0x0, TDFAR
);
305 sh_eth_write(ndev
, 0x0, TDFXR
);
306 sh_eth_write(ndev
, 0x0, TDFFR
);
307 sh_eth_write(ndev
, 0x0, RDLAR
);
308 sh_eth_write(ndev
, 0x0, RDFAR
);
309 sh_eth_write(ndev
, 0x0, RDFXR
);
310 sh_eth_write(ndev
, 0x0, RDFFR
);
313 static void sh_eth_set_duplex(struct net_device
*ndev
)
315 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
317 if (mdp
->duplex
) /* Full */
318 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) | ECMR_DM
, ECMR
);
320 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) & ~ECMR_DM
, ECMR
);
323 static void sh_eth_set_rate(struct net_device
*ndev
)
325 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
327 switch (mdp
->speed
) {
328 case 10: /* 10BASE */
329 sh_eth_write(ndev
, GECMR_10
, GECMR
);
331 case 100:/* 100BASE */
332 sh_eth_write(ndev
, GECMR_100
, GECMR
);
334 case 1000: /* 1000BASE */
335 sh_eth_write(ndev
, GECMR_1000
, GECMR
);
343 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
344 .chip_reset
= sh_eth_chip_reset
,
345 .set_duplex
= sh_eth_set_duplex
,
346 .set_rate
= sh_eth_set_rate
,
348 .ecsr_value
= ECSR_ICD
| ECSR_MPD
,
349 .ecsipr_value
= ECSIPR_LCHNGIP
| ECSIPR_ICDIP
| ECSIPR_MPDIP
,
350 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
352 .tx_check
= EESR_TC1
| EESR_FTC
,
353 .eesr_err_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_RABT
| \
354 EESR_RDE
| EESR_RFRMER
| EESR_TFE
| EESR_TDE
| \
356 .tx_error_check
= EESR_TWB1
| EESR_TWB
| EESR_TABT
| EESR_TDE
| \
369 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
370 #define SH_ETH_RESET_DEFAULT 1
371 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
372 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
379 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
380 #define SH_ETH_RESET_DEFAULT 1
381 #define SH_ETH_HAS_TSU 1
382 static struct sh_eth_cpu_data sh_eth_my_cpu_data
= {
383 .eesipr_value
= DMAC_M_RFRMER
| DMAC_M_ECI
| 0x003fffff,
388 static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data
*cd
)
391 cd
->ecsr_value
= DEFAULT_ECSR_INIT
;
393 if (!cd
->ecsipr_value
)
394 cd
->ecsipr_value
= DEFAULT_ECSIPR_INIT
;
396 if (!cd
->fcftr_value
)
397 cd
->fcftr_value
= DEFAULT_FIFO_F_D_RFF
| \
398 DEFAULT_FIFO_F_D_RFD
;
401 cd
->fdr_value
= DEFAULT_FDR_INIT
;
404 cd
->rmcr_value
= DEFAULT_RMCR_VALUE
;
407 cd
->tx_check
= DEFAULT_TX_CHECK
;
409 if (!cd
->eesr_err_check
)
410 cd
->eesr_err_check
= DEFAULT_EESR_ERR_CHECK
;
412 if (!cd
->tx_error_check
)
413 cd
->tx_error_check
= DEFAULT_TX_ERROR_CHECK
;
416 #if defined(SH_ETH_RESET_DEFAULT)
418 static void sh_eth_reset(struct net_device
*ndev
)
420 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) | EDMR_SRST_ETHER
, EDMR
);
422 sh_eth_write(ndev
, sh_eth_read(ndev
, EDMR
) & ~EDMR_SRST_ETHER
, EDMR
);
426 #if defined(CONFIG_CPU_SH4)
427 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
431 reserve
= SH4_SKB_RX_ALIGN
- ((u32
)skb
->data
& (SH4_SKB_RX_ALIGN
- 1));
433 skb_reserve(skb
, reserve
);
436 static void sh_eth_set_receive_align(struct sk_buff
*skb
)
438 skb_reserve(skb
, SH2_SH3_SKB_RX_ALIGN
);
443 /* CPU <-> EDMAC endian convert */
444 static inline __u32
cpu_to_edmac(struct sh_eth_private
*mdp
, u32 x
)
446 switch (mdp
->edmac_endian
) {
447 case EDMAC_LITTLE_ENDIAN
:
448 return cpu_to_le32(x
);
449 case EDMAC_BIG_ENDIAN
:
450 return cpu_to_be32(x
);
455 static inline __u32
edmac_to_cpu(struct sh_eth_private
*mdp
, u32 x
)
457 switch (mdp
->edmac_endian
) {
458 case EDMAC_LITTLE_ENDIAN
:
459 return le32_to_cpu(x
);
460 case EDMAC_BIG_ENDIAN
:
461 return be32_to_cpu(x
);
467 * Program the hardware MAC address from dev->dev_addr.
469 static void update_mac_address(struct net_device
*ndev
)
472 (ndev
->dev_addr
[0] << 24) | (ndev
->dev_addr
[1] << 16) |
473 (ndev
->dev_addr
[2] << 8) | (ndev
->dev_addr
[3]), MAHR
);
475 (ndev
->dev_addr
[4] << 8) | (ndev
->dev_addr
[5]), MALR
);
479 * Get MAC address from SuperH MAC address register
481 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
482 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
483 * When you want use this device, you must set MAC address in bootloader.
486 static void read_mac_address(struct net_device
*ndev
, unsigned char *mac
)
488 if (mac
[0] || mac
[1] || mac
[2] || mac
[3] || mac
[4] || mac
[5]) {
489 memcpy(ndev
->dev_addr
, mac
, 6);
491 ndev
->dev_addr
[0] = (sh_eth_read(ndev
, MAHR
) >> 24);
492 ndev
->dev_addr
[1] = (sh_eth_read(ndev
, MAHR
) >> 16) & 0xFF;
493 ndev
->dev_addr
[2] = (sh_eth_read(ndev
, MAHR
) >> 8) & 0xFF;
494 ndev
->dev_addr
[3] = (sh_eth_read(ndev
, MAHR
) & 0xFF);
495 ndev
->dev_addr
[4] = (sh_eth_read(ndev
, MALR
) >> 8) & 0xFF;
496 ndev
->dev_addr
[5] = (sh_eth_read(ndev
, MALR
) & 0xFF);
500 static int sh_eth_is_gether(struct sh_eth_private
*mdp
)
502 if (mdp
->reg_offset
== sh_eth_offset_gigabit
)
508 static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private
*mdp
)
510 if (sh_eth_is_gether(mdp
))
511 return EDTRR_TRNS_GETHER
;
513 return EDTRR_TRNS_ETHER
;
517 void (*set_gate
)(unsigned long addr
);
518 struct mdiobb_ctrl ctrl
;
520 u32 mmd_msk
;/* MMD */
527 static void bb_set(u32 addr
, u32 msk
)
529 writel(readl(addr
) | msk
, addr
);
533 static void bb_clr(u32 addr
, u32 msk
)
535 writel((readl(addr
) & ~msk
), addr
);
539 static int bb_read(u32 addr
, u32 msk
)
541 return (readl(addr
) & msk
) != 0;
544 /* Data I/O pin control */
545 static void sh_mmd_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
547 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
549 if (bitbang
->set_gate
)
550 bitbang
->set_gate(bitbang
->addr
);
553 bb_set(bitbang
->addr
, bitbang
->mmd_msk
);
555 bb_clr(bitbang
->addr
, bitbang
->mmd_msk
);
559 static void sh_set_mdio(struct mdiobb_ctrl
*ctrl
, int bit
)
561 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
563 if (bitbang
->set_gate
)
564 bitbang
->set_gate(bitbang
->addr
);
567 bb_set(bitbang
->addr
, bitbang
->mdo_msk
);
569 bb_clr(bitbang
->addr
, bitbang
->mdo_msk
);
573 static int sh_get_mdio(struct mdiobb_ctrl
*ctrl
)
575 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
577 if (bitbang
->set_gate
)
578 bitbang
->set_gate(bitbang
->addr
);
580 return bb_read(bitbang
->addr
, bitbang
->mdi_msk
);
583 /* MDC pin control */
584 static void sh_mdc_ctrl(struct mdiobb_ctrl
*ctrl
, int bit
)
586 struct bb_info
*bitbang
= container_of(ctrl
, struct bb_info
, ctrl
);
588 if (bitbang
->set_gate
)
589 bitbang
->set_gate(bitbang
->addr
);
592 bb_set(bitbang
->addr
, bitbang
->mdc_msk
);
594 bb_clr(bitbang
->addr
, bitbang
->mdc_msk
);
597 /* mdio bus control struct */
598 static struct mdiobb_ops bb_ops
= {
599 .owner
= THIS_MODULE
,
600 .set_mdc
= sh_mdc_ctrl
,
601 .set_mdio_dir
= sh_mmd_ctrl
,
602 .set_mdio_data
= sh_set_mdio
,
603 .get_mdio_data
= sh_get_mdio
,
606 /* free skb and descriptor buffer */
607 static void sh_eth_ring_free(struct net_device
*ndev
)
609 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
612 /* Free Rx skb ringbuffer */
613 if (mdp
->rx_skbuff
) {
614 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
615 if (mdp
->rx_skbuff
[i
])
616 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
619 kfree(mdp
->rx_skbuff
);
621 /* Free Tx skb ringbuffer */
622 if (mdp
->tx_skbuff
) {
623 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
624 if (mdp
->tx_skbuff
[i
])
625 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
628 kfree(mdp
->tx_skbuff
);
631 /* format skb and descriptor buffer */
632 static void sh_eth_ring_format(struct net_device
*ndev
)
634 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
637 struct sh_eth_rxdesc
*rxdesc
= NULL
;
638 struct sh_eth_txdesc
*txdesc
= NULL
;
639 int rx_ringsize
= sizeof(*rxdesc
) * RX_RING_SIZE
;
640 int tx_ringsize
= sizeof(*txdesc
) * TX_RING_SIZE
;
642 mdp
->cur_rx
= mdp
->cur_tx
= 0;
643 mdp
->dirty_rx
= mdp
->dirty_tx
= 0;
645 memset(mdp
->rx_ring
, 0, rx_ringsize
);
647 /* build Rx ring buffer */
648 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
650 mdp
->rx_skbuff
[i
] = NULL
;
651 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
652 mdp
->rx_skbuff
[i
] = skb
;
655 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
657 skb
->dev
= ndev
; /* Mark as being used by this device. */
658 sh_eth_set_receive_align(skb
);
661 rxdesc
= &mdp
->rx_ring
[i
];
662 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
663 rxdesc
->status
= cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
665 /* The size of the buffer is 16 byte boundary. */
666 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
667 /* Rx descriptor address set */
669 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDLAR
);
670 if (sh_eth_is_gether(mdp
))
671 sh_eth_write(ndev
, mdp
->rx_desc_dma
, RDFAR
);
675 mdp
->dirty_rx
= (u32
) (i
- RX_RING_SIZE
);
677 /* Mark the last entry as wrapping the ring. */
678 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RDEL
);
680 memset(mdp
->tx_ring
, 0, tx_ringsize
);
682 /* build Tx ring buffer */
683 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
684 mdp
->tx_skbuff
[i
] = NULL
;
685 txdesc
= &mdp
->tx_ring
[i
];
686 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
687 txdesc
->buffer_length
= 0;
689 /* Tx descriptor address set */
690 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDLAR
);
691 if (sh_eth_is_gether(mdp
))
692 sh_eth_write(ndev
, mdp
->tx_desc_dma
, TDFAR
);
696 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
699 /* Get skb and descriptor buffer */
700 static int sh_eth_ring_init(struct net_device
*ndev
)
702 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
703 int rx_ringsize
, tx_ringsize
, ret
= 0;
706 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
707 * card needs room to do 8 byte alignment, +2 so we can reserve
708 * the first 2 bytes, and +16 gets room for the status word from the
711 mdp
->rx_buf_sz
= (ndev
->mtu
<= 1492 ? PKT_BUF_SZ
:
712 (((ndev
->mtu
+ 26 + 7) & ~7) + 2 + 16));
714 mdp
->rx_buf_sz
+= NET_IP_ALIGN
;
716 /* Allocate RX and TX skb rings */
717 mdp
->rx_skbuff
= kmalloc(sizeof(*mdp
->rx_skbuff
) * RX_RING_SIZE
,
719 if (!mdp
->rx_skbuff
) {
720 dev_err(&ndev
->dev
, "Cannot allocate Rx skb\n");
725 mdp
->tx_skbuff
= kmalloc(sizeof(*mdp
->tx_skbuff
) * TX_RING_SIZE
,
727 if (!mdp
->tx_skbuff
) {
728 dev_err(&ndev
->dev
, "Cannot allocate Tx skb\n");
733 /* Allocate all Rx descriptors. */
734 rx_ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
735 mdp
->rx_ring
= dma_alloc_coherent(NULL
, rx_ringsize
, &mdp
->rx_desc_dma
,
739 dev_err(&ndev
->dev
, "Cannot allocate Rx Ring (size %d bytes)\n",
747 /* Allocate all Tx descriptors. */
748 tx_ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
749 mdp
->tx_ring
= dma_alloc_coherent(NULL
, tx_ringsize
, &mdp
->tx_desc_dma
,
752 dev_err(&ndev
->dev
, "Cannot allocate Tx Ring (size %d bytes)\n",
760 /* free DMA buffer */
761 dma_free_coherent(NULL
, rx_ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
764 /* Free Rx and Tx skb ring buffer */
765 sh_eth_ring_free(ndev
);
770 static int sh_eth_dev_init(struct net_device
*ndev
)
773 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
774 u_int32_t rx_int_var
, tx_int_var
;
780 /* Descriptor format */
781 sh_eth_ring_format(ndev
);
783 sh_eth_write(ndev
, mdp
->cd
->rpadir_value
, RPADIR
);
785 /* all sh_eth int mask */
786 sh_eth_write(ndev
, 0, EESIPR
);
788 #if defined(__LITTLE_ENDIAN__)
789 if (mdp
->cd
->hw_swap
)
790 sh_eth_write(ndev
, EDMR_EL
, EDMR
);
793 sh_eth_write(ndev
, 0, EDMR
);
796 sh_eth_write(ndev
, mdp
->cd
->fdr_value
, FDR
);
797 sh_eth_write(ndev
, 0, TFTR
);
799 /* Frame recv control */
800 sh_eth_write(ndev
, mdp
->cd
->rmcr_value
, RMCR
);
802 rx_int_var
= mdp
->rx_int_var
= DESC_I_RINT8
| DESC_I_RINT5
;
803 tx_int_var
= mdp
->tx_int_var
= DESC_I_TINT2
;
804 sh_eth_write(ndev
, rx_int_var
| tx_int_var
, TRSCER
);
807 sh_eth_write(ndev
, 0x800, BCULR
); /* Burst sycle set */
809 sh_eth_write(ndev
, mdp
->cd
->fcftr_value
, FCFTR
);
811 if (!mdp
->cd
->no_trimd
)
812 sh_eth_write(ndev
, 0, TRIMD
);
814 /* Recv frame limit set register */
815 sh_eth_write(ndev
, RFLR_VALUE
, RFLR
);
817 sh_eth_write(ndev
, sh_eth_read(ndev
, EESR
), EESR
);
818 sh_eth_write(ndev
, mdp
->cd
->eesipr_value
, EESIPR
);
820 /* PAUSE Prohibition */
821 val
= (sh_eth_read(ndev
, ECMR
) & ECMR_DM
) |
822 ECMR_ZPF
| (mdp
->duplex
? ECMR_DM
: 0) | ECMR_TE
| ECMR_RE
;
824 sh_eth_write(ndev
, val
, ECMR
);
826 if (mdp
->cd
->set_rate
)
827 mdp
->cd
->set_rate(ndev
);
829 /* E-MAC Status Register clear */
830 sh_eth_write(ndev
, mdp
->cd
->ecsr_value
, ECSR
);
832 /* E-MAC Interrupt Enable register */
833 sh_eth_write(ndev
, mdp
->cd
->ecsipr_value
, ECSIPR
);
835 /* Set MAC address */
836 update_mac_address(ndev
);
840 sh_eth_write(ndev
, APR_AP
, APR
);
842 sh_eth_write(ndev
, MPR_MP
, MPR
);
843 if (mdp
->cd
->tpauser
)
844 sh_eth_write(ndev
, TPAUSER_UNLIMITED
, TPAUSER
);
846 /* Setting the Rx mode will start the Rx process. */
847 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
849 netif_start_queue(ndev
);
854 /* free Tx skb function */
855 static int sh_eth_txfree(struct net_device
*ndev
)
857 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
858 struct sh_eth_txdesc
*txdesc
;
862 for (; mdp
->cur_tx
- mdp
->dirty_tx
> 0; mdp
->dirty_tx
++) {
863 entry
= mdp
->dirty_tx
% TX_RING_SIZE
;
864 txdesc
= &mdp
->tx_ring
[entry
];
865 if (txdesc
->status
& cpu_to_edmac(mdp
, TD_TACT
))
867 /* Free the original skb. */
868 if (mdp
->tx_skbuff
[entry
]) {
869 dev_kfree_skb_irq(mdp
->tx_skbuff
[entry
]);
870 mdp
->tx_skbuff
[entry
] = NULL
;
873 txdesc
->status
= cpu_to_edmac(mdp
, TD_TFP
);
874 if (entry
>= TX_RING_SIZE
- 1)
875 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TDLE
);
877 mdp
->stats
.tx_packets
++;
878 mdp
->stats
.tx_bytes
+= txdesc
->buffer_length
;
883 /* Packet receive function */
884 static int sh_eth_rx(struct net_device
*ndev
)
886 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
887 struct sh_eth_rxdesc
*rxdesc
;
889 int entry
= mdp
->cur_rx
% RX_RING_SIZE
;
890 int boguscnt
= (mdp
->dirty_rx
+ RX_RING_SIZE
) - mdp
->cur_rx
;
895 rxdesc
= &mdp
->rx_ring
[entry
];
896 while (!(rxdesc
->status
& cpu_to_edmac(mdp
, RD_RACT
))) {
897 desc_status
= edmac_to_cpu(mdp
, rxdesc
->status
);
898 pkt_len
= rxdesc
->frame_length
;
903 if (!(desc_status
& RDFEND
))
904 mdp
->stats
.rx_length_errors
++;
906 if (desc_status
& (RD_RFS1
| RD_RFS2
| RD_RFS3
| RD_RFS4
|
907 RD_RFS5
| RD_RFS6
| RD_RFS10
)) {
908 mdp
->stats
.rx_errors
++;
909 if (desc_status
& RD_RFS1
)
910 mdp
->stats
.rx_crc_errors
++;
911 if (desc_status
& RD_RFS2
)
912 mdp
->stats
.rx_frame_errors
++;
913 if (desc_status
& RD_RFS3
)
914 mdp
->stats
.rx_length_errors
++;
915 if (desc_status
& RD_RFS4
)
916 mdp
->stats
.rx_length_errors
++;
917 if (desc_status
& RD_RFS6
)
918 mdp
->stats
.rx_missed_errors
++;
919 if (desc_status
& RD_RFS10
)
920 mdp
->stats
.rx_over_errors
++;
922 if (!mdp
->cd
->hw_swap
)
924 phys_to_virt(ALIGN(rxdesc
->addr
, 4)),
926 skb
= mdp
->rx_skbuff
[entry
];
927 mdp
->rx_skbuff
[entry
] = NULL
;
929 skb_reserve(skb
, NET_IP_ALIGN
);
930 skb_put(skb
, pkt_len
);
931 skb
->protocol
= eth_type_trans(skb
, ndev
);
933 mdp
->stats
.rx_packets
++;
934 mdp
->stats
.rx_bytes
+= pkt_len
;
936 rxdesc
->status
|= cpu_to_edmac(mdp
, RD_RACT
);
937 entry
= (++mdp
->cur_rx
) % RX_RING_SIZE
;
938 rxdesc
= &mdp
->rx_ring
[entry
];
941 /* Refill the Rx ring buffers. */
942 for (; mdp
->cur_rx
- mdp
->dirty_rx
> 0; mdp
->dirty_rx
++) {
943 entry
= mdp
->dirty_rx
% RX_RING_SIZE
;
944 rxdesc
= &mdp
->rx_ring
[entry
];
945 /* The size of the buffer is 16 byte boundary. */
946 rxdesc
->buffer_length
= ALIGN(mdp
->rx_buf_sz
, 16);
948 if (mdp
->rx_skbuff
[entry
] == NULL
) {
949 skb
= dev_alloc_skb(mdp
->rx_buf_sz
);
950 mdp
->rx_skbuff
[entry
] = skb
;
952 break; /* Better luck next round. */
953 dma_map_single(&ndev
->dev
, skb
->tail
, mdp
->rx_buf_sz
,
956 sh_eth_set_receive_align(skb
);
958 skb_checksum_none_assert(skb
);
959 rxdesc
->addr
= virt_to_phys(PTR_ALIGN(skb
->data
, 4));
961 if (entry
>= RX_RING_SIZE
- 1)
963 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
| RD_RDEL
);
966 cpu_to_edmac(mdp
, RD_RACT
| RD_RFP
);
969 /* Restart Rx engine if stopped. */
970 /* If we don't need to check status, don't. -KDU */
971 if (!(sh_eth_read(ndev
, EDRRR
) & EDRRR_R
))
972 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
977 static void sh_eth_rcv_snd_disable(struct net_device
*ndev
)
979 /* disable tx and rx */
980 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) &
981 ~(ECMR_RE
| ECMR_TE
), ECMR
);
984 static void sh_eth_rcv_snd_enable(struct net_device
*ndev
)
986 /* enable tx and rx */
987 sh_eth_write(ndev
, sh_eth_read(ndev
, ECMR
) |
988 (ECMR_RE
| ECMR_TE
), ECMR
);
991 /* error control function */
992 static void sh_eth_error(struct net_device
*ndev
, int intr_status
)
994 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
999 if (intr_status
& EESR_ECI
) {
1000 felic_stat
= sh_eth_read(ndev
, ECSR
);
1001 sh_eth_write(ndev
, felic_stat
, ECSR
); /* clear int */
1002 if (felic_stat
& ECSR_ICD
)
1003 mdp
->stats
.tx_carrier_errors
++;
1004 if (felic_stat
& ECSR_LCHNG
) {
1006 if (mdp
->cd
->no_psr
|| mdp
->no_ether_link
) {
1007 if (mdp
->link
== PHY_DOWN
)
1010 link_stat
= PHY_ST_LINK
;
1012 link_stat
= (sh_eth_read(ndev
, PSR
));
1013 if (mdp
->ether_link_active_low
)
1014 link_stat
= ~link_stat
;
1016 if (!(link_stat
& PHY_ST_LINK
))
1017 sh_eth_rcv_snd_disable(ndev
);
1020 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) &
1021 ~DMAC_M_ECI
, EESIPR
);
1023 sh_eth_write(ndev
, sh_eth_read(ndev
, ECSR
),
1025 sh_eth_write(ndev
, sh_eth_read(ndev
, EESIPR
) |
1026 DMAC_M_ECI
, EESIPR
);
1027 /* enable tx and rx */
1028 sh_eth_rcv_snd_enable(ndev
);
1033 if (intr_status
& EESR_TWB
) {
1034 /* Write buck end. unused write back interrupt */
1035 if (intr_status
& EESR_TABT
) /* Transmit Abort int */
1036 mdp
->stats
.tx_aborted_errors
++;
1037 if (netif_msg_tx_err(mdp
))
1038 dev_err(&ndev
->dev
, "Transmit Abort\n");
1041 if (intr_status
& EESR_RABT
) {
1042 /* Receive Abort int */
1043 if (intr_status
& EESR_RFRMER
) {
1044 /* Receive Frame Overflow int */
1045 mdp
->stats
.rx_frame_errors
++;
1046 if (netif_msg_rx_err(mdp
))
1047 dev_err(&ndev
->dev
, "Receive Abort\n");
1051 if (intr_status
& EESR_TDE
) {
1052 /* Transmit Descriptor Empty int */
1053 mdp
->stats
.tx_fifo_errors
++;
1054 if (netif_msg_tx_err(mdp
))
1055 dev_err(&ndev
->dev
, "Transmit Descriptor Empty\n");
1058 if (intr_status
& EESR_TFE
) {
1059 /* FIFO under flow */
1060 mdp
->stats
.tx_fifo_errors
++;
1061 if (netif_msg_tx_err(mdp
))
1062 dev_err(&ndev
->dev
, "Transmit FIFO Under flow\n");
1065 if (intr_status
& EESR_RDE
) {
1066 /* Receive Descriptor Empty int */
1067 mdp
->stats
.rx_over_errors
++;
1069 if (sh_eth_read(ndev
, EDRRR
) ^ EDRRR_R
)
1070 sh_eth_write(ndev
, EDRRR_R
, EDRRR
);
1071 if (netif_msg_rx_err(mdp
))
1072 dev_err(&ndev
->dev
, "Receive Descriptor Empty\n");
1075 if (intr_status
& EESR_RFE
) {
1076 /* Receive FIFO Overflow int */
1077 mdp
->stats
.rx_fifo_errors
++;
1078 if (netif_msg_rx_err(mdp
))
1079 dev_err(&ndev
->dev
, "Receive FIFO Overflow\n");
1082 if (!mdp
->cd
->no_ade
&& (intr_status
& EESR_ADE
)) {
1084 mdp
->stats
.tx_fifo_errors
++;
1085 if (netif_msg_tx_err(mdp
))
1086 dev_err(&ndev
->dev
, "Address Error\n");
1089 mask
= EESR_TWB
| EESR_TABT
| EESR_ADE
| EESR_TDE
| EESR_TFE
;
1090 if (mdp
->cd
->no_ade
)
1092 if (intr_status
& mask
) {
1094 u32 edtrr
= sh_eth_read(ndev
, EDTRR
);
1096 dev_err(&ndev
->dev
, "TX error. status=%8.8x cur_tx=%8.8x ",
1097 intr_status
, mdp
->cur_tx
);
1098 dev_err(&ndev
->dev
, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1099 mdp
->dirty_tx
, (u32
) ndev
->state
, edtrr
);
1100 /* dirty buffer free */
1101 sh_eth_txfree(ndev
);
1104 if (edtrr
^ sh_eth_get_edtrr_trns(mdp
)) {
1106 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1109 netif_wake_queue(ndev
);
1113 static irqreturn_t
sh_eth_interrupt(int irq
, void *netdev
)
1115 struct net_device
*ndev
= netdev
;
1116 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1117 struct sh_eth_cpu_data
*cd
= mdp
->cd
;
1118 irqreturn_t ret
= IRQ_NONE
;
1119 u32 intr_status
= 0;
1121 spin_lock(&mdp
->lock
);
1123 /* Get interrpt stat */
1124 intr_status
= sh_eth_read(ndev
, EESR
);
1125 /* Clear interrupt */
1126 if (intr_status
& (EESR_FRC
| EESR_RMAF
| EESR_RRF
|
1127 EESR_RTLF
| EESR_RTSF
| EESR_PRE
| EESR_CERF
|
1128 cd
->tx_check
| cd
->eesr_err_check
)) {
1129 sh_eth_write(ndev
, intr_status
, EESR
);
1134 if (intr_status
& (EESR_FRC
| /* Frame recv*/
1135 EESR_RMAF
| /* Multi cast address recv*/
1136 EESR_RRF
| /* Bit frame recv */
1137 EESR_RTLF
| /* Long frame recv*/
1138 EESR_RTSF
| /* short frame recv */
1139 EESR_PRE
| /* PHY-LSI recv error */
1140 EESR_CERF
)){ /* recv frame CRC error */
1145 if (intr_status
& cd
->tx_check
) {
1146 sh_eth_txfree(ndev
);
1147 netif_wake_queue(ndev
);
1150 if (intr_status
& cd
->eesr_err_check
)
1151 sh_eth_error(ndev
, intr_status
);
1154 spin_unlock(&mdp
->lock
);
1159 static void sh_eth_timer(unsigned long data
)
1161 struct net_device
*ndev
= (struct net_device
*)data
;
1162 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1164 mod_timer(&mdp
->timer
, jiffies
+ (10 * HZ
));
1167 /* PHY state control function */
1168 static void sh_eth_adjust_link(struct net_device
*ndev
)
1170 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1171 struct phy_device
*phydev
= mdp
->phydev
;
1174 if (phydev
->link
!= PHY_DOWN
) {
1175 if (phydev
->duplex
!= mdp
->duplex
) {
1177 mdp
->duplex
= phydev
->duplex
;
1178 if (mdp
->cd
->set_duplex
)
1179 mdp
->cd
->set_duplex(ndev
);
1182 if (phydev
->speed
!= mdp
->speed
) {
1184 mdp
->speed
= phydev
->speed
;
1185 if (mdp
->cd
->set_rate
)
1186 mdp
->cd
->set_rate(ndev
);
1188 if (mdp
->link
== PHY_DOWN
) {
1190 (sh_eth_read(ndev
, ECMR
) & ~ECMR_TXF
), ECMR
);
1192 mdp
->link
= phydev
->link
;
1194 } else if (mdp
->link
) {
1196 mdp
->link
= PHY_DOWN
;
1201 if (new_state
&& netif_msg_link(mdp
))
1202 phy_print_status(phydev
);
1205 /* PHY init function */
1206 static int sh_eth_phy_init(struct net_device
*ndev
)
1208 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1209 char phy_id
[MII_BUS_ID_SIZE
+ 3];
1210 struct phy_device
*phydev
= NULL
;
1212 snprintf(phy_id
, sizeof(phy_id
), PHY_ID_FMT
,
1213 mdp
->mii_bus
->id
, mdp
->phy_id
);
1215 mdp
->link
= PHY_DOWN
;
1219 /* Try connect to PHY */
1220 phydev
= phy_connect(ndev
, phy_id
, sh_eth_adjust_link
,
1221 0, mdp
->phy_interface
);
1222 if (IS_ERR(phydev
)) {
1223 dev_err(&ndev
->dev
, "phy_connect failed\n");
1224 return PTR_ERR(phydev
);
1227 dev_info(&ndev
->dev
, "attached phy %i to driver %s\n",
1228 phydev
->addr
, phydev
->drv
->name
);
1230 mdp
->phydev
= phydev
;
1235 /* PHY control start function */
1236 static int sh_eth_phy_start(struct net_device
*ndev
)
1238 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1241 ret
= sh_eth_phy_init(ndev
);
1245 /* reset phy - this also wakes it from PDOWN */
1246 phy_write(mdp
->phydev
, MII_BMCR
, BMCR_RESET
);
1247 phy_start(mdp
->phydev
);
1252 static int sh_eth_get_settings(struct net_device
*ndev
,
1253 struct ethtool_cmd
*ecmd
)
1255 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1256 unsigned long flags
;
1259 spin_lock_irqsave(&mdp
->lock
, flags
);
1260 ret
= phy_ethtool_gset(mdp
->phydev
, ecmd
);
1261 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1266 static int sh_eth_set_settings(struct net_device
*ndev
,
1267 struct ethtool_cmd
*ecmd
)
1269 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1270 unsigned long flags
;
1273 spin_lock_irqsave(&mdp
->lock
, flags
);
1275 /* disable tx and rx */
1276 sh_eth_rcv_snd_disable(ndev
);
1278 ret
= phy_ethtool_sset(mdp
->phydev
, ecmd
);
1282 if (ecmd
->duplex
== DUPLEX_FULL
)
1287 if (mdp
->cd
->set_duplex
)
1288 mdp
->cd
->set_duplex(ndev
);
1293 /* enable tx and rx */
1294 sh_eth_rcv_snd_enable(ndev
);
1296 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1301 static int sh_eth_nway_reset(struct net_device
*ndev
)
1303 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1304 unsigned long flags
;
1307 spin_lock_irqsave(&mdp
->lock
, flags
);
1308 ret
= phy_start_aneg(mdp
->phydev
);
1309 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1314 static u32
sh_eth_get_msglevel(struct net_device
*ndev
)
1316 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1317 return mdp
->msg_enable
;
1320 static void sh_eth_set_msglevel(struct net_device
*ndev
, u32 value
)
1322 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1323 mdp
->msg_enable
= value
;
1326 static const char sh_eth_gstrings_stats
[][ETH_GSTRING_LEN
] = {
1327 "rx_current", "tx_current",
1328 "rx_dirty", "tx_dirty",
1330 #define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1332 static int sh_eth_get_sset_count(struct net_device
*netdev
, int sset
)
1336 return SH_ETH_STATS_LEN
;
1342 static void sh_eth_get_ethtool_stats(struct net_device
*ndev
,
1343 struct ethtool_stats
*stats
, u64
*data
)
1345 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1348 /* device-specific stats */
1349 data
[i
++] = mdp
->cur_rx
;
1350 data
[i
++] = mdp
->cur_tx
;
1351 data
[i
++] = mdp
->dirty_rx
;
1352 data
[i
++] = mdp
->dirty_tx
;
1355 static void sh_eth_get_strings(struct net_device
*ndev
, u32 stringset
, u8
*data
)
1357 switch (stringset
) {
1359 memcpy(data
, *sh_eth_gstrings_stats
,
1360 sizeof(sh_eth_gstrings_stats
));
1365 static struct ethtool_ops sh_eth_ethtool_ops
= {
1366 .get_settings
= sh_eth_get_settings
,
1367 .set_settings
= sh_eth_set_settings
,
1368 .nway_reset
= sh_eth_nway_reset
,
1369 .get_msglevel
= sh_eth_get_msglevel
,
1370 .set_msglevel
= sh_eth_set_msglevel
,
1371 .get_link
= ethtool_op_get_link
,
1372 .get_strings
= sh_eth_get_strings
,
1373 .get_ethtool_stats
= sh_eth_get_ethtool_stats
,
1374 .get_sset_count
= sh_eth_get_sset_count
,
1377 /* network device open function */
1378 static int sh_eth_open(struct net_device
*ndev
)
1381 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1383 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1385 ret
= request_irq(ndev
->irq
, sh_eth_interrupt
,
1386 #if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
1387 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1388 defined(CONFIG_CPU_SUBTYPE_SH7757)
1395 dev_err(&ndev
->dev
, "Can not assign IRQ number\n");
1399 /* Descriptor set */
1400 ret
= sh_eth_ring_init(ndev
);
1405 ret
= sh_eth_dev_init(ndev
);
1409 /* PHY control start*/
1410 ret
= sh_eth_phy_start(ndev
);
1414 /* Set the timer to check for link beat. */
1415 init_timer(&mdp
->timer
);
1416 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1417 setup_timer(&mdp
->timer
, sh_eth_timer
, (unsigned long)ndev
);
1422 free_irq(ndev
->irq
, ndev
);
1423 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1427 /* Timeout function */
1428 static void sh_eth_tx_timeout(struct net_device
*ndev
)
1430 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1431 struct sh_eth_rxdesc
*rxdesc
;
1434 netif_stop_queue(ndev
);
1436 if (netif_msg_timer(mdp
))
1437 dev_err(&ndev
->dev
, "%s: transmit timed out, status %8.8x,"
1438 " resetting...\n", ndev
->name
, (int)sh_eth_read(ndev
, EESR
));
1440 /* tx_errors count up */
1441 mdp
->stats
.tx_errors
++;
1444 del_timer_sync(&mdp
->timer
);
1446 /* Free all the skbuffs in the Rx queue. */
1447 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1448 rxdesc
= &mdp
->rx_ring
[i
];
1450 rxdesc
->addr
= 0xBADF00D0;
1451 if (mdp
->rx_skbuff
[i
])
1452 dev_kfree_skb(mdp
->rx_skbuff
[i
]);
1453 mdp
->rx_skbuff
[i
] = NULL
;
1455 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1456 if (mdp
->tx_skbuff
[i
])
1457 dev_kfree_skb(mdp
->tx_skbuff
[i
]);
1458 mdp
->tx_skbuff
[i
] = NULL
;
1462 sh_eth_dev_init(ndev
);
1465 mdp
->timer
.expires
= (jiffies
+ (24 * HZ
)) / 10;/* 2.4 sec. */
1466 add_timer(&mdp
->timer
);
1469 /* Packet transmit function */
1470 static int sh_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
1472 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1473 struct sh_eth_txdesc
*txdesc
;
1475 unsigned long flags
;
1477 spin_lock_irqsave(&mdp
->lock
, flags
);
1478 if ((mdp
->cur_tx
- mdp
->dirty_tx
) >= (TX_RING_SIZE
- 4)) {
1479 if (!sh_eth_txfree(ndev
)) {
1480 if (netif_msg_tx_queued(mdp
))
1481 dev_warn(&ndev
->dev
, "TxFD exhausted.\n");
1482 netif_stop_queue(ndev
);
1483 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1484 return NETDEV_TX_BUSY
;
1487 spin_unlock_irqrestore(&mdp
->lock
, flags
);
1489 entry
= mdp
->cur_tx
% TX_RING_SIZE
;
1490 mdp
->tx_skbuff
[entry
] = skb
;
1491 txdesc
= &mdp
->tx_ring
[entry
];
1492 txdesc
->addr
= virt_to_phys(skb
->data
);
1494 if (!mdp
->cd
->hw_swap
)
1495 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc
->addr
, 4)),
1498 __flush_purge_region(skb
->data
, skb
->len
);
1499 if (skb
->len
< ETHERSMALL
)
1500 txdesc
->buffer_length
= ETHERSMALL
;
1502 txdesc
->buffer_length
= skb
->len
;
1504 if (entry
>= TX_RING_SIZE
- 1)
1505 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
| TD_TDLE
);
1507 txdesc
->status
|= cpu_to_edmac(mdp
, TD_TACT
);
1511 if (!(sh_eth_read(ndev
, EDTRR
) & sh_eth_get_edtrr_trns(mdp
)))
1512 sh_eth_write(ndev
, sh_eth_get_edtrr_trns(mdp
), EDTRR
);
1514 return NETDEV_TX_OK
;
1517 /* device close function */
1518 static int sh_eth_close(struct net_device
*ndev
)
1520 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1523 netif_stop_queue(ndev
);
1525 /* Disable interrupts by clearing the interrupt mask. */
1526 sh_eth_write(ndev
, 0x0000, EESIPR
);
1528 /* Stop the chip's Tx and Rx processes. */
1529 sh_eth_write(ndev
, 0, EDTRR
);
1530 sh_eth_write(ndev
, 0, EDRRR
);
1532 /* PHY Disconnect */
1534 phy_stop(mdp
->phydev
);
1535 phy_disconnect(mdp
->phydev
);
1538 free_irq(ndev
->irq
, ndev
);
1540 del_timer_sync(&mdp
->timer
);
1542 /* Free all the skbuffs in the Rx queue. */
1543 sh_eth_ring_free(ndev
);
1545 /* free DMA buffer */
1546 ringsize
= sizeof(struct sh_eth_rxdesc
) * RX_RING_SIZE
;
1547 dma_free_coherent(NULL
, ringsize
, mdp
->rx_ring
, mdp
->rx_desc_dma
);
1549 /* free DMA buffer */
1550 ringsize
= sizeof(struct sh_eth_txdesc
) * TX_RING_SIZE
;
1551 dma_free_coherent(NULL
, ringsize
, mdp
->tx_ring
, mdp
->tx_desc_dma
);
1553 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1558 static struct net_device_stats
*sh_eth_get_stats(struct net_device
*ndev
)
1560 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1562 pm_runtime_get_sync(&mdp
->pdev
->dev
);
1564 mdp
->stats
.tx_dropped
+= sh_eth_read(ndev
, TROCR
);
1565 sh_eth_write(ndev
, 0, TROCR
); /* (write clear) */
1566 mdp
->stats
.collisions
+= sh_eth_read(ndev
, CDCR
);
1567 sh_eth_write(ndev
, 0, CDCR
); /* (write clear) */
1568 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, LCCR
);
1569 sh_eth_write(ndev
, 0, LCCR
); /* (write clear) */
1570 if (sh_eth_is_gether(mdp
)) {
1571 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CERCR
);
1572 sh_eth_write(ndev
, 0, CERCR
); /* (write clear) */
1573 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CEECR
);
1574 sh_eth_write(ndev
, 0, CEECR
); /* (write clear) */
1576 mdp
->stats
.tx_carrier_errors
+= sh_eth_read(ndev
, CNDCR
);
1577 sh_eth_write(ndev
, 0, CNDCR
); /* (write clear) */
1579 pm_runtime_put_sync(&mdp
->pdev
->dev
);
1584 /* ioctl to device funciotn*/
1585 static int sh_eth_do_ioctl(struct net_device
*ndev
, struct ifreq
*rq
,
1588 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1589 struct phy_device
*phydev
= mdp
->phydev
;
1591 if (!netif_running(ndev
))
1597 return phy_mii_ioctl(phydev
, rq
, cmd
);
1600 #if defined(SH_ETH_HAS_TSU)
1601 /* Multicast reception directions set */
1602 static void sh_eth_set_multicast_list(struct net_device
*ndev
)
1604 if (ndev
->flags
& IFF_PROMISC
) {
1605 /* Set promiscuous. */
1606 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_MCT
) |
1609 /* Normal, unicast/broadcast-only mode. */
1610 sh_eth_write(ndev
, (sh_eth_read(ndev
, ECMR
) & ~ECMR_PRM
) |
1614 #endif /* SH_ETH_HAS_TSU */
1616 /* SuperH's TSU register init function */
1617 static void sh_eth_tsu_init(struct sh_eth_private
*mdp
)
1619 sh_eth_tsu_write(mdp
, 0, TSU_FWEN0
); /* Disable forward(0->1) */
1620 sh_eth_tsu_write(mdp
, 0, TSU_FWEN1
); /* Disable forward(1->0) */
1621 sh_eth_tsu_write(mdp
, 0, TSU_FCM
); /* forward fifo 3k-3k */
1622 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL0
);
1623 sh_eth_tsu_write(mdp
, 0xc, TSU_BSYSL1
);
1624 sh_eth_tsu_write(mdp
, 0, TSU_PRISL0
);
1625 sh_eth_tsu_write(mdp
, 0, TSU_PRISL1
);
1626 sh_eth_tsu_write(mdp
, 0, TSU_FWSL0
);
1627 sh_eth_tsu_write(mdp
, 0, TSU_FWSL1
);
1628 sh_eth_tsu_write(mdp
, TSU_FWSLC_POSTENU
| TSU_FWSLC_POSTENL
, TSU_FWSLC
);
1629 if (sh_eth_is_gether(mdp
)) {
1630 sh_eth_tsu_write(mdp
, 0, TSU_QTAG0
); /* Disable QTAG(0->1) */
1631 sh_eth_tsu_write(mdp
, 0, TSU_QTAG1
); /* Disable QTAG(1->0) */
1633 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM0
); /* Disable QTAG(0->1) */
1634 sh_eth_tsu_write(mdp
, 0, TSU_QTAGM1
); /* Disable QTAG(1->0) */
1636 sh_eth_tsu_write(mdp
, 0, TSU_FWSR
); /* all interrupt status clear */
1637 sh_eth_tsu_write(mdp
, 0, TSU_FWINMK
); /* Disable all interrupt */
1638 sh_eth_tsu_write(mdp
, 0, TSU_TEN
); /* Disable all CAM entry */
1639 sh_eth_tsu_write(mdp
, 0, TSU_POST1
); /* Disable CAM entry [ 0- 7] */
1640 sh_eth_tsu_write(mdp
, 0, TSU_POST2
); /* Disable CAM entry [ 8-15] */
1641 sh_eth_tsu_write(mdp
, 0, TSU_POST3
); /* Disable CAM entry [16-23] */
1642 sh_eth_tsu_write(mdp
, 0, TSU_POST4
); /* Disable CAM entry [24-31] */
1645 /* MDIO bus release function */
1646 static int sh_mdio_release(struct net_device
*ndev
)
1648 struct mii_bus
*bus
= dev_get_drvdata(&ndev
->dev
);
1650 /* unregister mdio bus */
1651 mdiobus_unregister(bus
);
1653 /* remove mdio bus info from net_device */
1654 dev_set_drvdata(&ndev
->dev
, NULL
);
1656 /* free interrupts memory */
1659 /* free bitbang info */
1660 free_mdio_bitbang(bus
);
1665 /* MDIO bus init function */
1666 static int sh_mdio_init(struct net_device
*ndev
, int id
,
1667 struct sh_eth_plat_data
*pd
)
1670 struct bb_info
*bitbang
;
1671 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1673 /* create bit control struct for PHY */
1674 bitbang
= kzalloc(sizeof(struct bb_info
), GFP_KERNEL
);
1681 bitbang
->addr
= ndev
->base_addr
+ mdp
->reg_offset
[PIR
];
1682 bitbang
->set_gate
= pd
->set_mdio_gate
;
1683 bitbang
->mdi_msk
= 0x08;
1684 bitbang
->mdo_msk
= 0x04;
1685 bitbang
->mmd_msk
= 0x02;/* MMD */
1686 bitbang
->mdc_msk
= 0x01;
1687 bitbang
->ctrl
.ops
= &bb_ops
;
1689 /* MII controller setting */
1690 mdp
->mii_bus
= alloc_mdio_bitbang(&bitbang
->ctrl
);
1691 if (!mdp
->mii_bus
) {
1693 goto out_free_bitbang
;
1696 /* Hook up MII support for ethtool */
1697 mdp
->mii_bus
->name
= "sh_mii";
1698 mdp
->mii_bus
->parent
= &ndev
->dev
;
1699 snprintf(mdp
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", id
);
1702 mdp
->mii_bus
->irq
= kmalloc(sizeof(int)*PHY_MAX_ADDR
, GFP_KERNEL
);
1703 if (!mdp
->mii_bus
->irq
) {
1708 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1709 mdp
->mii_bus
->irq
[i
] = PHY_POLL
;
1711 /* regist mdio bus */
1712 ret
= mdiobus_register(mdp
->mii_bus
);
1716 dev_set_drvdata(&ndev
->dev
, mdp
->mii_bus
);
1721 kfree(mdp
->mii_bus
->irq
);
1724 free_mdio_bitbang(mdp
->mii_bus
);
1733 static const u16
*sh_eth_get_register_offset(int register_type
)
1735 const u16
*reg_offset
= NULL
;
1737 switch (register_type
) {
1738 case SH_ETH_REG_GIGABIT
:
1739 reg_offset
= sh_eth_offset_gigabit
;
1741 case SH_ETH_REG_FAST_SH4
:
1742 reg_offset
= sh_eth_offset_fast_sh4
;
1744 case SH_ETH_REG_FAST_SH3_SH2
:
1745 reg_offset
= sh_eth_offset_fast_sh3_sh2
;
1748 printk(KERN_ERR
"Unknown register type (%d)\n", register_type
);
1755 static const struct net_device_ops sh_eth_netdev_ops
= {
1756 .ndo_open
= sh_eth_open
,
1757 .ndo_stop
= sh_eth_close
,
1758 .ndo_start_xmit
= sh_eth_start_xmit
,
1759 .ndo_get_stats
= sh_eth_get_stats
,
1760 #if defined(SH_ETH_HAS_TSU)
1761 .ndo_set_multicast_list
= sh_eth_set_multicast_list
,
1763 .ndo_tx_timeout
= sh_eth_tx_timeout
,
1764 .ndo_do_ioctl
= sh_eth_do_ioctl
,
1765 .ndo_validate_addr
= eth_validate_addr
,
1766 .ndo_set_mac_address
= eth_mac_addr
,
1767 .ndo_change_mtu
= eth_change_mtu
,
1770 static int sh_eth_drv_probe(struct platform_device
*pdev
)
1773 struct resource
*res
;
1774 struct net_device
*ndev
= NULL
;
1775 struct sh_eth_private
*mdp
;
1776 struct sh_eth_plat_data
*pd
;
1779 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1780 if (unlikely(res
== NULL
)) {
1781 dev_err(&pdev
->dev
, "invalid resource\n");
1786 ndev
= alloc_etherdev(sizeof(struct sh_eth_private
));
1788 dev_err(&pdev
->dev
, "Could not allocate device.\n");
1793 /* The sh Ether-specific entries in the device structure. */
1794 ndev
->base_addr
= res
->start
;
1800 ret
= platform_get_irq(pdev
, 0);
1807 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1809 /* Fill in the fields of the device structure with ethernet values. */
1812 mdp
= netdev_priv(ndev
);
1813 spin_lock_init(&mdp
->lock
);
1815 pm_runtime_enable(&pdev
->dev
);
1816 pm_runtime_resume(&pdev
->dev
);
1818 pd
= (struct sh_eth_plat_data
*)(pdev
->dev
.platform_data
);
1820 mdp
->phy_id
= pd
->phy
;
1821 mdp
->phy_interface
= pd
->phy_interface
;
1823 mdp
->edmac_endian
= pd
->edmac_endian
;
1824 mdp
->no_ether_link
= pd
->no_ether_link
;
1825 mdp
->ether_link_active_low
= pd
->ether_link_active_low
;
1826 mdp
->reg_offset
= sh_eth_get_register_offset(pd
->register_type
);
1829 #if defined(SH_ETH_HAS_BOTH_MODULES)
1830 mdp
->cd
= sh_eth_get_cpu_data(mdp
);
1832 mdp
->cd
= &sh_eth_my_cpu_data
;
1834 sh_eth_set_default_cpu_data(mdp
->cd
);
1837 ndev
->netdev_ops
= &sh_eth_netdev_ops
;
1838 SET_ETHTOOL_OPS(ndev
, &sh_eth_ethtool_ops
);
1839 ndev
->watchdog_timeo
= TX_TIMEOUT
;
1841 /* debug message level */
1842 mdp
->msg_enable
= SH_ETH_DEF_MSG_ENABLE
;
1843 mdp
->post_rx
= POST_RX
>> (devno
<< 1);
1844 mdp
->post_fw
= POST_FW
>> (devno
<< 1);
1846 /* read and set MAC address */
1847 read_mac_address(ndev
, pd
->mac_addr
);
1849 /* First device only init */
1852 struct resource
*rtsu
;
1853 rtsu
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1855 dev_err(&pdev
->dev
, "Not found TSU resource\n");
1858 mdp
->tsu_addr
= ioremap(rtsu
->start
,
1859 resource_size(rtsu
));
1861 if (mdp
->cd
->chip_reset
)
1862 mdp
->cd
->chip_reset(ndev
);
1865 /* TSU init (Init only)*/
1866 sh_eth_tsu_init(mdp
);
1870 /* network device register */
1871 ret
= register_netdev(ndev
);
1876 ret
= sh_mdio_init(ndev
, pdev
->id
, pd
);
1878 goto out_unregister
;
1880 /* print device information */
1881 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1882 (u32
)ndev
->base_addr
, ndev
->dev_addr
, ndev
->irq
);
1884 platform_set_drvdata(pdev
, ndev
);
1889 unregister_netdev(ndev
);
1894 iounmap(mdp
->tsu_addr
);
1902 static int sh_eth_drv_remove(struct platform_device
*pdev
)
1904 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1905 struct sh_eth_private
*mdp
= netdev_priv(ndev
);
1907 iounmap(mdp
->tsu_addr
);
1908 sh_mdio_release(ndev
);
1909 unregister_netdev(ndev
);
1910 pm_runtime_disable(&pdev
->dev
);
1912 platform_set_drvdata(pdev
, NULL
);
1917 static int sh_eth_runtime_nop(struct device
*dev
)
1920 * Runtime PM callback shared between ->runtime_suspend()
1921 * and ->runtime_resume(). Simply returns success.
1923 * This driver re-initializes all registers after
1924 * pm_runtime_get_sync() anyway so there is no need
1925 * to save and restore registers here.
1930 static struct dev_pm_ops sh_eth_dev_pm_ops
= {
1931 .runtime_suspend
= sh_eth_runtime_nop
,
1932 .runtime_resume
= sh_eth_runtime_nop
,
1935 static struct platform_driver sh_eth_driver
= {
1936 .probe
= sh_eth_drv_probe
,
1937 .remove
= sh_eth_drv_remove
,
1940 .pm
= &sh_eth_dev_pm_ops
,
1944 static int __init
sh_eth_init(void)
1946 return platform_driver_register(&sh_eth_driver
);
1949 static void __exit
sh_eth_cleanup(void)
1951 platform_driver_unregister(&sh_eth_driver
);
1954 module_init(sh_eth_init
);
1955 module_exit(sh_eth_cleanup
);
1957 MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1958 MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1959 MODULE_LICENSE("GPL v2");