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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / net / tulip / tulip_core.c
blob82f87647207ecb4acdb4804ff2d95d914a392d9c
1 /* tulip_core.c: A DEC 21x4x-family ethernet driver for Linux.
2
3 Copyright 2000,2001 The Linux Kernel Team
4 Written/copyright 1994-2001 by Donald Becker.
5
6 This software may be used and distributed according to the terms
7 of the GNU General Public License, incorporated herein by reference.
8
9 Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
10 for more information on this driver.
11
12 Please submit bugs to http://bugzilla.kernel.org/ .
13 */
14
15 #define pr_fmt(fmt) "tulip: " fmt
16
17 #define DRV_NAME "tulip"
18 #ifdef CONFIG_TULIP_NAPI
19 #define DRV_VERSION "1.1.15-NAPI" /* Keep at least for test */
20 #else
21 #define DRV_VERSION "1.1.15"
22 #endif
23 #define DRV_RELDATE "Feb 27, 2007"
24
25
26 #include <linux/module.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include "tulip.h"
30 #include <linux/init.h>
31 #include <linux/etherdevice.h>
32 #include <linux/delay.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <asm/unaligned.h>
36 #include <asm/uaccess.h>
37
38 #ifdef CONFIG_SPARC
39 #include <asm/prom.h>
40 #endif
41
42 static char version[] __devinitdata =
43 "Linux Tulip driver version " DRV_VERSION " (" DRV_RELDATE ")\n";
44
45 /* A few user-configurable values. */
46
47 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
48 static unsigned int max_interrupt_work = 25;
49
50 #define MAX_UNITS 8
51 /* Used to pass the full-duplex flag, etc. */
52 static int full_duplex[MAX_UNITS];
53 static int options[MAX_UNITS];
54 static int mtu[MAX_UNITS]; /* Jumbo MTU for interfaces. */
55
56 /* The possible media types that can be set in options[] are: */
57 const char * const medianame[32] = {
58 "10baseT", "10base2", "AUI", "100baseTx",
59 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
60 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
61 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
62 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
63 "","","","", "","","","", "","","","Transceiver reset",
64 };
65
66 /* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */
67 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \
68 defined(CONFIG_SPARC) || defined(__ia64__) || \
69 defined(__sh__) || defined(__mips__)
70 static int rx_copybreak = 1518;
71 #else
72 static int rx_copybreak = 100;
73 #endif
74
75 /*
76 Set the bus performance register.
77 Typical: Set 16 longword cache alignment, no burst limit.
78 Cache alignment bits 15:14 Burst length 13:8
79 0000 No alignment 0x00000000 unlimited 0800 8 longwords
80 4000 8 longwords 0100 1 longword 1000 16 longwords
81 8000 16 longwords 0200 2 longwords 2000 32 longwords
82 C000 32 longwords 0400 4 longwords
83 Warning: many older 486 systems are broken and require setting 0x00A04800
84 8 longword cache alignment, 8 longword burst.
85 ToDo: Non-Intel setting could be better.
86 */
87
88 #if defined(__alpha__) || defined(__ia64__)
89 static int csr0 = 0x01A00000 | 0xE000;
90 #elif defined(__i386__) || defined(__powerpc__) || defined(__x86_64__)
91 static int csr0 = 0x01A00000 | 0x8000;
92 #elif defined(CONFIG_SPARC) || defined(__hppa__)
93 /* The UltraSparc PCI controllers will disconnect at every 64-byte
94 * crossing anyways so it makes no sense to tell Tulip to burst
95 * any more than that.
96 */
97 static int csr0 = 0x01A00000 | 0x9000;
98 #elif defined(__arm__) || defined(__sh__)
99 static int csr0 = 0x01A00000 | 0x4800;
100 #elif defined(__mips__)
101 static int csr0 = 0x00200000 | 0x4000;
102 #else
103 #warning Processor architecture undefined!
104 static int csr0 = 0x00A00000 | 0x4800;
105 #endif
106
107 /* Operational parameters that usually are not changed. */
108 /* Time in jiffies before concluding the transmitter is hung. */
109 #define TX_TIMEOUT (4*HZ)
110
111
112 MODULE_AUTHOR("The Linux Kernel Team");
113 MODULE_DESCRIPTION("Digital 21*4* Tulip ethernet driver");
114 MODULE_LICENSE("GPL");
115 MODULE_VERSION(DRV_VERSION);
116 module_param(tulip_debug, int, 0);
117 module_param(max_interrupt_work, int, 0);
118 module_param(rx_copybreak, int, 0);
119 module_param(csr0, int, 0);
120 module_param_array(options, int, NULL, 0);
121 module_param_array(full_duplex, int, NULL, 0);
122
123 #ifdef TULIP_DEBUG
124 int tulip_debug = TULIP_DEBUG;
125 #else
126 int tulip_debug = 1;
127 #endif
128
129 static void tulip_timer(unsigned long data)
130 {
131 struct net_device *dev = (struct net_device *)data;
132 struct tulip_private *tp = netdev_priv(dev);
133
134 if (netif_running(dev))
135 schedule_work(&tp->media_work);
136 }
137
138 /*
139 * This table use during operation for capabilities and media timer.
140 *
141 * It is indexed via the values in 'enum chips'
142 */
143
144 struct tulip_chip_table tulip_tbl[] = {
145 { }, /* placeholder for array, slot unused currently */
146 { }, /* placeholder for array, slot unused currently */
147
148 /* DC21140 */
149 { "Digital DS21140 Tulip", 128, 0x0001ebef,
150 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_PCI_MWI, tulip_timer,
151 tulip_media_task },
152
153 /* DC21142, DC21143 */
154 { "Digital DS21142/43 Tulip", 128, 0x0801fbff,
155 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI | HAS_NWAY
156 | HAS_INTR_MITIGATION | HAS_PCI_MWI, tulip_timer, t21142_media_task },
157
158 /* LC82C168 */
159 { "Lite-On 82c168 PNIC", 256, 0x0001fbef,
160 HAS_MII | HAS_PNICNWAY, pnic_timer, },
161
162 /* MX98713 */
163 { "Macronix 98713 PMAC", 128, 0x0001ebef,
164 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
165
166 /* MX98715 */
167 { "Macronix 98715 PMAC", 256, 0x0001ebef,
168 HAS_MEDIA_TABLE, mxic_timer, },
169
170 /* MX98725 */
171 { "Macronix 98725 PMAC", 256, 0x0001ebef,
172 HAS_MEDIA_TABLE, mxic_timer, },
173
174 /* AX88140 */
175 { "ASIX AX88140", 128, 0x0001fbff,
176 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
177 | IS_ASIX, tulip_timer, tulip_media_task },
178
179 /* PNIC2 */
180 { "Lite-On PNIC-II", 256, 0x0801fbff,
181 HAS_MII | HAS_NWAY | HAS_8023X | HAS_PCI_MWI, pnic2_timer, },
182
183 /* COMET */
184 { "ADMtek Comet", 256, 0x0001abef,
185 HAS_MII | MC_HASH_ONLY | COMET_MAC_ADDR, comet_timer, },
186
187 /* COMPEX9881 */
188 { "Compex 9881 PMAC", 128, 0x0001ebef,
189 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM, mxic_timer, },
190
191 /* I21145 */
192 { "Intel DS21145 Tulip", 128, 0x0801fbff,
193 HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII | HAS_ACPI
194 | HAS_NWAY | HAS_PCI_MWI, tulip_timer, tulip_media_task },
195
196 /* DM910X */
197 #ifdef CONFIG_TULIP_DM910X
198 { "Davicom DM9102/DM9102A", 128, 0x0001ebef,
199 HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | HAS_ACPI,
200 tulip_timer, tulip_media_task },
201 #else
202 { NULL },
203 #endif
204
205 /* RS7112 */
206 { "Conexant LANfinity", 256, 0x0001ebef,
207 HAS_MII | HAS_ACPI, tulip_timer, tulip_media_task },
208
209 };
210
211
212 static DEFINE_PCI_DEVICE_TABLE(tulip_pci_tbl) = {
213 { 0x1011, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21140 },
214 { 0x1011, 0x0019, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DC21143 },
215 { 0x11AD, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, LC82C168 },
216 { 0x10d9, 0x0512, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98713 },
217 { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
218 /* { 0x10d9, 0x0531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98725 },*/
219 { 0x125B, 0x1400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AX88140 },
220 { 0x11AD, 0xc115, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PNIC2 },
221 { 0x1317, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
222 { 0x1317, 0x0985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
223 { 0x1317, 0x1985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
224 { 0x1317, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
225 { 0x13D1, 0xAB02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
226 { 0x13D1, 0xAB03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
227 { 0x13D1, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
228 { 0x104A, 0x0981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
229 { 0x104A, 0x2774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
230 { 0x1259, 0xa120, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
231 { 0x11F6, 0x9881, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMPEX9881 },
232 { 0x8086, 0x0039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, I21145 },
233 #ifdef CONFIG_TULIP_DM910X
234 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
235 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DM910X },
236 #endif
237 { 0x1113, 0x1216, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
238 { 0x1113, 0x1217, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MX98715 },
239 { 0x1113, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
240 { 0x1186, 0x1541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
241 { 0x1186, 0x1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
242 { 0x1186, 0x1591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
243 { 0x14f1, 0x1803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CONEXANT },
244 { 0x1626, 0x8410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
245 { 0x1737, 0xAB09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
246 { 0x1737, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
247 { 0x17B3, 0xAB08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
248 { 0x10b7, 0x9300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* 3Com 3CSOHO100B-TX */
249 { 0x14ea, 0xab08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Planex FNW-3602-TX */
250 { 0x1414, 0x0001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET }, /* Microsoft MN-120 */
251 { 0x1414, 0x0002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, COMET },
252 { } /* terminate list */
253 };
254 MODULE_DEVICE_TABLE(pci, tulip_pci_tbl);
255
256
257 /* A full-duplex map for media types. */
258 const char tulip_media_cap[32] =
259 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 28,31,0,0, };
260
261 static void tulip_tx_timeout(struct net_device *dev);
262 static void tulip_init_ring(struct net_device *dev);
263 static void tulip_free_ring(struct net_device *dev);
264 static netdev_tx_t tulip_start_xmit(struct sk_buff *skb,
265 struct net_device *dev);
266 static int tulip_open(struct net_device *dev);
267 static int tulip_close(struct net_device *dev);
268 static void tulip_up(struct net_device *dev);
269 static void tulip_down(struct net_device *dev);
270 static struct net_device_stats *tulip_get_stats(struct net_device *dev);
271 static int private_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
272 static void set_rx_mode(struct net_device *dev);
273 static void tulip_set_wolopts(struct pci_dev *pdev, u32 wolopts);
274 #ifdef CONFIG_NET_POLL_CONTROLLER
275 static void poll_tulip(struct net_device *dev);
276 #endif
277
278 static void tulip_set_power_state (struct tulip_private *tp,
279 int sleep, int snooze)
280 {
281 if (tp->flags & HAS_ACPI) {
282 u32 tmp, newtmp;
283 pci_read_config_dword (tp->pdev, CFDD, &tmp);
284 newtmp = tmp & ~(CFDD_Sleep | CFDD_Snooze);
285 if (sleep)
286 newtmp |= CFDD_Sleep;
287 else if (snooze)
288 newtmp |= CFDD_Snooze;
289 if (tmp != newtmp)
290 pci_write_config_dword (tp->pdev, CFDD, newtmp);
291 }
292
293 }
294
295
296 static void tulip_up(struct net_device *dev)
297 {
298 struct tulip_private *tp = netdev_priv(dev);
299 void __iomem *ioaddr = tp->base_addr;
300 int next_tick = 3*HZ;
301 u32 reg;
302 int i;
303
304 #ifdef CONFIG_TULIP_NAPI
305 napi_enable(&tp->napi);
306 #endif
307
308 /* Wake the chip from sleep/snooze mode. */
309 tulip_set_power_state (tp, 0, 0);
310
311 /* Disable all WOL events */
312 pci_enable_wake(tp->pdev, PCI_D3hot, 0);
313 pci_enable_wake(tp->pdev, PCI_D3cold, 0);
314 tulip_set_wolopts(tp->pdev, 0);
315
316 /* On some chip revs we must set the MII/SYM port before the reset!? */
317 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii))
318 iowrite32(0x00040000, ioaddr + CSR6);
319
320 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
321 iowrite32(0x00000001, ioaddr + CSR0);
322 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
323 udelay(100);
324
325 /* Deassert reset.
326 Wait the specified 50 PCI cycles after a reset by initializing
327 Tx and Rx queues and the address filter list. */
328 iowrite32(tp->csr0, ioaddr + CSR0);
329 pci_read_config_dword(tp->pdev, PCI_COMMAND, &reg); /* flush write */
330 udelay(100);
331
332 if (tulip_debug > 1)
333 netdev_dbg(dev, "tulip_up(), irq==%d\n", dev->irq);
334
335 iowrite32(tp->rx_ring_dma, ioaddr + CSR3);
336 iowrite32(tp->tx_ring_dma, ioaddr + CSR4);
337 tp->cur_rx = tp->cur_tx = 0;
338 tp->dirty_rx = tp->dirty_tx = 0;
339
340 if (tp->flags & MC_HASH_ONLY) {
341 u32 addr_low = get_unaligned_le32(dev->dev_addr);
342 u32 addr_high = get_unaligned_le16(dev->dev_addr + 4);
343 if (tp->chip_id == AX88140) {
344 iowrite32(0, ioaddr + CSR13);
345 iowrite32(addr_low, ioaddr + CSR14);
346 iowrite32(1, ioaddr + CSR13);
347 iowrite32(addr_high, ioaddr + CSR14);
348 } else if (tp->flags & COMET_MAC_ADDR) {
349 iowrite32(addr_low, ioaddr + 0xA4);
350 iowrite32(addr_high, ioaddr + 0xA8);
351 iowrite32(0, ioaddr + CSR27);
352 iowrite32(0, ioaddr + CSR28);
353 }
354 } else {
355 /* This is set_rx_mode(), but without starting the transmitter. */
356 u16 *eaddrs = (u16 *)dev->dev_addr;
357 u16 *setup_frm = &tp->setup_frame[15*6];
358 dma_addr_t mapping;
359
360 /* 21140 bug: you must add the broadcast address. */
361 memset(tp->setup_frame, 0xff, sizeof(tp->setup_frame));
362 /* Fill the final entry of the table with our physical address. */
363 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
364 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
365 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
366
367 mapping = pci_map_single(tp->pdev, tp->setup_frame,
368 sizeof(tp->setup_frame),
369 PCI_DMA_TODEVICE);
370 tp->tx_buffers[tp->cur_tx].skb = NULL;
371 tp->tx_buffers[tp->cur_tx].mapping = mapping;
372
373 /* Put the setup frame on the Tx list. */
374 tp->tx_ring[tp->cur_tx].length = cpu_to_le32(0x08000000 | 192);
375 tp->tx_ring[tp->cur_tx].buffer1 = cpu_to_le32(mapping);
376 tp->tx_ring[tp->cur_tx].status = cpu_to_le32(DescOwned);
377
378 tp->cur_tx++;
379 }
380
381 tp->saved_if_port = dev->if_port;
382 if (dev->if_port == 0)
383 dev->if_port = tp->default_port;
384
385 /* Allow selecting a default media. */
386 i = 0;
387 if (tp->mtable == NULL)
388 goto media_picked;
389 if (dev->if_port) {
390 int looking_for = tulip_media_cap[dev->if_port] & MediaIsMII ? 11 :
391 (dev->if_port == 12 ? 0 : dev->if_port);
392 for (i = 0; i < tp->mtable->leafcount; i++)
393 if (tp->mtable->mleaf[i].media == looking_for) {
394 dev_info(&dev->dev,
395 "Using user-specified media %s\n",
396 medianame[dev->if_port]);
397 goto media_picked;
398 }
399 }
400 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
401 int looking_for = tp->mtable->defaultmedia & MEDIA_MASK;
402 for (i = 0; i < tp->mtable->leafcount; i++)
403 if (tp->mtable->mleaf[i].media == looking_for) {
404 dev_info(&dev->dev,
405 "Using EEPROM-set media %s\n",
406 medianame[looking_for]);
407 goto media_picked;
408 }
409 }
410 /* Start sensing first non-full-duplex media. */
411 for (i = tp->mtable->leafcount - 1;
412 (tulip_media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
413 ;
414 media_picked:
415
416 tp->csr6 = 0;
417 tp->cur_index = i;
418 tp->nwayset = 0;
419
420 if (dev->if_port) {
421 if (tp->chip_id == DC21143 &&
422 (tulip_media_cap[dev->if_port] & MediaIsMII)) {
423 /* We must reset the media CSRs when we force-select MII mode. */
424 iowrite32(0x0000, ioaddr + CSR13);
425 iowrite32(0x0000, ioaddr + CSR14);
426 iowrite32(0x0008, ioaddr + CSR15);
427 }
428 tulip_select_media(dev, 1);
429 } else if (tp->chip_id == DC21142) {
430 if (tp->mii_cnt) {
431 tulip_select_media(dev, 1);
432 if (tulip_debug > 1)
433 dev_info(&dev->dev,
434 "Using MII transceiver %d, status %04x\n",
435 tp->phys[0],
436 tulip_mdio_read(dev, tp->phys[0], 1));
437 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
438 tp->csr6 = csr6_mask_hdcap;
439 dev->if_port = 11;
440 iowrite32(0x0000, ioaddr + CSR13);
441 iowrite32(0x0000, ioaddr + CSR14);
442 } else
443 t21142_start_nway(dev);
444 } else if (tp->chip_id == PNIC2) {
445 /* for initial startup advertise 10/100 Full and Half */
446 tp->sym_advertise = 0x01E0;
447 /* enable autonegotiate end interrupt */
448 iowrite32(ioread32(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5);
449 iowrite32(ioread32(ioaddr+CSR7)| 0x00008010, ioaddr + CSR7);
450 pnic2_start_nway(dev);
451 } else if (tp->chip_id == LC82C168 && ! tp->medialock) {
452 if (tp->mii_cnt) {
453 dev->if_port = 11;
454 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
455 iowrite32(0x0001, ioaddr + CSR15);
456 } else if (ioread32(ioaddr + CSR5) & TPLnkPass)
457 pnic_do_nway(dev);
458 else {
459 /* Start with 10mbps to do autonegotiation. */
460 iowrite32(0x32, ioaddr + CSR12);
461 tp->csr6 = 0x00420000;
462 iowrite32(0x0001B078, ioaddr + 0xB8);
463 iowrite32(0x0201B078, ioaddr + 0xB8);
464 next_tick = 1*HZ;
465 }
466 } else if ((tp->chip_id == MX98713 || tp->chip_id == COMPEX9881) &&
467 ! tp->medialock) {
468 dev->if_port = 0;
469 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
470 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
471 } else if (tp->chip_id == MX98715 || tp->chip_id == MX98725) {
472 /* Provided by BOLO, Macronix - 12/10/1998. */
473 dev->if_port = 0;
474 tp->csr6 = 0x01a80200;
475 iowrite32(0x0f370000 | ioread16(ioaddr + 0x80), ioaddr + 0x80);
476 iowrite32(0x11000 | ioread16(ioaddr + 0xa0), ioaddr + 0xa0);
477 } else if (tp->chip_id == COMET || tp->chip_id == CONEXANT) {
478 /* Enable automatic Tx underrun recovery. */
479 iowrite32(ioread32(ioaddr + 0x88) | 1, ioaddr + 0x88);
480 dev->if_port = tp->mii_cnt ? 11 : 0;
481 tp->csr6 = 0x00040000;
482 } else if (tp->chip_id == AX88140) {
483 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
484 } else
485 tulip_select_media(dev, 1);
486
487 /* Start the chip's Tx to process setup frame. */
488 tulip_stop_rxtx(tp);
489 barrier();
490 udelay(5);
491 iowrite32(tp->csr6 | TxOn, ioaddr + CSR6);
492
493 /* Enable interrupts by setting the interrupt mask. */
494 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5);
495 iowrite32(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR7);
496 tulip_start_rxtx(tp);
497 iowrite32(0, ioaddr + CSR2); /* Rx poll demand */
498
499 if (tulip_debug > 2) {
500 netdev_dbg(dev, "Done tulip_up(), CSR0 %08x, CSR5 %08x CSR6 %08x\n",
501 ioread32(ioaddr + CSR0),
502 ioread32(ioaddr + CSR5),
503 ioread32(ioaddr + CSR6));
504 }
505
506 /* Set the timer to switch to check for link beat and perhaps switch
507 to an alternate media type. */
508 tp->timer.expires = RUN_AT(next_tick);
509 add_timer(&tp->timer);
510 #ifdef CONFIG_TULIP_NAPI
511 init_timer(&tp->oom_timer);
512 tp->oom_timer.data = (unsigned long)dev;
513 tp->oom_timer.function = oom_timer;
514 #endif
515 }
516
517 static int
518 tulip_open(struct net_device *dev)
519 {
520 int retval;
521
522 tulip_init_ring (dev);
523
524 retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev);
525 if (retval)
526 goto free_ring;
527
528 tulip_up (dev);
529
530 netif_start_queue (dev);
531
532 return 0;
533
534 free_ring:
535 tulip_free_ring (dev);
536 return retval;
537 }
538
539
540 static void tulip_tx_timeout(struct net_device *dev)
541 {
542 struct tulip_private *tp = netdev_priv(dev);
543 void __iomem *ioaddr = tp->base_addr;
544 unsigned long flags;
545
546 spin_lock_irqsave (&tp->lock, flags);
547
548 if (tulip_media_cap[dev->if_port] & MediaIsMII) {
549 /* Do nothing -- the media monitor should handle this. */
550 if (tulip_debug > 1)
551 dev_warn(&dev->dev,
552 "Transmit timeout using MII device\n");
553 } else if (tp->chip_id == DC21140 || tp->chip_id == DC21142 ||
554 tp->chip_id == MX98713 || tp->chip_id == COMPEX9881 ||
555 tp->chip_id == DM910X) {
556 dev_warn(&dev->dev,
557 "21140 transmit timed out, status %08x, SIA %08x %08x %08x %08x, resetting...\n",
558 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12),
559 ioread32(ioaddr + CSR13), ioread32(ioaddr + CSR14),
560 ioread32(ioaddr + CSR15));
561 tp->timeout_recovery = 1;
562 schedule_work(&tp->media_work);
563 goto out_unlock;
564 } else if (tp->chip_id == PNIC2) {
565 dev_warn(&dev->dev,
566 "PNIC2 transmit timed out, status %08x, CSR6/7 %08x / %08x CSR12 %08x, resetting...\n",
567 (int)ioread32(ioaddr + CSR5),
568 (int)ioread32(ioaddr + CSR6),
569 (int)ioread32(ioaddr + CSR7),
570 (int)ioread32(ioaddr + CSR12));
571 } else {
572 dev_warn(&dev->dev,
573 "Transmit timed out, status %08x, CSR12 %08x, resetting...\n",
574 ioread32(ioaddr + CSR5), ioread32(ioaddr + CSR12));
575 dev->if_port = 0;
576 }
577
578 #if defined(way_too_many_messages)
579 if (tulip_debug > 3) {
580 int i;
581 for (i = 0; i < RX_RING_SIZE; i++) {
582 u8 *buf = (u8 *)(tp->rx_ring[i].buffer1);
583 int j;
584 printk(KERN_DEBUG
585 "%2d: %08x %08x %08x %08x %02x %02x %02x\n",
586 i,
587 (unsigned int)tp->rx_ring[i].status,
588 (unsigned int)tp->rx_ring[i].length,
589 (unsigned int)tp->rx_ring[i].buffer1,
590 (unsigned int)tp->rx_ring[i].buffer2,
591 buf[0], buf[1], buf[2]);
592 for (j = 0; buf[j] != 0xee && j < 1600; j++)
593 if (j < 100)
594 pr_cont(" %02x", buf[j]);
595 pr_cont(" j=%d\n", j);
596 }
597 printk(KERN_DEBUG " Rx ring %p: ", tp->rx_ring);
598 for (i = 0; i < RX_RING_SIZE; i++)
599 pr_cont(" %08x", (unsigned int)tp->rx_ring[i].status);
600 printk(KERN_DEBUG " Tx ring %p: ", tp->tx_ring);
601 for (i = 0; i < TX_RING_SIZE; i++)
602 pr_cont(" %08x", (unsigned int)tp->tx_ring[i].status);
603 pr_cont("\n");
604 }
605 #endif
606
607 tulip_tx_timeout_complete(tp, ioaddr);
608
609 out_unlock:
610 spin_unlock_irqrestore (&tp->lock, flags);
611 dev->trans_start = jiffies; /* prevent tx timeout */
612 netif_wake_queue (dev);
613 }
614
615
616 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
617 static void tulip_init_ring(struct net_device *dev)
618 {
619 struct tulip_private *tp = netdev_priv(dev);
620 int i;
621
622 tp->susp_rx = 0;
623 tp->ttimer = 0;
624 tp->nir = 0;
625
626 for (i = 0; i < RX_RING_SIZE; i++) {
627 tp->rx_ring[i].status = 0x00000000;
628 tp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ);
629 tp->rx_ring[i].buffer2 = cpu_to_le32(tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * (i + 1));
630 tp->rx_buffers[i].skb = NULL;
631 tp->rx_buffers[i].mapping = 0;
632 }
633 /* Mark the last entry as wrapping the ring. */
634 tp->rx_ring[i-1].length = cpu_to_le32(PKT_BUF_SZ | DESC_RING_WRAP);
635 tp->rx_ring[i-1].buffer2 = cpu_to_le32(tp->rx_ring_dma);
636
637 for (i = 0; i < RX_RING_SIZE; i++) {
638 dma_addr_t mapping;
639
640 /* Note the receive buffer must be longword aligned.
641 dev_alloc_skb() provides 16 byte alignment. But do *not*
642 use skb_reserve() to align the IP header! */
643 struct sk_buff *skb = dev_alloc_skb(PKT_BUF_SZ);
644 tp->rx_buffers[i].skb = skb;
645 if (skb == NULL)
646 break;
647 mapping = pci_map_single(tp->pdev, skb->data,
648 PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
649 tp->rx_buffers[i].mapping = mapping;
650 skb->dev = dev; /* Mark as being used by this device. */
651 tp->rx_ring[i].status = cpu_to_le32(DescOwned); /* Owned by Tulip chip */
652 tp->rx_ring[i].buffer1 = cpu_to_le32(mapping);
653 }
654 tp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
655
656 /* The Tx buffer descriptor is filled in as needed, but we
657 do need to clear the ownership bit. */
658 for (i = 0; i < TX_RING_SIZE; i++) {
659 tp->tx_buffers[i].skb = NULL;
660 tp->tx_buffers[i].mapping = 0;
661 tp->tx_ring[i].status = 0x00000000;
662 tp->tx_ring[i].buffer2 = cpu_to_le32(tp->tx_ring_dma + sizeof(struct tulip_tx_desc) * (i + 1));
663 }
664 tp->tx_ring[i-1].buffer2 = cpu_to_le32(tp->tx_ring_dma);
665 }
666
667 static netdev_tx_t
668 tulip_start_xmit(struct sk_buff *skb, struct net_device *dev)
669 {
670 struct tulip_private *tp = netdev_priv(dev);
671 int entry;
672 u32 flag;
673 dma_addr_t mapping;
674 unsigned long flags;
675
676 spin_lock_irqsave(&tp->lock, flags);
677
678 /* Calculate the next Tx descriptor entry. */
679 entry = tp->cur_tx % TX_RING_SIZE;
680
681 tp->tx_buffers[entry].skb = skb;
682 mapping = pci_map_single(tp->pdev, skb->data,
683 skb->len, PCI_DMA_TODEVICE);
684 tp->tx_buffers[entry].mapping = mapping;
685 tp->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
686
687 if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE/2) {/* Typical path */
688 flag = 0x60000000; /* No interrupt */
689 } else if (tp->cur_tx - tp->dirty_tx == TX_RING_SIZE/2) {
690 flag = 0xe0000000; /* Tx-done intr. */
691 } else if (tp->cur_tx - tp->dirty_tx < TX_RING_SIZE - 2) {
692 flag = 0x60000000; /* No Tx-done intr. */
693 } else { /* Leave room for set_rx_mode() to fill entries. */
694 flag = 0xe0000000; /* Tx-done intr. */
695 netif_stop_queue(dev);
696 }
697 if (entry == TX_RING_SIZE-1)
698 flag = 0xe0000000 | DESC_RING_WRAP;
699
700 tp->tx_ring[entry].length = cpu_to_le32(skb->len | flag);
701 /* if we were using Transmit Automatic Polling, we would need a
702 * wmb() here. */
703 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
704 wmb();
705
706 tp->cur_tx++;
707
708 /* Trigger an immediate transmit demand. */
709 iowrite32(0, tp->base_addr + CSR1);
710
711 spin_unlock_irqrestore(&tp->lock, flags);
712
713 return NETDEV_TX_OK;
714 }
715
716 static void tulip_clean_tx_ring(struct tulip_private *tp)
717 {
718 unsigned int dirty_tx;
719
720 for (dirty_tx = tp->dirty_tx ; tp->cur_tx - dirty_tx > 0;
721 dirty_tx++) {
722 int entry = dirty_tx % TX_RING_SIZE;
723 int status = le32_to_cpu(tp->tx_ring[entry].status);
724
725 if (status < 0) {
726 tp->dev->stats.tx_errors++; /* It wasn't Txed */
727 tp->tx_ring[entry].status = 0;
728 }
729
730 /* Check for Tx filter setup frames. */
731 if (tp->tx_buffers[entry].skb == NULL) {
732 /* test because dummy frames not mapped */
733 if (tp->tx_buffers[entry].mapping)
734 pci_unmap_single(tp->pdev,
735 tp->tx_buffers[entry].mapping,
736 sizeof(tp->setup_frame),
737 PCI_DMA_TODEVICE);
738 continue;
739 }
740
741 pci_unmap_single(tp->pdev, tp->tx_buffers[entry].mapping,
742 tp->tx_buffers[entry].skb->len,
743 PCI_DMA_TODEVICE);
744
745 /* Free the original skb. */
746 dev_kfree_skb_irq(tp->tx_buffers[entry].skb);
747 tp->tx_buffers[entry].skb = NULL;
748 tp->tx_buffers[entry].mapping = 0;
749 }
750 }
751
752 static void tulip_down (struct net_device *dev)
753 {
754 struct tulip_private *tp = netdev_priv(dev);
755 void __iomem *ioaddr = tp->base_addr;
756 unsigned long flags;
757
758 cancel_work_sync(&tp->media_work);
759
760 #ifdef CONFIG_TULIP_NAPI
761 napi_disable(&tp->napi);
762 #endif
763
764 del_timer_sync (&tp->timer);
765 #ifdef CONFIG_TULIP_NAPI
766 del_timer_sync (&tp->oom_timer);
767 #endif
768 spin_lock_irqsave (&tp->lock, flags);
769
770 /* Disable interrupts by clearing the interrupt mask. */
771 iowrite32 (0x00000000, ioaddr + CSR7);
772
773 /* Stop the Tx and Rx processes. */
774 tulip_stop_rxtx(tp);
775
776 /* prepare receive buffers */
777 tulip_refill_rx(dev);
778
779 /* release any unconsumed transmit buffers */
780 tulip_clean_tx_ring(tp);
781
782 if (ioread32(ioaddr + CSR6) != 0xffffffff)
783 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
784
785 spin_unlock_irqrestore (&tp->lock, flags);
786
787 init_timer(&tp->timer);
788 tp->timer.data = (unsigned long)dev;
789 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
790
791 dev->if_port = tp->saved_if_port;
792
793 /* Leave the driver in snooze, not sleep, mode. */
794 tulip_set_power_state (tp, 0, 1);
795 }
796
797 static void tulip_free_ring (struct net_device *dev)
798 {
799 struct tulip_private *tp = netdev_priv(dev);
800 int i;
801
802 /* Free all the skbuffs in the Rx queue. */
803 for (i = 0; i < RX_RING_SIZE; i++) {
804 struct sk_buff *skb = tp->rx_buffers[i].skb;
805 dma_addr_t mapping = tp->rx_buffers[i].mapping;
806
807 tp->rx_buffers[i].skb = NULL;
808 tp->rx_buffers[i].mapping = 0;
809
810 tp->rx_ring[i].status = 0; /* Not owned by Tulip chip. */
811 tp->rx_ring[i].length = 0;
812 /* An invalid address. */
813 tp->rx_ring[i].buffer1 = cpu_to_le32(0xBADF00D0);
814 if (skb) {
815 pci_unmap_single(tp->pdev, mapping, PKT_BUF_SZ,
816 PCI_DMA_FROMDEVICE);
817 dev_kfree_skb (skb);
818 }
819 }
820
821 for (i = 0; i < TX_RING_SIZE; i++) {
822 struct sk_buff *skb = tp->tx_buffers[i].skb;
823
824 if (skb != NULL) {
825 pci_unmap_single(tp->pdev, tp->tx_buffers[i].mapping,
826 skb->len, PCI_DMA_TODEVICE);
827 dev_kfree_skb (skb);
828 }
829 tp->tx_buffers[i].skb = NULL;
830 tp->tx_buffers[i].mapping = 0;
831 }
832 }
833
834 static int tulip_close (struct net_device *dev)
835 {
836 struct tulip_private *tp = netdev_priv(dev);
837 void __iomem *ioaddr = tp->base_addr;
838
839 netif_stop_queue (dev);
840
841 tulip_down (dev);
842
843 if (tulip_debug > 1)
844 netdev_dbg(dev, "Shutting down ethercard, status was %02x\n",
845 ioread32 (ioaddr + CSR5));
846
847 free_irq (dev->irq, dev);
848
849 tulip_free_ring (dev);
850
851 return 0;
852 }
853
854 static struct net_device_stats *tulip_get_stats(struct net_device *dev)
855 {
856 struct tulip_private *tp = netdev_priv(dev);
857 void __iomem *ioaddr = tp->base_addr;
858
859 if (netif_running(dev)) {
860 unsigned long flags;
861
862 spin_lock_irqsave (&tp->lock, flags);
863
864 dev->stats.rx_missed_errors += ioread32(ioaddr + CSR8) & 0xffff;
865
866 spin_unlock_irqrestore(&tp->lock, flags);
867 }
868
869 return &dev->stats;
870 }
871
872
873 static void tulip_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
874 {
875 struct tulip_private *np = netdev_priv(dev);
876 strcpy(info->driver, DRV_NAME);
877 strcpy(info->version, DRV_VERSION);
878 strcpy(info->bus_info, pci_name(np->pdev));
879 }
880
881
882 static int tulip_ethtool_set_wol(struct net_device *dev,
883 struct ethtool_wolinfo *wolinfo)
884 {
885 struct tulip_private *tp = netdev_priv(dev);
886
887 if (wolinfo->wolopts & (~tp->wolinfo.supported))
888 return -EOPNOTSUPP;
889
890 tp->wolinfo.wolopts = wolinfo->wolopts;
891 device_set_wakeup_enable(&tp->pdev->dev, tp->wolinfo.wolopts);
892 return 0;
893 }
894
895 static void tulip_ethtool_get_wol(struct net_device *dev,
896 struct ethtool_wolinfo *wolinfo)
897 {
898 struct tulip_private *tp = netdev_priv(dev);
899
900 wolinfo->supported = tp->wolinfo.supported;
901 wolinfo->wolopts = tp->wolinfo.wolopts;
902 return;
903 }
904
905
906 static const struct ethtool_ops ops = {
907 .get_drvinfo = tulip_get_drvinfo,
908 .set_wol = tulip_ethtool_set_wol,
909 .get_wol = tulip_ethtool_get_wol,
910 };
911
912 /* Provide ioctl() calls to examine the MII xcvr state. */
913 static int private_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
914 {
915 struct tulip_private *tp = netdev_priv(dev);
916 void __iomem *ioaddr = tp->base_addr;
917 struct mii_ioctl_data *data = if_mii(rq);
918 const unsigned int phy_idx = 0;
919 int phy = tp->phys[phy_idx] & 0x1f;
920 unsigned int regnum = data->reg_num;
921
922 switch (cmd) {
923 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
924 if (tp->mii_cnt)
925 data->phy_id = phy;
926 else if (tp->flags & HAS_NWAY)
927 data->phy_id = 32;
928 else if (tp->chip_id == COMET)
929 data->phy_id = 1;
930 else
931 return -ENODEV;
932
933 case SIOCGMIIREG: /* Read MII PHY register. */
934 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
935 int csr12 = ioread32 (ioaddr + CSR12);
936 int csr14 = ioread32 (ioaddr + CSR14);
937 switch (regnum) {
938 case 0:
939 if (((csr14<<5) & 0x1000) ||
940 (dev->if_port == 5 && tp->nwayset))
941 data->val_out = 0x1000;
942 else
943 data->val_out = (tulip_media_cap[dev->if_port]&MediaIs100 ? 0x2000 : 0)
944 | (tulip_media_cap[dev->if_port]&MediaIsFD ? 0x0100 : 0);
945 break;
946 case 1:
947 data->val_out =
948 0x1848 +
949 ((csr12&0x7000) == 0x5000 ? 0x20 : 0) +
950 ((csr12&0x06) == 6 ? 0 : 4);
951 data->val_out |= 0x6048;
952 break;
953 case 4:
954 /* Advertised value, bogus 10baseTx-FD value from CSR6. */
955 data->val_out =
956 ((ioread32(ioaddr + CSR6) >> 3) & 0x0040) +
957 ((csr14 >> 1) & 0x20) + 1;
958 data->val_out |= ((csr14 >> 9) & 0x03C0);
959 break;
960 case 5: data->val_out = tp->lpar; break;
961 default: data->val_out = 0; break;
962 }
963 } else {
964 data->val_out = tulip_mdio_read (dev, data->phy_id & 0x1f, regnum);
965 }
966 return 0;
967
968 case SIOCSMIIREG: /* Write MII PHY register. */
969 if (regnum & ~0x1f)
970 return -EINVAL;
971 if (data->phy_id == phy) {
972 u16 value = data->val_in;
973 switch (regnum) {
974 case 0: /* Check for autonegotiation on or reset. */
975 tp->full_duplex_lock = (value & 0x9000) ? 0 : 1;
976 if (tp->full_duplex_lock)
977 tp->full_duplex = (value & 0x0100) ? 1 : 0;
978 break;
979 case 4:
980 tp->advertising[phy_idx] =
981 tp->mii_advertise = data->val_in;
982 break;
983 }
984 }
985 if (data->phy_id == 32 && (tp->flags & HAS_NWAY)) {
986 u16 value = data->val_in;
987 if (regnum == 0) {
988 if ((value & 0x1200) == 0x1200) {
989 if (tp->chip_id == PNIC2) {
990 pnic2_start_nway (dev);
991 } else {
992 t21142_start_nway (dev);
993 }
994 }
995 } else if (regnum == 4)
996 tp->sym_advertise = value;
997 } else {
998 tulip_mdio_write (dev, data->phy_id & 0x1f, regnum, data->val_in);
999 }
1000 return 0;
1001 default:
1002 return -EOPNOTSUPP;
1003 }
1004
1005 return -EOPNOTSUPP;
1006 }
1007
1008
1009 /* Set or clear the multicast filter for this adaptor.
1010 Note that we only use exclusion around actually queueing the
1011 new frame, not around filling tp->setup_frame. This is non-deterministic
1012 when re-entered but still correct. */
1013
1014 #undef set_bit_le
1015 #define set_bit_le(i,p) do { ((char *)(p))[(i)/8] |= (1<<((i)%8)); } while(0)
1016
1017 static void build_setup_frame_hash(u16 *setup_frm, struct net_device *dev)
1018 {
1019 struct tulip_private *tp = netdev_priv(dev);
1020 u16 hash_table[32];
1021 struct netdev_hw_addr *ha;
1022 int i;
1023 u16 *eaddrs;
1024
1025 memset(hash_table, 0, sizeof(hash_table));
1026 set_bit_le(255, hash_table); /* Broadcast entry */
1027 /* This should work on big-endian machines as well. */
1028 netdev_for_each_mc_addr(ha, dev) {
1029 int index = ether_crc_le(ETH_ALEN, ha->addr) & 0x1ff;
1030
1031 set_bit_le(index, hash_table);
1032 }
1033 for (i = 0; i < 32; i++) {
1034 *setup_frm++ = hash_table[i];
1035 *setup_frm++ = hash_table[i];
1036 }
1037 setup_frm = &tp->setup_frame[13*6];
1038
1039 /* Fill the final entry with our physical address. */
1040 eaddrs = (u16 *)dev->dev_addr;
1041 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1042 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1043 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1044 }
1045
1046 static void build_setup_frame_perfect(u16 *setup_frm, struct net_device *dev)
1047 {
1048 struct tulip_private *tp = netdev_priv(dev);
1049 struct netdev_hw_addr *ha;
1050 u16 *eaddrs;
1051
1052 /* We have <= 14 addresses so we can use the wonderful
1053 16 address perfect filtering of the Tulip. */
1054 netdev_for_each_mc_addr(ha, dev) {
1055 eaddrs = (u16 *) ha->addr;
1056 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1057 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1058 *setup_frm++ = *eaddrs; *setup_frm++ = *eaddrs++;
1059 }
1060 /* Fill the unused entries with the broadcast address. */
1061 memset(setup_frm, 0xff, (15 - netdev_mc_count(dev)) * 12);
1062 setup_frm = &tp->setup_frame[15*6];
1063
1064 /* Fill the final entry with our physical address. */
1065 eaddrs = (u16 *)dev->dev_addr;
1066 *setup_frm++ = eaddrs[0]; *setup_frm++ = eaddrs[0];
1067 *setup_frm++ = eaddrs[1]; *setup_frm++ = eaddrs[1];
1068 *setup_frm++ = eaddrs[2]; *setup_frm++ = eaddrs[2];
1069 }
1070
1071
1072 static void set_rx_mode(struct net_device *dev)
1073 {
1074 struct tulip_private *tp = netdev_priv(dev);
1075 void __iomem *ioaddr = tp->base_addr;
1076 int csr6;
1077
1078 csr6 = ioread32(ioaddr + CSR6) & ~0x00D5;
1079
1080 tp->csr6 &= ~0x00D5;
1081 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1082 tp->csr6 |= AcceptAllMulticast | AcceptAllPhys;
1083 csr6 |= AcceptAllMulticast | AcceptAllPhys;
1084 } else if ((netdev_mc_count(dev) > 1000) ||
1085 (dev->flags & IFF_ALLMULTI)) {
1086 /* Too many to filter well -- accept all multicasts. */
1087 tp->csr6 |= AcceptAllMulticast;
1088 csr6 |= AcceptAllMulticast;
1089 } else if (tp->flags & MC_HASH_ONLY) {
1090 /* Some work-alikes have only a 64-entry hash filter table. */
1091 /* Should verify correctness on big-endian/__powerpc__ */
1092 struct netdev_hw_addr *ha;
1093 if (netdev_mc_count(dev) > 64) {
1094 /* Arbitrary non-effective limit. */
1095 tp->csr6 |= AcceptAllMulticast;
1096 csr6 |= AcceptAllMulticast;
1097 } else {
1098 u32 mc_filter[2] = {0, 0}; /* Multicast hash filter */
1099 int filterbit;
1100 netdev_for_each_mc_addr(ha, dev) {
1101 if (tp->flags & COMET_MAC_ADDR)
1102 filterbit = ether_crc_le(ETH_ALEN,
1103 ha->addr);
1104 else
1105 filterbit = ether_crc(ETH_ALEN,
1106 ha->addr) >> 26;
1107 filterbit &= 0x3f;
1108 mc_filter[filterbit >> 5] |= 1 << (filterbit & 31);
1109 if (tulip_debug > 2)
1110 dev_info(&dev->dev,
1111 "Added filter for %pM %08x bit %d\n",
1112 ha->addr,
1113 ether_crc(ETH_ALEN, ha->addr),
1114 filterbit);
1115 }
1116 if (mc_filter[0] == tp->mc_filter[0] &&
1117 mc_filter[1] == tp->mc_filter[1])
1118 ; /* No change. */
1119 else if (tp->flags & IS_ASIX) {
1120 iowrite32(2, ioaddr + CSR13);
1121 iowrite32(mc_filter[0], ioaddr + CSR14);
1122 iowrite32(3, ioaddr + CSR13);
1123 iowrite32(mc_filter[1], ioaddr + CSR14);
1124 } else if (tp->flags & COMET_MAC_ADDR) {
1125 iowrite32(mc_filter[0], ioaddr + CSR27);
1126 iowrite32(mc_filter[1], ioaddr + CSR28);
1127 }
1128 tp->mc_filter[0] = mc_filter[0];
1129 tp->mc_filter[1] = mc_filter[1];
1130 }
1131 } else {
1132 unsigned long flags;
1133 u32 tx_flags = 0x08000000 | 192;
1134
1135 /* Note that only the low-address shortword of setup_frame is valid!
1136 The values are doubled for big-endian architectures. */
1137 if (netdev_mc_count(dev) > 14) {
1138 /* Must use a multicast hash table. */
1139 build_setup_frame_hash(tp->setup_frame, dev);
1140 tx_flags = 0x08400000 | 192;
1141 } else {
1142 build_setup_frame_perfect(tp->setup_frame, dev);
1143 }
1144
1145 spin_lock_irqsave(&tp->lock, flags);
1146
1147 if (tp->cur_tx - tp->dirty_tx > TX_RING_SIZE - 2) {
1148 /* Same setup recently queued, we need not add it. */
1149 } else {
1150 unsigned int entry;
1151 int dummy = -1;
1152
1153 /* Now add this frame to the Tx list. */
1154
1155 entry = tp->cur_tx++ % TX_RING_SIZE;
1156
1157 if (entry != 0) {
1158 /* Avoid a chip errata by prefixing a dummy entry. */
1159 tp->tx_buffers[entry].skb = NULL;
1160 tp->tx_buffers[entry].mapping = 0;
1161 tp->tx_ring[entry].length =
1162 (entry == TX_RING_SIZE-1) ? cpu_to_le32(DESC_RING_WRAP) : 0;
1163 tp->tx_ring[entry].buffer1 = 0;
1164 /* Must set DescOwned later to avoid race with chip */
1165 dummy = entry;
1166 entry = tp->cur_tx++ % TX_RING_SIZE;
1167
1168 }
1169
1170 tp->tx_buffers[entry].skb = NULL;
1171 tp->tx_buffers[entry].mapping =
1172 pci_map_single(tp->pdev, tp->setup_frame,
1173 sizeof(tp->setup_frame),
1174 PCI_DMA_TODEVICE);
1175 /* Put the setup frame on the Tx list. */
1176 if (entry == TX_RING_SIZE-1)
1177 tx_flags |= DESC_RING_WRAP; /* Wrap ring. */
1178 tp->tx_ring[entry].length = cpu_to_le32(tx_flags);
1179 tp->tx_ring[entry].buffer1 =
1180 cpu_to_le32(tp->tx_buffers[entry].mapping);
1181 tp->tx_ring[entry].status = cpu_to_le32(DescOwned);
1182 if (dummy >= 0)
1183 tp->tx_ring[dummy].status = cpu_to_le32(DescOwned);
1184 if (tp->cur_tx - tp->dirty_tx >= TX_RING_SIZE - 2)
1185 netif_stop_queue(dev);
1186
1187 /* Trigger an immediate transmit demand. */
1188 iowrite32(0, ioaddr + CSR1);
1189 }
1190
1191 spin_unlock_irqrestore(&tp->lock, flags);
1192 }
1193
1194 iowrite32(csr6, ioaddr + CSR6);
1195 }
1196
1197 #ifdef CONFIG_TULIP_MWI
1198 static void __devinit tulip_mwi_config (struct pci_dev *pdev,
1199 struct net_device *dev)
1200 {
1201 struct tulip_private *tp = netdev_priv(dev);
1202 u8 cache;
1203 u16 pci_command;
1204 u32 csr0;
1205
1206 if (tulip_debug > 3)
1207 netdev_dbg(dev, "tulip_mwi_config()\n");
1208
1209 tp->csr0 = csr0 = 0;
1210
1211 /* if we have any cache line size at all, we can do MRM and MWI */
1212 csr0 |= MRM | MWI;
1213
1214 /* Enable MWI in the standard PCI command bit.
1215 * Check for the case where MWI is desired but not available
1216 */
1217 pci_try_set_mwi(pdev);
1218
1219 /* read result from hardware (in case bit refused to enable) */
1220 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
1221 if ((csr0 & MWI) && (!(pci_command & PCI_COMMAND_INVALIDATE)))
1222 csr0 &= ~MWI;
1223
1224 /* if cache line size hardwired to zero, no MWI */
1225 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache);
1226 if ((csr0 & MWI) && (cache == 0)) {
1227 csr0 &= ~MWI;
1228 pci_clear_mwi(pdev);
1229 }
1230
1231 /* assign per-cacheline-size cache alignment and
1232 * burst length values
1233 */
1234 switch (cache) {
1235 case 8:
1236 csr0 |= MRL | (1 << CALShift) | (16 << BurstLenShift);
1237 break;
1238 case 16:
1239 csr0 |= MRL | (2 << CALShift) | (16 << BurstLenShift);
1240 break;
1241 case 32:
1242 csr0 |= MRL | (3 << CALShift) | (32 << BurstLenShift);
1243 break;
1244 default:
1245 cache = 0;
1246 break;
1247 }
1248
1249 /* if we have a good cache line size, we by now have a good
1250 * csr0, so save it and exit
1251 */
1252 if (cache)
1253 goto out;
1254
1255 /* we don't have a good csr0 or cache line size, disable MWI */
1256 if (csr0 & MWI) {
1257 pci_clear_mwi(pdev);
1258 csr0 &= ~MWI;
1259 }
1260
1261 /* sane defaults for burst length and cache alignment
1262 * originally from de4x5 driver
1263 */
1264 csr0 |= (8 << BurstLenShift) | (1 << CALShift);
1265
1266 out:
1267 tp->csr0 = csr0;
1268 if (tulip_debug > 2)
1269 netdev_dbg(dev, "MWI config cacheline=%d, csr0=%08x\n",
1270 cache, csr0);
1271 }
1272 #endif
1273
1274 /*
1275 * Chips that have the MRM/reserved bit quirk and the burst quirk. That
1276 * is the DM910X and the on chip ULi devices
1277 */
1278
1279 static int tulip_uli_dm_quirk(struct pci_dev *pdev)
1280 {
1281 if (pdev->vendor == 0x1282 && pdev->device == 0x9102)
1282 return 1;
1283 return 0;
1284 }
1285
1286 static const struct net_device_ops tulip_netdev_ops = {
1287 .ndo_open = tulip_open,
1288 .ndo_start_xmit = tulip_start_xmit,
1289 .ndo_tx_timeout = tulip_tx_timeout,
1290 .ndo_stop = tulip_close,
1291 .ndo_get_stats = tulip_get_stats,
1292 .ndo_do_ioctl = private_ioctl,
1293 .ndo_set_multicast_list = set_rx_mode,
1294 .ndo_change_mtu = eth_change_mtu,
1295 .ndo_set_mac_address = eth_mac_addr,
1296 .ndo_validate_addr = eth_validate_addr,
1297 #ifdef CONFIG_NET_POLL_CONTROLLER
1298 .ndo_poll_controller = poll_tulip,
1299 #endif
1300 };
1301
1302 DEFINE_PCI_DEVICE_TABLE(early_486_chipsets) = {
1303 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82424) },
1304 { PCI_DEVICE(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496) },
1305 { },
1306 };
1307
1308 static int __devinit tulip_init_one (struct pci_dev *pdev,
1309 const struct pci_device_id *ent)
1310 {
1311 struct tulip_private *tp;
1312 /* See note below on the multiport cards. */
1313 static unsigned char last_phys_addr[6] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1314 static int last_irq;
1315 static int multiport_cnt; /* For four-port boards w/one EEPROM */
1316 int i, irq;
1317 unsigned short sum;
1318 unsigned char *ee_data;
1319 struct net_device *dev;
1320 void __iomem *ioaddr;
1321 static int board_idx = -1;
1322 int chip_idx = ent->driver_data;
1323 const char *chip_name = tulip_tbl[chip_idx].chip_name;
1324 unsigned int eeprom_missing = 0;
1325 unsigned int force_csr0 = 0;
1326
1327 #ifndef MODULE
1328 if (tulip_debug > 0)
1329 printk_once(KERN_INFO "%s", version);
1330 #endif
1331
1332 board_idx++;
1333
1334 /*
1335 * Lan media wire a tulip chip to a wan interface. Needs a very
1336 * different driver (lmc driver)
1337 */
1338
1339 if (pdev->subsystem_vendor == PCI_VENDOR_ID_LMC) {
1340 pr_err("skipping LMC card\n");
1341 return -ENODEV;
1342 } else if (pdev->subsystem_vendor == PCI_VENDOR_ID_SBE &&
1343 (pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_T3E3 ||
1344 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P0 ||
1345 pdev->subsystem_device == PCI_SUBDEVICE_ID_SBE_2T3E3_P1)) {
1346 pr_err("skipping SBE T3E3 port\n");
1347 return -ENODEV;
1348 }
1349
1350 /*
1351 * DM910x chips should be handled by the dmfe driver, except
1352 * on-board chips on SPARC systems. Also, early DM9100s need
1353 * software CRC which only the dmfe driver supports.
1354 */
1355
1356 #ifdef CONFIG_TULIP_DM910X
1357 if (chip_idx == DM910X) {
1358 struct device_node *dp;
1359
1360 if (pdev->vendor == 0x1282 && pdev->device == 0x9100 &&
1361 pdev->revision < 0x30) {
1362 pr_info("skipping early DM9100 with Crc bug (use dmfe)\n");
1363 return -ENODEV;
1364 }
1365
1366 dp = pci_device_to_OF_node(pdev);
1367 if (!(dp && of_get_property(dp, "local-mac-address", NULL))) {
1368 pr_info("skipping DM910x expansion card (use dmfe)\n");
1369 return -ENODEV;
1370 }
1371 }
1372 #endif
1373
1374 /*
1375 * Looks for early PCI chipsets where people report hangs
1376 * without the workarounds being on.
1377 */
1378
1379 /* 1. Intel Saturn. Switch to 8 long words burst, 8 long word cache
1380 aligned. Aries might need this too. The Saturn errata are not
1381 pretty reading but thankfully it's an old 486 chipset.
1382
1383 2. The dreaded SiS496 486 chipset. Same workaround as Intel
1384 Saturn.
1385 */
1386
1387 if (pci_dev_present(early_486_chipsets)) {
1388 csr0 = MRL | MRM | (8 << BurstLenShift) | (1 << CALShift);
1389 force_csr0 = 1;
1390 }
1391
1392 /* bugfix: the ASIX must have a burst limit or horrible things happen. */
1393 if (chip_idx == AX88140) {
1394 if ((csr0 & 0x3f00) == 0)
1395 csr0 |= 0x2000;
1396 }
1397
1398 /* PNIC doesn't have MWI/MRL/MRM... */
1399 if (chip_idx == LC82C168)
1400 csr0 &= ~0xfff10000; /* zero reserved bits 31:20, 16 */
1401
1402 /* DM9102A has troubles with MRM & clear reserved bits 24:22, 20, 16, 7:1 */
1403 if (tulip_uli_dm_quirk(pdev)) {
1404 csr0 &= ~0x01f100ff;
1405 #if defined(CONFIG_SPARC)
1406 csr0 = (csr0 & ~0xff00) | 0xe000;
1407 #endif
1408 }
1409 /*
1410 * And back to business
1411 */
1412
1413 i = pci_enable_device(pdev);
1414 if (i) {
1415 pr_err("Cannot enable tulip board #%d, aborting\n", board_idx);
1416 return i;
1417 }
1418
1419 /* The chip will fail to enter a low-power state later unless
1420 * first explicitly commanded into D0 */
1421 if (pci_set_power_state(pdev, PCI_D0)) {
1422 pr_notice("Failed to set power state to D0\n");
1423 }
1424
1425 irq = pdev->irq;
1426
1427 /* alloc_etherdev ensures aligned and zeroed private structures */
1428 dev = alloc_etherdev (sizeof (*tp));
1429 if (!dev) {
1430 pr_err("ether device alloc failed, aborting\n");
1431 return -ENOMEM;
1432 }
1433
1434 SET_NETDEV_DEV(dev, &pdev->dev);
1435 if (pci_resource_len (pdev, 0) < tulip_tbl[chip_idx].io_size) {
1436 pr_err("%s: I/O region (0x%llx@0x%llx) too small, aborting\n",
1437 pci_name(pdev),
1438 (unsigned long long)pci_resource_len (pdev, 0),
1439 (unsigned long long)pci_resource_start (pdev, 0));
1440 goto err_out_free_netdev;
1441 }
1442
1443 /* grab all resources from both PIO and MMIO regions, as we
1444 * don't want anyone else messing around with our hardware */
1445 if (pci_request_regions (pdev, DRV_NAME))
1446 goto err_out_free_netdev;
1447
1448 ioaddr = pci_iomap(pdev, TULIP_BAR, tulip_tbl[chip_idx].io_size);
1449
1450 if (!ioaddr)
1451 goto err_out_free_res;
1452
1453 /*
1454 * initialize private data structure 'tp'
1455 * it is zeroed and aligned in alloc_etherdev
1456 */
1457 tp = netdev_priv(dev);
1458 tp->dev = dev;
1459
1460 tp->rx_ring = pci_alloc_consistent(pdev,
1461 sizeof(struct tulip_rx_desc) * RX_RING_SIZE +
1462 sizeof(struct tulip_tx_desc) * TX_RING_SIZE,
1463 &tp->rx_ring_dma);
1464 if (!tp->rx_ring)
1465 goto err_out_mtable;
1466 tp->tx_ring = (struct tulip_tx_desc *)(tp->rx_ring + RX_RING_SIZE);
1467 tp->tx_ring_dma = tp->rx_ring_dma + sizeof(struct tulip_rx_desc) * RX_RING_SIZE;
1468
1469 tp->chip_id = chip_idx;
1470 tp->flags = tulip_tbl[chip_idx].flags;
1471
1472 tp->wolinfo.supported = 0;
1473 tp->wolinfo.wolopts = 0;
1474 /* COMET: Enable power management only for AN983B */
1475 if (chip_idx == COMET ) {
1476 u32 sig;
1477 pci_read_config_dword (pdev, 0x80, &sig);
1478 if (sig == 0x09811317) {
1479 tp->flags |= COMET_PM;
1480 tp->wolinfo.supported = WAKE_PHY | WAKE_MAGIC;
1481 pr_info("%s: Enabled WOL support for AN983B\n",
1482 __func__);
1483 }
1484 }
1485 tp->pdev = pdev;
1486 tp->base_addr = ioaddr;
1487 tp->revision = pdev->revision;
1488 tp->csr0 = csr0;
1489 spin_lock_init(&tp->lock);
1490 spin_lock_init(&tp->mii_lock);
1491 init_timer(&tp->timer);
1492 tp->timer.data = (unsigned long)dev;
1493 tp->timer.function = tulip_tbl[tp->chip_id].media_timer;
1494
1495 INIT_WORK(&tp->media_work, tulip_tbl[tp->chip_id].media_task);
1496
1497 dev->base_addr = (unsigned long)ioaddr;
1498
1499 #ifdef CONFIG_TULIP_MWI
1500 if (!force_csr0 && (tp->flags & HAS_PCI_MWI))
1501 tulip_mwi_config (pdev, dev);
1502 #endif
1503
1504 /* Stop the chip's Tx and Rx processes. */
1505 tulip_stop_rxtx(tp);
1506
1507 pci_set_master(pdev);
1508
1509 #ifdef CONFIG_GSC
1510 if (pdev->subsystem_vendor == PCI_VENDOR_ID_HP) {
1511 switch (pdev->subsystem_device) {
1512 default:
1513 break;
1514 case 0x1061:
1515 case 0x1062:
1516 case 0x1063:
1517 case 0x1098:
1518 case 0x1099:
1519 case 0x10EE:
1520 tp->flags |= HAS_SWAPPED_SEEPROM | NEEDS_FAKE_MEDIA_TABLE;
1521 chip_name = "GSC DS21140 Tulip";
1522 }
1523 }
1524 #endif
1525
1526 /* Clear the missed-packet counter. */
1527 ioread32(ioaddr + CSR8);
1528
1529 /* The station address ROM is read byte serially. The register must
1530 be polled, waiting for the value to be read bit serially from the
1531 EEPROM.
1532 */
1533 ee_data = tp->eeprom;
1534 memset(ee_data, 0, sizeof(tp->eeprom));
1535 sum = 0;
1536 if (chip_idx == LC82C168) {
1537 for (i = 0; i < 3; i++) {
1538 int value, boguscnt = 100000;
1539 iowrite32(0x600 | i, ioaddr + 0x98);
1540 do {
1541 value = ioread32(ioaddr + CSR9);
1542 } while (value < 0 && --boguscnt > 0);
1543 put_unaligned_le16(value, ((__le16 *)dev->dev_addr) + i);
1544 sum += value & 0xffff;
1545 }
1546 } else if (chip_idx == COMET) {
1547 /* No need to read the EEPROM. */
1548 put_unaligned_le32(ioread32(ioaddr + 0xA4), dev->dev_addr);
1549 put_unaligned_le16(ioread32(ioaddr + 0xA8), dev->dev_addr + 4);
1550 for (i = 0; i < 6; i ++)
1551 sum += dev->dev_addr[i];
1552 } else {
1553 /* A serial EEPROM interface, we read now and sort it out later. */
1554 int sa_offset = 0;
1555 int ee_addr_size = tulip_read_eeprom(dev, 0xff, 8) & 0x40000 ? 8 : 6;
1556 int ee_max_addr = ((1 << ee_addr_size) - 1) * sizeof(u16);
1557
1558 if (ee_max_addr > sizeof(tp->eeprom))
1559 ee_max_addr = sizeof(tp->eeprom);
1560
1561 for (i = 0; i < ee_max_addr ; i += sizeof(u16)) {
1562 u16 data = tulip_read_eeprom(dev, i/2, ee_addr_size);
1563 ee_data[i] = data & 0xff;
1564 ee_data[i + 1] = data >> 8;
1565 }
1566
1567 /* DEC now has a specification (see Notes) but early board makers
1568 just put the address in the first EEPROM locations. */
1569 /* This does memcmp(ee_data, ee_data+16, 8) */
1570 for (i = 0; i < 8; i ++)
1571 if (ee_data[i] != ee_data[16+i])
1572 sa_offset = 20;
1573 if (chip_idx == CONEXANT) {
1574 /* Check that the tuple type and length is correct. */
1575 if (ee_data[0x198] == 0x04 && ee_data[0x199] == 6)
1576 sa_offset = 0x19A;
1577 } else if (ee_data[0] == 0xff && ee_data[1] == 0xff &&
1578 ee_data[2] == 0) {
1579 sa_offset = 2; /* Grrr, damn Matrox boards. */
1580 multiport_cnt = 4;
1581 }
1582 #ifdef CONFIG_MIPS_COBALT
1583 if ((pdev->bus->number == 0) &&
1584 ((PCI_SLOT(pdev->devfn) == 7) ||
1585 (PCI_SLOT(pdev->devfn) == 12))) {
1586 /* Cobalt MAC address in first EEPROM locations. */
1587 sa_offset = 0;
1588 /* Ensure our media table fixup get's applied */
1589 memcpy(ee_data + 16, ee_data, 8);
1590 }
1591 #endif
1592 #ifdef CONFIG_GSC
1593 /* Check to see if we have a broken srom */
1594 if (ee_data[0] == 0x61 && ee_data[1] == 0x10) {
1595 /* pci_vendor_id and subsystem_id are swapped */
1596 ee_data[0] = ee_data[2];
1597 ee_data[1] = ee_data[3];
1598 ee_data[2] = 0x61;
1599 ee_data[3] = 0x10;
1600
1601 /* HSC-PCI boards need to be byte-swaped and shifted
1602 * up 1 word. This shift needs to happen at the end
1603 * of the MAC first because of the 2 byte overlap.
1604 */
1605 for (i = 4; i >= 0; i -= 2) {
1606 ee_data[17 + i + 3] = ee_data[17 + i];
1607 ee_data[16 + i + 5] = ee_data[16 + i];
1608 }
1609 }
1610 #endif
1611
1612 for (i = 0; i < 6; i ++) {
1613 dev->dev_addr[i] = ee_data[i + sa_offset];
1614 sum += ee_data[i + sa_offset];
1615 }
1616 }
1617 /* Lite-On boards have the address byte-swapped. */
1618 if ((dev->dev_addr[0] == 0xA0 ||
1619 dev->dev_addr[0] == 0xC0 ||
1620 dev->dev_addr[0] == 0x02) &&
1621 dev->dev_addr[1] == 0x00)
1622 for (i = 0; i < 6; i+=2) {
1623 char tmp = dev->dev_addr[i];
1624 dev->dev_addr[i] = dev->dev_addr[i+1];
1625 dev->dev_addr[i+1] = tmp;
1626 }
1627 /* On the Zynx 315 Etherarray and other multiport boards only the
1628 first Tulip has an EEPROM.
1629 On Sparc systems the mac address is held in the OBP property
1630 "local-mac-address".
1631 The addresses of the subsequent ports are derived from the first.
1632 Many PCI BIOSes also incorrectly report the IRQ line, so we correct
1633 that here as well. */
1634 if (sum == 0 || sum == 6*0xff) {
1635 #if defined(CONFIG_SPARC)
1636 struct device_node *dp = pci_device_to_OF_node(pdev);
1637 const unsigned char *addr;
1638 int len;
1639 #endif
1640 eeprom_missing = 1;
1641 for (i = 0; i < 5; i++)
1642 dev->dev_addr[i] = last_phys_addr[i];
1643 dev->dev_addr[i] = last_phys_addr[i] + 1;
1644 #if defined(CONFIG_SPARC)
1645 addr = of_get_property(dp, "local-mac-address", &len);
1646 if (addr && len == 6)
1647 memcpy(dev->dev_addr, addr, 6);
1648 #endif
1649 #if defined(__i386__) || defined(__x86_64__) /* Patch up x86 BIOS bug. */
1650 if (last_irq)
1651 irq = last_irq;
1652 #endif
1653 }
1654
1655 for (i = 0; i < 6; i++)
1656 last_phys_addr[i] = dev->dev_addr[i];
1657 last_irq = irq;
1658 dev->irq = irq;
1659
1660 /* The lower four bits are the media type. */
1661 if (board_idx >= 0 && board_idx < MAX_UNITS) {
1662 if (options[board_idx] & MEDIA_MASK)
1663 tp->default_port = options[board_idx] & MEDIA_MASK;
1664 if ((options[board_idx] & FullDuplex) || full_duplex[board_idx] > 0)
1665 tp->full_duplex = 1;
1666 if (mtu[board_idx] > 0)
1667 dev->mtu = mtu[board_idx];
1668 }
1669 if (dev->mem_start & MEDIA_MASK)
1670 tp->default_port = dev->mem_start & MEDIA_MASK;
1671 if (tp->default_port) {
1672 pr_info(DRV_NAME "%d: Transceiver selection forced to %s\n",
1673 board_idx, medianame[tp->default_port & MEDIA_MASK]);
1674 tp->medialock = 1;
1675 if (tulip_media_cap[tp->default_port] & MediaAlwaysFD)
1676 tp->full_duplex = 1;
1677 }
1678 if (tp->full_duplex)
1679 tp->full_duplex_lock = 1;
1680
1681 if (tulip_media_cap[tp->default_port] & MediaIsMII) {
1682 static const u16 media2advert[] = {
1683 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200
1684 };
1685 tp->mii_advertise = media2advert[tp->default_port - 9];
1686 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1687 }
1688
1689 if (tp->flags & HAS_MEDIA_TABLE) {
1690 sprintf(dev->name, DRV_NAME "%d", board_idx); /* hack */
1691 tulip_parse_eeprom(dev);
1692 strcpy(dev->name, "eth%d"); /* un-hack */
1693 }
1694
1695 if ((tp->flags & ALWAYS_CHECK_MII) ||
1696 (tp->mtable && tp->mtable->has_mii) ||
1697 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1698 if (tp->mtable && tp->mtable->has_mii) {
1699 for (i = 0; i < tp->mtable->leafcount; i++)
1700 if (tp->mtable->mleaf[i].media == 11) {
1701 tp->cur_index = i;
1702 tp->saved_if_port = dev->if_port;
1703 tulip_select_media(dev, 2);
1704 dev->if_port = tp->saved_if_port;
1705 break;
1706 }
1707 }
1708
1709 /* Find the connected MII xcvrs.
1710 Doing this in open() would allow detecting external xcvrs
1711 later, but takes much time. */
1712 tulip_find_mii (dev, board_idx);
1713 }
1714
1715 /* The Tulip-specific entries in the device structure. */
1716 dev->netdev_ops = &tulip_netdev_ops;
1717 dev->watchdog_timeo = TX_TIMEOUT;
1718 #ifdef CONFIG_TULIP_NAPI
1719 netif_napi_add(dev, &tp->napi, tulip_poll, 16);
1720 #endif
1721 SET_ETHTOOL_OPS(dev, &ops);
1722
1723 if (register_netdev(dev))
1724 goto err_out_free_ring;
1725
1726 pci_set_drvdata(pdev, dev);
1727
1728 dev_info(&dev->dev,
1729 #ifdef CONFIG_TULIP_MMIO
1730 "%s rev %d at MMIO %#llx,%s %pM, IRQ %d\n",
1731 #else
1732 "%s rev %d at Port %#llx,%s %pM, IRQ %d\n",
1733 #endif
1734 chip_name, pdev->revision,
1735 (unsigned long long)pci_resource_start(pdev, TULIP_BAR),
1736 eeprom_missing ? " EEPROM not present," : "",
1737 dev->dev_addr, irq);
1738
1739 if (tp->chip_id == PNIC2)
1740 tp->link_change = pnic2_lnk_change;
1741 else if (tp->flags & HAS_NWAY)
1742 tp->link_change = t21142_lnk_change;
1743 else if (tp->flags & HAS_PNICNWAY)
1744 tp->link_change = pnic_lnk_change;
1745
1746 /* Reset the xcvr interface and turn on heartbeat. */
1747 switch (chip_idx) {
1748 case DC21140:
1749 case DM910X:
1750 default:
1751 if (tp->mtable)
1752 iowrite32(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1753 break;
1754 case DC21142:
1755 if (tp->mii_cnt || tulip_media_cap[dev->if_port] & MediaIsMII) {
1756 iowrite32(csr6_mask_defstate, ioaddr + CSR6);
1757 iowrite32(0x0000, ioaddr + CSR13);
1758 iowrite32(0x0000, ioaddr + CSR14);
1759 iowrite32(csr6_mask_hdcap, ioaddr + CSR6);
1760 } else
1761 t21142_start_nway(dev);
1762 break;
1763 case PNIC2:
1764 /* just do a reset for sanity sake */
1765 iowrite32(0x0000, ioaddr + CSR13);
1766 iowrite32(0x0000, ioaddr + CSR14);
1767 break;
1768 case LC82C168:
1769 if ( ! tp->mii_cnt) {
1770 tp->nway = 1;
1771 tp->nwayset = 0;
1772 iowrite32(csr6_ttm | csr6_ca, ioaddr + CSR6);
1773 iowrite32(0x30, ioaddr + CSR12);
1774 iowrite32(0x0001F078, ioaddr + CSR6);
1775 iowrite32(0x0201F078, ioaddr + CSR6); /* Turn on autonegotiation. */
1776 }
1777 break;
1778 case MX98713:
1779 case COMPEX9881:
1780 iowrite32(0x00000000, ioaddr + CSR6);
1781 iowrite32(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1782 iowrite32(0x00000001, ioaddr + CSR13);
1783 break;
1784 case MX98715:
1785 case MX98725:
1786 iowrite32(0x01a80000, ioaddr + CSR6);
1787 iowrite32(0xFFFFFFFF, ioaddr + CSR14);
1788 iowrite32(0x00001000, ioaddr + CSR12);
1789 break;
1790 case COMET:
1791 /* No initialization necessary. */
1792 break;
1793 }
1794
1795 /* put the chip in snooze mode until opened */
1796 tulip_set_power_state (tp, 0, 1);
1797
1798 return 0;
1799
1800 err_out_free_ring:
1801 pci_free_consistent (pdev,
1802 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1803 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1804 tp->rx_ring, tp->rx_ring_dma);
1805
1806 err_out_mtable:
1807 kfree (tp->mtable);
1808 pci_iounmap(pdev, ioaddr);
1809
1810 err_out_free_res:
1811 pci_release_regions (pdev);
1812
1813 err_out_free_netdev:
1814 free_netdev (dev);
1815 return -ENODEV;
1816 }
1817
1818
1819 /* set the registers according to the given wolopts */
1820 static void tulip_set_wolopts (struct pci_dev *pdev, u32 wolopts)
1821 {
1822 struct net_device *dev = pci_get_drvdata(pdev);
1823 struct tulip_private *tp = netdev_priv(dev);
1824 void __iomem *ioaddr = tp->base_addr;
1825
1826 if (tp->flags & COMET_PM) {
1827
1828 unsigned int tmp;
1829
1830 tmp = ioread32(ioaddr + CSR18);
1831 tmp &= ~(comet_csr18_pmes_sticky | comet_csr18_apm_mode | comet_csr18_d3a);
1832 tmp |= comet_csr18_pm_mode;
1833 iowrite32(tmp, ioaddr + CSR18);
1834
1835 /* Set the Wake-up Control/Status Register to the given WOL options*/
1836 tmp = ioread32(ioaddr + CSR13);
1837 tmp &= ~(comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_wfre | comet_csr13_lsce | comet_csr13_mpre);
1838 if (wolopts & WAKE_MAGIC)
1839 tmp |= comet_csr13_mpre;
1840 if (wolopts & WAKE_PHY)
1841 tmp |= comet_csr13_linkoffe | comet_csr13_linkone | comet_csr13_lsce;
1842 /* Clear the event flags */
1843 tmp |= comet_csr13_wfr | comet_csr13_mpr | comet_csr13_lsc;
1844 iowrite32(tmp, ioaddr + CSR13);
1845 }
1846 }
1847
1848 #ifdef CONFIG_PM
1849
1850
1851 static int tulip_suspend (struct pci_dev *pdev, pm_message_t state)
1852 {
1853 pci_power_t pstate;
1854 struct net_device *dev = pci_get_drvdata(pdev);
1855 struct tulip_private *tp = netdev_priv(dev);
1856
1857 if (!dev)
1858 return -EINVAL;
1859
1860 if (!netif_running(dev))
1861 goto save_state;
1862
1863 tulip_down(dev);
1864
1865 netif_device_detach(dev);
1866 free_irq(dev->irq, dev);
1867
1868 save_state:
1869 pci_save_state(pdev);
1870 pci_disable_device(pdev);
1871 pstate = pci_choose_state(pdev, state);
1872 if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) {
1873 int rc;
1874
1875 tulip_set_wolopts(pdev, tp->wolinfo.wolopts);
1876 rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts);
1877 if (rc)
1878 pr_err("pci_enable_wake failed (%d)\n", rc);
1879 }
1880 pci_set_power_state(pdev, pstate);
1881
1882 return 0;
1883 }
1884
1885
1886 static int tulip_resume(struct pci_dev *pdev)
1887 {
1888 struct net_device *dev = pci_get_drvdata(pdev);
1889 struct tulip_private *tp = netdev_priv(dev);
1890 void __iomem *ioaddr = tp->base_addr;
1891 int retval;
1892 unsigned int tmp;
1893
1894 if (!dev)
1895 return -EINVAL;
1896
1897 pci_set_power_state(pdev, PCI_D0);
1898 pci_restore_state(pdev);
1899
1900 if (!netif_running(dev))
1901 return 0;
1902
1903 if ((retval = pci_enable_device(pdev))) {
1904 pr_err("pci_enable_device failed in resume\n");
1905 return retval;
1906 }
1907
1908 if ((retval = request_irq(dev->irq, tulip_interrupt, IRQF_SHARED, dev->name, dev))) {
1909 pr_err("request_irq failed in resume\n");
1910 return retval;
1911 }
1912
1913 if (tp->flags & COMET_PM) {
1914 pci_enable_wake(pdev, PCI_D3hot, 0);
1915 pci_enable_wake(pdev, PCI_D3cold, 0);
1916
1917 /* Clear the PMES flag */
1918 tmp = ioread32(ioaddr + CSR20);
1919 tmp |= comet_csr20_pmes;
1920 iowrite32(tmp, ioaddr + CSR20);
1921
1922 /* Disable all wake-up events */
1923 tulip_set_wolopts(pdev, 0);
1924 }
1925 netif_device_attach(dev);
1926
1927 if (netif_running(dev))
1928 tulip_up(dev);
1929
1930 return 0;
1931 }
1932
1933 #endif /* CONFIG_PM */
1934
1935
1936 static void __devexit tulip_remove_one (struct pci_dev *pdev)
1937 {
1938 struct net_device *dev = pci_get_drvdata (pdev);
1939 struct tulip_private *tp;
1940
1941 if (!dev)
1942 return;
1943
1944 tp = netdev_priv(dev);
1945 unregister_netdev(dev);
1946 pci_free_consistent (pdev,
1947 sizeof (struct tulip_rx_desc) * RX_RING_SIZE +
1948 sizeof (struct tulip_tx_desc) * TX_RING_SIZE,
1949 tp->rx_ring, tp->rx_ring_dma);
1950 kfree (tp->mtable);
1951 pci_iounmap(pdev, tp->base_addr);
1952 free_netdev (dev);
1953 pci_release_regions (pdev);
1954 pci_set_drvdata (pdev, NULL);
1955
1956 /* pci_power_off (pdev, -1); */
1957 }
1958
1959 #ifdef CONFIG_NET_POLL_CONTROLLER
1960 /*
1961 * Polling 'interrupt' - used by things like netconsole to send skbs
1962 * without having to re-enable interrupts. It's not called while
1963 * the interrupt routine is executing.
1964 */
1965
1966 static void poll_tulip (struct net_device *dev)
1967 {
1968 /* disable_irq here is not very nice, but with the lockless
1969 interrupt handler we have no other choice. */
1970 disable_irq(dev->irq);
1971 tulip_interrupt (dev->irq, dev);
1972 enable_irq(dev->irq);
1973 }
1974 #endif
1975
1976 static struct pci_driver tulip_driver = {
1977 .name = DRV_NAME,
1978 .id_table = tulip_pci_tbl,
1979 .probe = tulip_init_one,
1980 .remove = __devexit_p(tulip_remove_one),
1981 #ifdef CONFIG_PM
1982 .suspend = tulip_suspend,
1983 .resume = tulip_resume,
1984 #endif /* CONFIG_PM */
1985 };
1986
1987
1988 static int __init tulip_init (void)
1989 {
1990 #ifdef MODULE
1991 pr_info("%s", version);
1992 #endif
1993
1994 /* copy module parms into globals */
1995 tulip_rx_copybreak = rx_copybreak;
1996 tulip_max_interrupt_work = max_interrupt_work;
1997
1998 /* probe for and init boards */
1999 return pci_register_driver(&tulip_driver);
2000 }
2001
2002
2003 static void __exit tulip_cleanup (void)
2004 {
2005 pci_unregister_driver (&tulip_driver);
2006 }
2007
2008
2009 module_init(tulip_init);
2010 module_exit(tulip_cleanup);
Linux with added FPC-III support