drivers/net/wan/c101.c

   1 /*
   2  * Moxa C101 synchronous serial card driver for Linux
   3  *
   4  * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
  11  *
  12  * Sources of information:
  13  *    Hitachi HD64570 SCA User's Manual
  14  *    Moxa C101 User's Manual
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/capability.h>
  20 #include <linux/slab.h>
  21 #include <linux/types.h>
  22 #include <linux/string.h>
  23 #include <linux/errno.h>
  24 #include <linux/init.h>
  25 #include <linux/moduleparam.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/hdlc.h>
  28 #include <linux/delay.h>
  29 #include <asm/io.h>
  30
  31 #include "hd64570.h"
  32
  33
  34 static const char* version = "Moxa C101 driver version: 1.15";
  35 static const char* devname = "C101";
  36
  37 #undef DEBUG_PKT
  38 #define DEBUG_RINGS
  39
  40 #define C101_PAGE 0x1D00
  41 #define C101_DTR 0x1E00
  42 #define C101_SCA 0x1F00
  43 #define C101_WINDOW_SIZE 0x2000
  44 #define C101_MAPPED_RAM_SIZE 0x4000
  45
  46 #define RAM_SIZE (256 * 1024)
  47 #define TX_RING_BUFFERS 10
  48 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) /                \
  49                          (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
  50
  51 #define CLOCK_BASE 9830400      /* 9.8304 MHz */
  52 #define PAGE0_ALWAYS_MAPPED
  53
  54 static char *hw;                /* pointer to hw=xxx command line string */
  55
  56
  57 typedef struct card_s {
  58         struct net_device *dev;
  59         spinlock_t lock;        /* TX lock */
  60         u8 __iomem *win0base;   /* ISA window base address */
  61         u32 phy_winbase;        /* ISA physical base address */
  62         sync_serial_settings settings;
  63         int rxpart;             /* partial frame received, next frame invalid*/
  64         unsigned short encoding;
  65         unsigned short parity;
  66         u16 rx_ring_buffers;    /* number of buffers in a ring */
  67         u16 tx_ring_buffers;
  68         u16 buff_offset;        /* offset of first buffer of first channel */
  69         u16 rxin;               /* rx ring buffer 'in' pointer */
  70         u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
  71         u16 txlast;
  72         u8 rxs, txs, tmc;       /* SCA registers */
  73         u8 irq;                 /* IRQ (3-15) */
  74         u8 page;
  75
  76         struct card_s *next_card;
  77 }card_t;
  78
  79 typedef card_t port_t;
  80
  81 static card_t *first_card;
  82 static card_t **new_card = &first_card;
  83
  84
  85 #define sca_in(reg, card)          readb((card)->win0base + C101_SCA + (reg))
  86 #define sca_out(value, reg, card)  writeb(value, (card)->win0base + C101_SCA + (reg))
  87 #define sca_inw(reg, card)         readw((card)->win0base + C101_SCA + (reg))
  88
  89 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
  90 #define sca_outw(value, reg, card) do { \
  91         writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
  92         writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg + 1));\
  93 } while(0)
  94
  95 #define port_to_card(port)         (port)
  96 #define log_node(port)             (0)
  97 #define phy_node(port)             (0)
  98 #define winsize(card)              (C101_WINDOW_SIZE)
  99 #define win0base(card)             ((card)->win0base)
 100 #define winbase(card)              ((card)->win0base + 0x2000)
 101 #define get_port(card, port)       (card)
 102 static void sca_msci_intr(port_t *port);
 103
 104
 105 static inline u8 sca_get_page(card_t *card)
 106 {
 107         return card->page;
 108 }
 109
 110 static inline void openwin(card_t *card, u8 page)
 111 {
 112         card->page = page;
 113         writeb(page, card->win0base + C101_PAGE);
 114 }
 115
 116
 117 #include "hd64570.c"
 118
 119
 120 static inline void set_carrier(port_t *port)
 121 {
 122         if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))
 123                 netif_carrier_on(port_to_dev(port));
 124         else
 125                 netif_carrier_off(port_to_dev(port));
 126 }
 127
 128
 129 static void sca_msci_intr(port_t *port)
 130 {
 131         u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */
 132
 133         /* Reset MSCI TX underrun and CDCD (ignored) status bit */
 134         sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);
 135
 136         if (stat & ST1_UDRN) {
 137                 /* TX Underrun error detected */
 138                 port_to_dev(port)->stats.tx_errors++;
 139                 port_to_dev(port)->stats.tx_fifo_errors++;
 140         }
 141
 142         stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
 143         /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
 144         sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
 145
 146         if (stat & ST1_CDCD)
 147                 set_carrier(port);
 148 }
 149
 150
 151 static void c101_set_iface(port_t *port)
 152 {
 153         u8 rxs = port->rxs & CLK_BRG_MASK;
 154         u8 txs = port->txs & CLK_BRG_MASK;
 155
 156         switch(port->settings.clock_type) {
 157         case CLOCK_INT:
 158                 rxs |= CLK_BRG_RX; /* TX clock */
 159                 txs |= CLK_RXCLK_TX; /* BRG output */
 160                 break;
 161
 162         case CLOCK_TXINT:
 163                 rxs |= CLK_LINE_RX; /* RXC input */
 164                 txs |= CLK_BRG_TX; /* BRG output */
 165                 break;
 166
 167         case CLOCK_TXFROMRX:
 168                 rxs |= CLK_LINE_RX; /* RXC input */
 169                 txs |= CLK_RXCLK_TX; /* RX clock */
 170                 break;
 171
 172         default:        /* EXTernal clock */
 173                 rxs |= CLK_LINE_RX; /* RXC input */
 174                 txs |= CLK_LINE_TX; /* TXC input */
 175         }
 176
 177         port->rxs = rxs;
 178         port->txs = txs;
 179         sca_out(rxs, MSCI1_OFFSET + RXS, port);
 180         sca_out(txs, MSCI1_OFFSET + TXS, port);
 181         sca_set_port(port);
 182 }
 183
 184
 185 static int c101_open(struct net_device *dev)
 186 {
 187         port_t *port = dev_to_port(dev);
 188         int result;
 189
 190         result = hdlc_open(dev);
 191         if (result)
 192                 return result;
 193
 194         writeb(1, port->win0base + C101_DTR);
 195         sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
 196         sca_open(dev);
 197         /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
 198         sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
 199         sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
 200
 201         set_carrier(port);
 202
 203         /* enable MSCI1 CDCD interrupt */
 204         sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
 205         sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
 206         sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
 207         c101_set_iface(port);
 208         return 0;
 209 }
 210
 211
 212 static int c101_close(struct net_device *dev)
 213 {
 214         port_t *port = dev_to_port(dev);
 215
 216         sca_close(dev);
 217         writeb(0, port->win0base + C101_DTR);
 218         sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
 219         hdlc_close(dev);
 220         return 0;
 221 }
 222
 223
 224 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 225 {
 226         const size_t size = sizeof(sync_serial_settings);
 227         sync_serial_settings new_line;
 228         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 229         port_t *port = dev_to_port(dev);
 230
 231 #ifdef DEBUG_RINGS
 232         if (cmd == SIOCDEVPRIVATE) {
 233                 sca_dump_rings(dev);
 234                 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
 235                        sca_in(MSCI1_OFFSET + ST0, port),
 236                        sca_in(MSCI1_OFFSET + ST1, port),
 237                        sca_in(MSCI1_OFFSET + ST2, port),
 238                        sca_in(MSCI1_OFFSET + ST3, port));
 239                 return 0;
 240         }
 241 #endif
 242         if (cmd != SIOCWANDEV)
 243                 return hdlc_ioctl(dev, ifr, cmd);
 244
 245         switch(ifr->ifr_settings.type) {
 246         case IF_GET_IFACE:
 247                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
 248                 if (ifr->ifr_settings.size < size) {
 249                         ifr->ifr_settings.size = size; /* data size wanted */
 250                         return -ENOBUFS;
 251                 }
 252                 if (copy_to_user(line, &port->settings, size))
 253                         return -EFAULT;
 254                 return 0;
 255
 256         case IF_IFACE_SYNC_SERIAL:
 257                 if(!capable(CAP_NET_ADMIN))
 258                         return -EPERM;
 259
 260                 if (copy_from_user(&new_line, line, size))
 261                         return -EFAULT;
 262
 263                 if (new_line.clock_type != CLOCK_EXT &&
 264                     new_line.clock_type != CLOCK_TXFROMRX &&
 265                     new_line.clock_type != CLOCK_INT &&
 266                     new_line.clock_type != CLOCK_TXINT)
 267                         return -EINVAL; /* No such clock setting */
 268
 269                 if (new_line.loopback != 0 && new_line.loopback != 1)
 270                         return -EINVAL;
 271
 272                 memcpy(&port->settings, &new_line, size); /* Update settings */
 273                 c101_set_iface(port);
 274                 return 0;
 275
 276         default:
 277                 return hdlc_ioctl(dev, ifr, cmd);
 278         }
 279 }
 280
 281
 282
 283 static void c101_destroy_card(card_t *card)
 284 {
 285         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 286
 287         if (card->irq)
 288                 free_irq(card->irq, card);
 289
 290         if (card->win0base) {
 291                 iounmap(card->win0base);
 292                 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
 293         }
 294
 295         free_netdev(card->dev);
 296
 297         kfree(card);
 298 }
 299
 300 static const struct net_device_ops c101_ops = {
 301         .ndo_open       = c101_open,
 302         .ndo_stop       = c101_close,
 303         .ndo_change_mtu = hdlc_change_mtu,
 304         .ndo_start_xmit = hdlc_start_xmit,
 305         .ndo_do_ioctl   = c101_ioctl,
 306 };
 307
 308 static int __init c101_run(unsigned long irq, unsigned long winbase)
 309 {
 310         struct net_device *dev;
 311         hdlc_device *hdlc;
 312         card_t *card;
 313         int result;
 314
 315         if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
 316                 printk(KERN_ERR "c101: invalid IRQ value\n");
 317                 return -ENODEV;
 318         }
 319
 320         if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
 321                 printk(KERN_ERR "c101: invalid RAM value\n");
 322                 return -ENODEV;
 323         }
 324
 325         card = kzalloc(sizeof(card_t), GFP_KERNEL);
 326         if (card == NULL) {
 327                 printk(KERN_ERR "c101: unable to allocate memory\n");
 328                 return -ENOBUFS;
 329         }
 330
 331         card->dev = alloc_hdlcdev(card);
 332         if (!card->dev) {
 333                 printk(KERN_ERR "c101: unable to allocate memory\n");
 334                 kfree(card);
 335                 return -ENOBUFS;
 336         }
 337
 338         if (request_irq(irq, sca_intr, 0, devname, card)) {
 339                 printk(KERN_ERR "c101: could not allocate IRQ\n");
 340                 c101_destroy_card(card);
 341                 return -EBUSY;
 342         }
 343         card->irq = irq;
 344
 345         if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
 346                 printk(KERN_ERR "c101: could not request RAM window\n");
 347                 c101_destroy_card(card);
 348                 return -EBUSY;
 349         }
 350         card->phy_winbase = winbase;
 351         card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
 352         if (!card->win0base) {
 353                 printk(KERN_ERR "c101: could not map I/O address\n");
 354                 c101_destroy_card(card);
 355                 return -EFAULT;
 356         }
 357
 358         card->tx_ring_buffers = TX_RING_BUFFERS;
 359         card->rx_ring_buffers = RX_RING_BUFFERS;
 360         card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
 361
 362         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 363         udelay(100);
 364         writeb(0, card->win0base + C101_PAGE);
 365         writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
 366
 367         sca_init(card, 0);
 368
 369         dev = port_to_dev(card);
 370         hdlc = dev_to_hdlc(dev);
 371
 372         spin_lock_init(&card->lock);
 373         dev->irq = irq;
 374         dev->mem_start = winbase;
 375         dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
 376         dev->tx_queue_len = 50;
 377         dev->netdev_ops = &c101_ops;
 378         hdlc->attach = sca_attach;
 379         hdlc->xmit = sca_xmit;
 380         card->settings.clock_type = CLOCK_EXT;
 381
 382         result = register_hdlc_device(dev);
 383         if (result) {
 384                 printk(KERN_WARNING "c101: unable to register hdlc device\n");
 385                 c101_destroy_card(card);
 386                 return result;
 387         }
 388
 389         sca_init_port(card); /* Set up C101 memory */
 390         set_carrier(card);
 391
 392         printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
 393                " using %u TX + %u RX packets rings\n",
 394                dev->name, card->irq,
 395                card->tx_ring_buffers, card->rx_ring_buffers);
 396
 397         *new_card = card;
 398         new_card = &card->next_card;
 399         return 0;
 400 }
 401
 402
 403
 404 static int __init c101_init(void)
 405 {
 406         if (hw == NULL) {
 407 #ifdef MODULE
 408                 printk(KERN_INFO "c101: no card initialized\n");
 409 #endif
 410                 return -EINVAL; /* no parameters specified, abort */
 411         }
 412
 413         printk(KERN_INFO "%s\n", version);
 414
 415         do {
 416                 unsigned long irq, ram;
 417
 418                 irq = simple_strtoul(hw, &hw, 0);
 419
 420                 if (*hw++ != ',')
 421                         break;
 422                 ram = simple_strtoul(hw, &hw, 0);
 423
 424                 if (*hw == ':' || *hw == '\x0')
 425                         c101_run(irq, ram);
 426
 427                 if (*hw == '\x0')
 428                         return first_card ? 0 : -EINVAL;
 429         }while(*hw++ == ':');
 430
 431         printk(KERN_ERR "c101: invalid hardware parameters\n");
 432         return first_card ? 0 : -EINVAL;
 433 }
 434
 435
 436 static void __exit c101_cleanup(void)
 437 {
 438         card_t *card = first_card;
 439
 440         while (card) {
 441                 card_t *ptr = card;
 442                 card = card->next_card;
 443                 unregister_hdlc_device(port_to_dev(ptr));
 444                 c101_destroy_card(ptr);
 445         }
 446 }
 447
 448
 449 module_init(c101_init);
 450 module_exit(c101_cleanup);
 451
 452 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 453 MODULE_DESCRIPTION("Moxa C101 serial port driver");
 454 MODULE_LICENSE("GPL v2");
 455 module_param(hw, charp, 0444);
 456 MODULE_PARM_DESC(hw, "irq,ram:irq,...");