ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / spi / atmel_spi.c
blob08711e9202ab41cc38a4a512d3eb0c40b11663db
1 /*
2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
23 #include <asm/io.h>
24 #include <mach/board.h>
25 #include <mach/gpio.h>
26 #include <mach/cpu.h>
28 #include "atmel_spi.h"
31 * The core SPI transfer engine just talks to a register bank to set up
32 * DMA transfers; transfer queue progress is driven by IRQs. The clock
33 * framework provides the base clock, subdivided for each spi_device.
35 struct atmel_spi {
36 spinlock_t lock;
38 void __iomem *regs;
39 int irq;
40 struct clk *clk;
41 struct platform_device *pdev;
42 struct spi_device *stay;
44 u8 stopping;
45 struct list_head queue;
46 struct spi_transfer *current_transfer;
47 unsigned long current_remaining_bytes;
48 struct spi_transfer *next_transfer;
49 unsigned long next_remaining_bytes;
51 void *buffer;
52 dma_addr_t buffer_dma;
55 /* Controller-specific per-slave state */
56 struct atmel_spi_device {
57 unsigned int npcs_pin;
58 u32 csr;
61 #define BUFFER_SIZE PAGE_SIZE
62 #define INVALID_DMA_ADDRESS 0xffffffff
65 * Version 2 of the SPI controller has
66 * - CR.LASTXFER
67 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
68 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
69 * - SPI_CSRx.CSAAT
70 * - SPI_CSRx.SBCR allows faster clocking
72 * We can determine the controller version by reading the VERSION
73 * register, but I haven't checked that it exists on all chips, and
74 * this is cheaper anyway.
76 static bool atmel_spi_is_v2(void)
78 return !cpu_is_at91rm9200();
82 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
83 * they assume that spi slave device state will not change on deselect, so
84 * that automagic deselection is OK. ("NPCSx rises if no data is to be
85 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
86 * controllers have CSAAT and friends.
88 * Since the CSAAT functionality is a bit weird on newer controllers as
89 * well, we use GPIO to control nCSx pins on all controllers, updating
90 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
91 * support active-high chipselects despite the controller's belief that
92 * only active-low devices/systems exists.
94 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
95 * right when driven with GPIO. ("Mode Fault does not allow more than one
96 * Master on Chip Select 0.") No workaround exists for that ... so for
97 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
98 * and (c) will trigger that first erratum in some cases.
100 * TODO: Test if the atmel_spi_is_v2() branch below works on
101 * AT91RM9200 if we use some other register than CSR0. However, don't
102 * do this unconditionally since AP7000 has an errata where the BITS
103 * field in CSR0 overrides all other CSRs.
106 static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
108 struct atmel_spi_device *asd = spi->controller_state;
109 unsigned active = spi->mode & SPI_CS_HIGH;
110 u32 mr;
112 if (atmel_spi_is_v2()) {
114 * Always use CSR0. This ensures that the clock
115 * switches to the correct idle polarity before we
116 * toggle the CS.
118 spi_writel(as, CSR0, asd->csr);
119 spi_writel(as, MR, SPI_BF(PCS, 0x0e) | SPI_BIT(MODFDIS)
120 | SPI_BIT(MSTR));
121 mr = spi_readl(as, MR);
122 gpio_set_value(asd->npcs_pin, active);
123 } else {
124 u32 cpol = (spi->mode & SPI_CPOL) ? SPI_BIT(CPOL) : 0;
125 int i;
126 u32 csr;
128 /* Make sure clock polarity is correct */
129 for (i = 0; i < spi->master->num_chipselect; i++) {
130 csr = spi_readl(as, CSR0 + 4 * i);
131 if ((csr ^ cpol) & SPI_BIT(CPOL))
132 spi_writel(as, CSR0 + 4 * i,
133 csr ^ SPI_BIT(CPOL));
136 mr = spi_readl(as, MR);
137 mr = SPI_BFINS(PCS, ~(1 << spi->chip_select), mr);
138 if (spi->chip_select != 0)
139 gpio_set_value(asd->npcs_pin, active);
140 spi_writel(as, MR, mr);
143 dev_dbg(&spi->dev, "activate %u%s, mr %08x\n",
144 asd->npcs_pin, active ? " (high)" : "",
145 mr);
148 static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
150 struct atmel_spi_device *asd = spi->controller_state;
151 unsigned active = spi->mode & SPI_CS_HIGH;
152 u32 mr;
154 /* only deactivate *this* device; sometimes transfers to
155 * another device may be active when this routine is called.
157 mr = spi_readl(as, MR);
158 if (~SPI_BFEXT(PCS, mr) & (1 << spi->chip_select)) {
159 mr = SPI_BFINS(PCS, 0xf, mr);
160 spi_writel(as, MR, mr);
163 dev_dbg(&spi->dev, "DEactivate %u%s, mr %08x\n",
164 asd->npcs_pin, active ? " (low)" : "",
165 mr);
167 if (atmel_spi_is_v2() || spi->chip_select != 0)
168 gpio_set_value(asd->npcs_pin, !active);
171 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
172 struct spi_transfer *xfer)
174 return msg->transfers.prev == &xfer->transfer_list;
177 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
179 return xfer->delay_usecs == 0 && !xfer->cs_change;
182 static void atmel_spi_next_xfer_data(struct spi_master *master,
183 struct spi_transfer *xfer,
184 dma_addr_t *tx_dma,
185 dma_addr_t *rx_dma,
186 u32 *plen)
188 struct atmel_spi *as = spi_master_get_devdata(master);
189 u32 len = *plen;
191 /* use scratch buffer only when rx or tx data is unspecified */
192 if (xfer->rx_buf)
193 *rx_dma = xfer->rx_dma + xfer->len - *plen;
194 else {
195 *rx_dma = as->buffer_dma;
196 if (len > BUFFER_SIZE)
197 len = BUFFER_SIZE;
199 if (xfer->tx_buf)
200 *tx_dma = xfer->tx_dma + xfer->len - *plen;
201 else {
202 *tx_dma = as->buffer_dma;
203 if (len > BUFFER_SIZE)
204 len = BUFFER_SIZE;
205 memset(as->buffer, 0, len);
206 dma_sync_single_for_device(&as->pdev->dev,
207 as->buffer_dma, len, DMA_TO_DEVICE);
210 *plen = len;
214 * Submit next transfer for DMA.
215 * lock is held, spi irq is blocked
217 static void atmel_spi_next_xfer(struct spi_master *master,
218 struct spi_message *msg)
220 struct atmel_spi *as = spi_master_get_devdata(master);
221 struct spi_transfer *xfer;
222 u32 len, remaining;
223 u32 ieval;
224 dma_addr_t tx_dma, rx_dma;
226 if (!as->current_transfer)
227 xfer = list_entry(msg->transfers.next,
228 struct spi_transfer, transfer_list);
229 else if (!as->next_transfer)
230 xfer = list_entry(as->current_transfer->transfer_list.next,
231 struct spi_transfer, transfer_list);
232 else
233 xfer = NULL;
235 if (xfer) {
236 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
238 len = xfer->len;
239 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
240 remaining = xfer->len - len;
242 spi_writel(as, RPR, rx_dma);
243 spi_writel(as, TPR, tx_dma);
245 if (msg->spi->bits_per_word > 8)
246 len >>= 1;
247 spi_writel(as, RCR, len);
248 spi_writel(as, TCR, len);
250 dev_dbg(&msg->spi->dev,
251 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
252 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
253 xfer->rx_buf, xfer->rx_dma);
254 } else {
255 xfer = as->next_transfer;
256 remaining = as->next_remaining_bytes;
259 as->current_transfer = xfer;
260 as->current_remaining_bytes = remaining;
262 if (remaining > 0)
263 len = remaining;
264 else if (!atmel_spi_xfer_is_last(msg, xfer)
265 && atmel_spi_xfer_can_be_chained(xfer)) {
266 xfer = list_entry(xfer->transfer_list.next,
267 struct spi_transfer, transfer_list);
268 len = xfer->len;
269 } else
270 xfer = NULL;
272 as->next_transfer = xfer;
274 if (xfer) {
275 u32 total;
277 total = len;
278 atmel_spi_next_xfer_data(master, xfer, &tx_dma, &rx_dma, &len);
279 as->next_remaining_bytes = total - len;
281 spi_writel(as, RNPR, rx_dma);
282 spi_writel(as, TNPR, tx_dma);
284 if (msg->spi->bits_per_word > 8)
285 len >>= 1;
286 spi_writel(as, RNCR, len);
287 spi_writel(as, TNCR, len);
289 dev_dbg(&msg->spi->dev,
290 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
291 xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
292 xfer->rx_buf, xfer->rx_dma);
293 ieval = SPI_BIT(ENDRX) | SPI_BIT(OVRES);
294 } else {
295 spi_writel(as, RNCR, 0);
296 spi_writel(as, TNCR, 0);
297 ieval = SPI_BIT(RXBUFF) | SPI_BIT(ENDRX) | SPI_BIT(OVRES);
300 /* REVISIT: We're waiting for ENDRX before we start the next
301 * transfer because we need to handle some difficult timing
302 * issues otherwise. If we wait for ENDTX in one transfer and
303 * then starts waiting for ENDRX in the next, it's difficult
304 * to tell the difference between the ENDRX interrupt we're
305 * actually waiting for and the ENDRX interrupt of the
306 * previous transfer.
308 * It should be doable, though. Just not now...
310 spi_writel(as, IER, ieval);
311 spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
314 static void atmel_spi_next_message(struct spi_master *master)
316 struct atmel_spi *as = spi_master_get_devdata(master);
317 struct spi_message *msg;
318 struct spi_device *spi;
320 BUG_ON(as->current_transfer);
322 msg = list_entry(as->queue.next, struct spi_message, queue);
323 spi = msg->spi;
325 dev_dbg(master->dev.parent, "start message %p for %s\n",
326 msg, dev_name(&spi->dev));
328 /* select chip if it's not still active */
329 if (as->stay) {
330 if (as->stay != spi) {
331 cs_deactivate(as, as->stay);
332 cs_activate(as, spi);
334 as->stay = NULL;
335 } else
336 cs_activate(as, spi);
338 atmel_spi_next_xfer(master, msg);
342 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
343 * - The buffer is either valid for CPU access, else NULL
344 * - If the buffer is valid, so is its DMA address
346 * This driver manages the dma address unless message->is_dma_mapped.
348 static int
349 atmel_spi_dma_map_xfer(struct atmel_spi *as, struct spi_transfer *xfer)
351 struct device *dev = &as->pdev->dev;
353 xfer->tx_dma = xfer->rx_dma = INVALID_DMA_ADDRESS;
354 if (xfer->tx_buf) {
355 /* tx_buf is a const void* where we need a void * for the dma
356 * mapping */
357 void *nonconst_tx = (void *)xfer->tx_buf;
359 xfer->tx_dma = dma_map_single(dev,
360 nonconst_tx, xfer->len,
361 DMA_TO_DEVICE);
362 if (dma_mapping_error(dev, xfer->tx_dma))
363 return -ENOMEM;
365 if (xfer->rx_buf) {
366 xfer->rx_dma = dma_map_single(dev,
367 xfer->rx_buf, xfer->len,
368 DMA_FROM_DEVICE);
369 if (dma_mapping_error(dev, xfer->rx_dma)) {
370 if (xfer->tx_buf)
371 dma_unmap_single(dev,
372 xfer->tx_dma, xfer->len,
373 DMA_TO_DEVICE);
374 return -ENOMEM;
377 return 0;
380 static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
381 struct spi_transfer *xfer)
383 if (xfer->tx_dma != INVALID_DMA_ADDRESS)
384 dma_unmap_single(master->dev.parent, xfer->tx_dma,
385 xfer->len, DMA_TO_DEVICE);
386 if (xfer->rx_dma != INVALID_DMA_ADDRESS)
387 dma_unmap_single(master->dev.parent, xfer->rx_dma,
388 xfer->len, DMA_FROM_DEVICE);
391 static void
392 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
393 struct spi_message *msg, int status, int stay)
395 if (!stay || status < 0)
396 cs_deactivate(as, msg->spi);
397 else
398 as->stay = msg->spi;
400 list_del(&msg->queue);
401 msg->status = status;
403 dev_dbg(master->dev.parent,
404 "xfer complete: %u bytes transferred\n",
405 msg->actual_length);
407 spin_unlock(&as->lock);
408 msg->complete(msg->context);
409 spin_lock(&as->lock);
411 as->current_transfer = NULL;
412 as->next_transfer = NULL;
414 /* continue if needed */
415 if (list_empty(&as->queue) || as->stopping)
416 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
417 else
418 atmel_spi_next_message(master);
421 static irqreturn_t
422 atmel_spi_interrupt(int irq, void *dev_id)
424 struct spi_master *master = dev_id;
425 struct atmel_spi *as = spi_master_get_devdata(master);
426 struct spi_message *msg;
427 struct spi_transfer *xfer;
428 u32 status, pending, imr;
429 int ret = IRQ_NONE;
431 spin_lock(&as->lock);
433 xfer = as->current_transfer;
434 msg = list_entry(as->queue.next, struct spi_message, queue);
436 imr = spi_readl(as, IMR);
437 status = spi_readl(as, SR);
438 pending = status & imr;
440 if (pending & SPI_BIT(OVRES)) {
441 int timeout;
443 ret = IRQ_HANDLED;
445 spi_writel(as, IDR, (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX)
446 | SPI_BIT(OVRES)));
449 * When we get an overrun, we disregard the current
450 * transfer. Data will not be copied back from any
451 * bounce buffer and msg->actual_len will not be
452 * updated with the last xfer.
454 * We will also not process any remaning transfers in
455 * the message.
457 * First, stop the transfer and unmap the DMA buffers.
459 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
460 if (!msg->is_dma_mapped)
461 atmel_spi_dma_unmap_xfer(master, xfer);
463 /* REVISIT: udelay in irq is unfriendly */
464 if (xfer->delay_usecs)
465 udelay(xfer->delay_usecs);
467 dev_warn(master->dev.parent, "overrun (%u/%u remaining)\n",
468 spi_readl(as, TCR), spi_readl(as, RCR));
471 * Clean up DMA registers and make sure the data
472 * registers are empty.
474 spi_writel(as, RNCR, 0);
475 spi_writel(as, TNCR, 0);
476 spi_writel(as, RCR, 0);
477 spi_writel(as, TCR, 0);
478 for (timeout = 1000; timeout; timeout--)
479 if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))
480 break;
481 if (!timeout)
482 dev_warn(master->dev.parent,
483 "timeout waiting for TXEMPTY");
484 while (spi_readl(as, SR) & SPI_BIT(RDRF))
485 spi_readl(as, RDR);
487 /* Clear any overrun happening while cleaning up */
488 spi_readl(as, SR);
490 atmel_spi_msg_done(master, as, msg, -EIO, 0);
491 } else if (pending & (SPI_BIT(RXBUFF) | SPI_BIT(ENDRX))) {
492 ret = IRQ_HANDLED;
494 spi_writel(as, IDR, pending);
496 if (as->current_remaining_bytes == 0) {
497 msg->actual_length += xfer->len;
499 if (!msg->is_dma_mapped)
500 atmel_spi_dma_unmap_xfer(master, xfer);
502 /* REVISIT: udelay in irq is unfriendly */
503 if (xfer->delay_usecs)
504 udelay(xfer->delay_usecs);
506 if (atmel_spi_xfer_is_last(msg, xfer)) {
507 /* report completed message */
508 atmel_spi_msg_done(master, as, msg, 0,
509 xfer->cs_change);
510 } else {
511 if (xfer->cs_change) {
512 cs_deactivate(as, msg->spi);
513 udelay(1);
514 cs_activate(as, msg->spi);
518 * Not done yet. Submit the next transfer.
520 * FIXME handle protocol options for xfer
522 atmel_spi_next_xfer(master, msg);
524 } else {
526 * Keep going, we still have data to send in
527 * the current transfer.
529 atmel_spi_next_xfer(master, msg);
533 spin_unlock(&as->lock);
535 return ret;
538 static int atmel_spi_setup(struct spi_device *spi)
540 struct atmel_spi *as;
541 struct atmel_spi_device *asd;
542 u32 scbr, csr;
543 unsigned int bits = spi->bits_per_word;
544 unsigned long bus_hz;
545 unsigned int npcs_pin;
546 int ret;
548 as = spi_master_get_devdata(spi->master);
550 if (as->stopping)
551 return -ESHUTDOWN;
553 if (spi->chip_select > spi->master->num_chipselect) {
554 dev_dbg(&spi->dev,
555 "setup: invalid chipselect %u (%u defined)\n",
556 spi->chip_select, spi->master->num_chipselect);
557 return -EINVAL;
560 if (bits < 8 || bits > 16) {
561 dev_dbg(&spi->dev,
562 "setup: invalid bits_per_word %u (8 to 16)\n",
563 bits);
564 return -EINVAL;
567 /* see notes above re chipselect */
568 if (!atmel_spi_is_v2()
569 && spi->chip_select == 0
570 && (spi->mode & SPI_CS_HIGH)) {
571 dev_dbg(&spi->dev, "setup: can't be active-high\n");
572 return -EINVAL;
575 /* v1 chips start out at half the peripheral bus speed. */
576 bus_hz = clk_get_rate(as->clk);
577 if (!atmel_spi_is_v2())
578 bus_hz /= 2;
580 if (spi->max_speed_hz) {
582 * Calculate the lowest divider that satisfies the
583 * constraint, assuming div32/fdiv/mbz == 0.
585 scbr = DIV_ROUND_UP(bus_hz, spi->max_speed_hz);
588 * If the resulting divider doesn't fit into the
589 * register bitfield, we can't satisfy the constraint.
591 if (scbr >= (1 << SPI_SCBR_SIZE)) {
592 dev_dbg(&spi->dev,
593 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
594 spi->max_speed_hz, scbr, bus_hz/255);
595 return -EINVAL;
597 } else
598 /* speed zero means "as slow as possible" */
599 scbr = 0xff;
601 csr = SPI_BF(SCBR, scbr) | SPI_BF(BITS, bits - 8);
602 if (spi->mode & SPI_CPOL)
603 csr |= SPI_BIT(CPOL);
604 if (!(spi->mode & SPI_CPHA))
605 csr |= SPI_BIT(NCPHA);
607 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
609 * DLYBCT would add delays between words, slowing down transfers.
610 * It could potentially be useful to cope with DMA bottlenecks, but
611 * in those cases it's probably best to just use a lower bitrate.
613 csr |= SPI_BF(DLYBS, 0);
614 csr |= SPI_BF(DLYBCT, 0);
616 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
617 npcs_pin = (unsigned int)spi->controller_data;
618 asd = spi->controller_state;
619 if (!asd) {
620 asd = kzalloc(sizeof(struct atmel_spi_device), GFP_KERNEL);
621 if (!asd)
622 return -ENOMEM;
624 ret = gpio_request(npcs_pin, dev_name(&spi->dev));
625 if (ret) {
626 kfree(asd);
627 return ret;
630 asd->npcs_pin = npcs_pin;
631 spi->controller_state = asd;
632 gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
633 } else {
634 unsigned long flags;
636 spin_lock_irqsave(&as->lock, flags);
637 if (as->stay == spi)
638 as->stay = NULL;
639 cs_deactivate(as, spi);
640 spin_unlock_irqrestore(&as->lock, flags);
643 asd->csr = csr;
645 dev_dbg(&spi->dev,
646 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
647 bus_hz / scbr, bits, spi->mode, spi->chip_select, csr);
649 if (!atmel_spi_is_v2())
650 spi_writel(as, CSR0 + 4 * spi->chip_select, csr);
652 return 0;
655 static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
657 struct atmel_spi *as;
658 struct spi_transfer *xfer;
659 unsigned long flags;
660 struct device *controller = spi->master->dev.parent;
661 u8 bits;
662 struct atmel_spi_device *asd;
664 as = spi_master_get_devdata(spi->master);
666 dev_dbg(controller, "new message %p submitted for %s\n",
667 msg, dev_name(&spi->dev));
669 if (unlikely(list_empty(&msg->transfers)))
670 return -EINVAL;
672 if (as->stopping)
673 return -ESHUTDOWN;
675 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
676 if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) {
677 dev_dbg(&spi->dev, "missing rx or tx buf\n");
678 return -EINVAL;
681 if (xfer->bits_per_word) {
682 asd = spi->controller_state;
683 bits = (asd->csr >> 4) & 0xf;
684 if (bits != xfer->bits_per_word - 8) {
685 dev_dbg(&spi->dev, "you can't yet change "
686 "bits_per_word in transfers\n");
687 return -ENOPROTOOPT;
691 /* FIXME implement these protocol options!! */
692 if (xfer->speed_hz) {
693 dev_dbg(&spi->dev, "no protocol options yet\n");
694 return -ENOPROTOOPT;
698 * DMA map early, for performance (empties dcache ASAP) and
699 * better fault reporting. This is a DMA-only driver.
701 * NOTE that if dma_unmap_single() ever starts to do work on
702 * platforms supported by this driver, we would need to clean
703 * up mappings for previously-mapped transfers.
705 if (!msg->is_dma_mapped) {
706 if (atmel_spi_dma_map_xfer(as, xfer) < 0)
707 return -ENOMEM;
711 #ifdef VERBOSE
712 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
713 dev_dbg(controller,
714 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
715 xfer, xfer->len,
716 xfer->tx_buf, xfer->tx_dma,
717 xfer->rx_buf, xfer->rx_dma);
719 #endif
721 msg->status = -EINPROGRESS;
722 msg->actual_length = 0;
724 spin_lock_irqsave(&as->lock, flags);
725 list_add_tail(&msg->queue, &as->queue);
726 if (!as->current_transfer)
727 atmel_spi_next_message(spi->master);
728 spin_unlock_irqrestore(&as->lock, flags);
730 return 0;
733 static void atmel_spi_cleanup(struct spi_device *spi)
735 struct atmel_spi *as = spi_master_get_devdata(spi->master);
736 struct atmel_spi_device *asd = spi->controller_state;
737 unsigned gpio = (unsigned) spi->controller_data;
738 unsigned long flags;
740 if (!asd)
741 return;
743 spin_lock_irqsave(&as->lock, flags);
744 if (as->stay == spi) {
745 as->stay = NULL;
746 cs_deactivate(as, spi);
748 spin_unlock_irqrestore(&as->lock, flags);
750 spi->controller_state = NULL;
751 gpio_free(gpio);
752 kfree(asd);
755 /*-------------------------------------------------------------------------*/
757 static int __init atmel_spi_probe(struct platform_device *pdev)
759 struct resource *regs;
760 int irq;
761 struct clk *clk;
762 int ret;
763 struct spi_master *master;
764 struct atmel_spi *as;
766 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
767 if (!regs)
768 return -ENXIO;
770 irq = platform_get_irq(pdev, 0);
771 if (irq < 0)
772 return irq;
774 clk = clk_get(&pdev->dev, "spi_clk");
775 if (IS_ERR(clk))
776 return PTR_ERR(clk);
778 /* setup spi core then atmel-specific driver state */
779 ret = -ENOMEM;
780 master = spi_alloc_master(&pdev->dev, sizeof *as);
781 if (!master)
782 goto out_free;
784 /* the spi->mode bits understood by this driver: */
785 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
787 master->bus_num = pdev->id;
788 master->num_chipselect = 4;
789 master->setup = atmel_spi_setup;
790 master->transfer = atmel_spi_transfer;
791 master->cleanup = atmel_spi_cleanup;
792 platform_set_drvdata(pdev, master);
794 as = spi_master_get_devdata(master);
797 * Scratch buffer is used for throwaway rx and tx data.
798 * It's coherent to minimize dcache pollution.
800 as->buffer = dma_alloc_coherent(&pdev->dev, BUFFER_SIZE,
801 &as->buffer_dma, GFP_KERNEL);
802 if (!as->buffer)
803 goto out_free;
805 spin_lock_init(&as->lock);
806 INIT_LIST_HEAD(&as->queue);
807 as->pdev = pdev;
808 as->regs = ioremap(regs->start, resource_size(regs));
809 if (!as->regs)
810 goto out_free_buffer;
811 as->irq = irq;
812 as->clk = clk;
814 ret = request_irq(irq, atmel_spi_interrupt, 0,
815 dev_name(&pdev->dev), master);
816 if (ret)
817 goto out_unmap_regs;
819 /* Initialize the hardware */
820 clk_enable(clk);
821 spi_writel(as, CR, SPI_BIT(SWRST));
822 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
823 spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
824 spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
825 spi_writel(as, CR, SPI_BIT(SPIEN));
827 /* go! */
828 dev_info(&pdev->dev, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
829 (unsigned long)regs->start, irq);
831 ret = spi_register_master(master);
832 if (ret)
833 goto out_reset_hw;
835 return 0;
837 out_reset_hw:
838 spi_writel(as, CR, SPI_BIT(SWRST));
839 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
840 clk_disable(clk);
841 free_irq(irq, master);
842 out_unmap_regs:
843 iounmap(as->regs);
844 out_free_buffer:
845 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
846 as->buffer_dma);
847 out_free:
848 clk_put(clk);
849 spi_master_put(master);
850 return ret;
853 static int __exit atmel_spi_remove(struct platform_device *pdev)
855 struct spi_master *master = platform_get_drvdata(pdev);
856 struct atmel_spi *as = spi_master_get_devdata(master);
857 struct spi_message *msg;
859 /* reset the hardware and block queue progress */
860 spin_lock_irq(&as->lock);
861 as->stopping = 1;
862 spi_writel(as, CR, SPI_BIT(SWRST));
863 spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
864 spi_readl(as, SR);
865 spin_unlock_irq(&as->lock);
867 /* Terminate remaining queued transfers */
868 list_for_each_entry(msg, &as->queue, queue) {
869 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
870 * but we shouldn't depend on that...
872 msg->status = -ESHUTDOWN;
873 msg->complete(msg->context);
876 dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
877 as->buffer_dma);
879 clk_disable(as->clk);
880 clk_put(as->clk);
881 free_irq(as->irq, master);
882 iounmap(as->regs);
884 spi_unregister_master(master);
886 return 0;
889 #ifdef CONFIG_PM
891 static int atmel_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
893 struct spi_master *master = platform_get_drvdata(pdev);
894 struct atmel_spi *as = spi_master_get_devdata(master);
896 clk_disable(as->clk);
897 return 0;
900 static int atmel_spi_resume(struct platform_device *pdev)
902 struct spi_master *master = platform_get_drvdata(pdev);
903 struct atmel_spi *as = spi_master_get_devdata(master);
905 clk_enable(as->clk);
906 return 0;
909 #else
910 #define atmel_spi_suspend NULL
911 #define atmel_spi_resume NULL
912 #endif
915 static struct platform_driver atmel_spi_driver = {
916 .driver = {
917 .name = "atmel_spi",
918 .owner = THIS_MODULE,
920 .suspend = atmel_spi_suspend,
921 .resume = atmel_spi_resume,
922 .remove = __exit_p(atmel_spi_remove),
925 static int __init atmel_spi_init(void)
927 return platform_driver_probe(&atmel_spi_driver, atmel_spi_probe);
929 module_init(atmel_spi_init);
931 static void __exit atmel_spi_exit(void)
933 platform_driver_unregister(&atmel_spi_driver);
935 module_exit(atmel_spi_exit);
937 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
938 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
939 MODULE_LICENSE("GPL");
940 MODULE_ALIAS("platform:atmel_spi");