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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / ssb / main.c
blobf8a13f86321742c9d3ca776369ca6019bb81963c
1 /*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11 #include "ssb_private.h"
12
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/ssb/ssb.h>
16 #include <linux/ssb/ssb_regs.h>
17 #include <linux/ssb/ssb_driver_gige.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/pci.h>
20 #include <linux/mmc/sdio_func.h>
21 #include <linux/slab.h>
22
23 #include <pcmcia/cistpl.h>
24 #include <pcmcia/ds.h>
25
26
27 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
28 MODULE_LICENSE("GPL");
29
30
31 /* Temporary list of yet-to-be-attached buses */
32 static LIST_HEAD(attach_queue);
33 /* List if running buses */
34 static LIST_HEAD(buses);
35 /* Software ID counter */
36 static unsigned int next_busnumber;
37 /* buses_mutes locks the two buslists and the next_busnumber.
38 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
39 static DEFINE_MUTEX(buses_mutex);
40
41 /* There are differences in the codeflow, if the bus is
42 * initialized from early boot, as various needed services
43 * are not available early. This is a mechanism to delay
44 * these initializations to after early boot has finished.
45 * It's also used to avoid mutex locking, as that's not
46 * available and needed early. */
47 static bool ssb_is_early_boot = 1;
48
49 static void ssb_buses_lock(void);
50 static void ssb_buses_unlock(void);
51
52
53 #ifdef CONFIG_SSB_PCIHOST
54 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
55 {
56 struct ssb_bus *bus;
57
58 ssb_buses_lock();
59 list_for_each_entry(bus, &buses, list) {
60 if (bus->bustype == SSB_BUSTYPE_PCI &&
61 bus->host_pci == pdev)
62 goto found;
63 }
64 bus = NULL;
65 found:
66 ssb_buses_unlock();
67
68 return bus;
69 }
70 #endif /* CONFIG_SSB_PCIHOST */
71
72 #ifdef CONFIG_SSB_PCMCIAHOST
73 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
74 {
75 struct ssb_bus *bus;
76
77 ssb_buses_lock();
78 list_for_each_entry(bus, &buses, list) {
79 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
80 bus->host_pcmcia == pdev)
81 goto found;
82 }
83 bus = NULL;
84 found:
85 ssb_buses_unlock();
86
87 return bus;
88 }
89 #endif /* CONFIG_SSB_PCMCIAHOST */
90
91 #ifdef CONFIG_SSB_SDIOHOST
92 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
93 {
94 struct ssb_bus *bus;
95
96 ssb_buses_lock();
97 list_for_each_entry(bus, &buses, list) {
98 if (bus->bustype == SSB_BUSTYPE_SDIO &&
99 bus->host_sdio == func)
100 goto found;
101 }
102 bus = NULL;
103 found:
104 ssb_buses_unlock();
105
106 return bus;
107 }
108 #endif /* CONFIG_SSB_SDIOHOST */
109
110 int ssb_for_each_bus_call(unsigned long data,
111 int (*func)(struct ssb_bus *bus, unsigned long data))
112 {
113 struct ssb_bus *bus;
114 int res;
115
116 ssb_buses_lock();
117 list_for_each_entry(bus, &buses, list) {
118 res = func(bus, data);
119 if (res >= 0) {
120 ssb_buses_unlock();
121 return res;
122 }
123 }
124 ssb_buses_unlock();
125
126 return -ENODEV;
127 }
128
129 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
130 {
131 if (dev)
132 get_device(dev->dev);
133 return dev;
134 }
135
136 static void ssb_device_put(struct ssb_device *dev)
137 {
138 if (dev)
139 put_device(dev->dev);
140 }
141
142 static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
143 {
144 if (drv)
145 get_driver(&drv->drv);
146 return drv;
147 }
148
149 static inline void ssb_driver_put(struct ssb_driver *drv)
150 {
151 if (drv)
152 put_driver(&drv->drv);
153 }
154
155 static int ssb_device_resume(struct device *dev)
156 {
157 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
158 struct ssb_driver *ssb_drv;
159 int err = 0;
160
161 if (dev->driver) {
162 ssb_drv = drv_to_ssb_drv(dev->driver);
163 if (ssb_drv && ssb_drv->resume)
164 err = ssb_drv->resume(ssb_dev);
165 if (err)
166 goto out;
167 }
168 out:
169 return err;
170 }
171
172 static int ssb_device_suspend(struct device *dev, pm_message_t state)
173 {
174 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
175 struct ssb_driver *ssb_drv;
176 int err = 0;
177
178 if (dev->driver) {
179 ssb_drv = drv_to_ssb_drv(dev->driver);
180 if (ssb_drv && ssb_drv->suspend)
181 err = ssb_drv->suspend(ssb_dev, state);
182 if (err)
183 goto out;
184 }
185 out:
186 return err;
187 }
188
189 int ssb_bus_resume(struct ssb_bus *bus)
190 {
191 int err;
192
193 /* Reset HW state information in memory, so that HW is
194 * completely reinitialized. */
195 bus->mapped_device = NULL;
196 #ifdef CONFIG_SSB_DRIVER_PCICORE
197 bus->pcicore.setup_done = 0;
198 #endif
199
200 err = ssb_bus_powerup(bus, 0);
201 if (err)
202 return err;
203 err = ssb_pcmcia_hardware_setup(bus);
204 if (err) {
205 ssb_bus_may_powerdown(bus);
206 return err;
207 }
208 ssb_chipco_resume(&bus->chipco);
209 ssb_bus_may_powerdown(bus);
210
211 return 0;
212 }
213 EXPORT_SYMBOL(ssb_bus_resume);
214
215 int ssb_bus_suspend(struct ssb_bus *bus)
216 {
217 ssb_chipco_suspend(&bus->chipco);
218 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
219
220 return 0;
221 }
222 EXPORT_SYMBOL(ssb_bus_suspend);
223
224 #ifdef CONFIG_SSB_SPROM
225 /** ssb_devices_freeze - Freeze all devices on the bus.
226 *
227 * After freezing no device driver will be handling a device
228 * on this bus anymore. ssb_devices_thaw() must be called after
229 * a successful freeze to reactivate the devices.
230 *
231 * @bus: The bus.
232 * @ctx: Context structure. Pass this to ssb_devices_thaw().
233 */
234 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
235 {
236 struct ssb_device *sdev;
237 struct ssb_driver *sdrv;
238 unsigned int i;
239
240 memset(ctx, 0, sizeof(*ctx));
241 ctx->bus = bus;
242 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
243
244 for (i = 0; i < bus->nr_devices; i++) {
245 sdev = ssb_device_get(&bus->devices[i]);
246
247 if (!sdev->dev || !sdev->dev->driver ||
248 !device_is_registered(sdev->dev)) {
249 ssb_device_put(sdev);
250 continue;
251 }
252 sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
253 if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
254 ssb_device_put(sdev);
255 continue;
256 }
257 sdrv->remove(sdev);
258 ctx->device_frozen[i] = 1;
259 }
260
261 return 0;
262 }
263
264 /** ssb_devices_thaw - Unfreeze all devices on the bus.
265 *
266 * This will re-attach the device drivers and re-init the devices.
267 *
268 * @ctx: The context structure from ssb_devices_freeze()
269 */
270 int ssb_devices_thaw(struct ssb_freeze_context *ctx)
271 {
272 struct ssb_bus *bus = ctx->bus;
273 struct ssb_device *sdev;
274 struct ssb_driver *sdrv;
275 unsigned int i;
276 int err, result = 0;
277
278 for (i = 0; i < bus->nr_devices; i++) {
279 if (!ctx->device_frozen[i])
280 continue;
281 sdev = &bus->devices[i];
282
283 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
284 continue;
285 sdrv = drv_to_ssb_drv(sdev->dev->driver);
286 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
287 continue;
288
289 err = sdrv->probe(sdev, &sdev->id);
290 if (err) {
291 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
292 dev_name(sdev->dev));
293 result = err;
294 }
295 ssb_driver_put(sdrv);
296 ssb_device_put(sdev);
297 }
298
299 return result;
300 }
301 #endif /* CONFIG_SSB_SPROM */
302
303 static void ssb_device_shutdown(struct device *dev)
304 {
305 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
306 struct ssb_driver *ssb_drv;
307
308 if (!dev->driver)
309 return;
310 ssb_drv = drv_to_ssb_drv(dev->driver);
311 if (ssb_drv && ssb_drv->shutdown)
312 ssb_drv->shutdown(ssb_dev);
313 }
314
315 static int ssb_device_remove(struct device *dev)
316 {
317 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
318 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
319
320 if (ssb_drv && ssb_drv->remove)
321 ssb_drv->remove(ssb_dev);
322 ssb_device_put(ssb_dev);
323
324 return 0;
325 }
326
327 static int ssb_device_probe(struct device *dev)
328 {
329 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
330 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
331 int err = 0;
332
333 ssb_device_get(ssb_dev);
334 if (ssb_drv && ssb_drv->probe)
335 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
336 if (err)
337 ssb_device_put(ssb_dev);
338
339 return err;
340 }
341
342 static int ssb_match_devid(const struct ssb_device_id *tabid,
343 const struct ssb_device_id *devid)
344 {
345 if ((tabid->vendor != devid->vendor) &&
346 tabid->vendor != SSB_ANY_VENDOR)
347 return 0;
348 if ((tabid->coreid != devid->coreid) &&
349 tabid->coreid != SSB_ANY_ID)
350 return 0;
351 if ((tabid->revision != devid->revision) &&
352 tabid->revision != SSB_ANY_REV)
353 return 0;
354 return 1;
355 }
356
357 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
358 {
359 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
360 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
361 const struct ssb_device_id *id;
362
363 for (id = ssb_drv->id_table;
364 id->vendor || id->coreid || id->revision;
365 id++) {
366 if (ssb_match_devid(id, &ssb_dev->id))
367 return 1; /* found */
368 }
369
370 return 0;
371 }
372
373 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
374 {
375 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
376
377 if (!dev)
378 return -ENODEV;
379
380 return add_uevent_var(env,
381 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
382 ssb_dev->id.vendor, ssb_dev->id.coreid,
383 ssb_dev->id.revision);
384 }
385
386 #define ssb_config_attr(attrib, field, format_string) \
387 static ssize_t \
388 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
389 { \
390 return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
391 }
392
393 ssb_config_attr(core_num, core_index, "%u\n")
394 ssb_config_attr(coreid, id.coreid, "0x%04x\n")
395 ssb_config_attr(vendor, id.vendor, "0x%04x\n")
396 ssb_config_attr(revision, id.revision, "%u\n")
397 ssb_config_attr(irq, irq, "%u\n")
398 static ssize_t
399 name_show(struct device *dev, struct device_attribute *attr, char *buf)
400 {
401 return sprintf(buf, "%s\n",
402 ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
403 }
404
405 static struct device_attribute ssb_device_attrs[] = {
406 __ATTR_RO(name),
407 __ATTR_RO(core_num),
408 __ATTR_RO(coreid),
409 __ATTR_RO(vendor),
410 __ATTR_RO(revision),
411 __ATTR_RO(irq),
412 __ATTR_NULL,
413 };
414
415 static struct bus_type ssb_bustype = {
416 .name = "ssb",
417 .match = ssb_bus_match,
418 .probe = ssb_device_probe,
419 .remove = ssb_device_remove,
420 .shutdown = ssb_device_shutdown,
421 .suspend = ssb_device_suspend,
422 .resume = ssb_device_resume,
423 .uevent = ssb_device_uevent,
424 .dev_attrs = ssb_device_attrs,
425 };
426
427 static void ssb_buses_lock(void)
428 {
429 /* See the comment at the ssb_is_early_boot definition */
430 if (!ssb_is_early_boot)
431 mutex_lock(&buses_mutex);
432 }
433
434 static void ssb_buses_unlock(void)
435 {
436 /* See the comment at the ssb_is_early_boot definition */
437 if (!ssb_is_early_boot)
438 mutex_unlock(&buses_mutex);
439 }
440
441 static void ssb_devices_unregister(struct ssb_bus *bus)
442 {
443 struct ssb_device *sdev;
444 int i;
445
446 for (i = bus->nr_devices - 1; i >= 0; i--) {
447 sdev = &(bus->devices[i]);
448 if (sdev->dev)
449 device_unregister(sdev->dev);
450 }
451 }
452
453 void ssb_bus_unregister(struct ssb_bus *bus)
454 {
455 ssb_buses_lock();
456 ssb_devices_unregister(bus);
457 list_del(&bus->list);
458 ssb_buses_unlock();
459
460 ssb_pcmcia_exit(bus);
461 ssb_pci_exit(bus);
462 ssb_iounmap(bus);
463 }
464 EXPORT_SYMBOL(ssb_bus_unregister);
465
466 static void ssb_release_dev(struct device *dev)
467 {
468 struct __ssb_dev_wrapper *devwrap;
469
470 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
471 kfree(devwrap);
472 }
473
474 static int ssb_devices_register(struct ssb_bus *bus)
475 {
476 struct ssb_device *sdev;
477 struct device *dev;
478 struct __ssb_dev_wrapper *devwrap;
479 int i, err = 0;
480 int dev_idx = 0;
481
482 for (i = 0; i < bus->nr_devices; i++) {
483 sdev = &(bus->devices[i]);
484
485 /* We don't register SSB-system devices to the kernel,
486 * as the drivers for them are built into SSB. */
487 switch (sdev->id.coreid) {
488 case SSB_DEV_CHIPCOMMON:
489 case SSB_DEV_PCI:
490 case SSB_DEV_PCIE:
491 case SSB_DEV_PCMCIA:
492 case SSB_DEV_MIPS:
493 case SSB_DEV_MIPS_3302:
494 case SSB_DEV_EXTIF:
495 continue;
496 }
497
498 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
499 if (!devwrap) {
500 ssb_printk(KERN_ERR PFX
501 "Could not allocate device\n");
502 err = -ENOMEM;
503 goto error;
504 }
505 dev = &devwrap->dev;
506 devwrap->sdev = sdev;
507
508 dev->release = ssb_release_dev;
509 dev->bus = &ssb_bustype;
510 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
511
512 switch (bus->bustype) {
513 case SSB_BUSTYPE_PCI:
514 #ifdef CONFIG_SSB_PCIHOST
515 sdev->irq = bus->host_pci->irq;
516 dev->parent = &bus->host_pci->dev;
517 sdev->dma_dev = dev->parent;
518 #endif
519 break;
520 case SSB_BUSTYPE_PCMCIA:
521 #ifdef CONFIG_SSB_PCMCIAHOST
522 sdev->irq = bus->host_pcmcia->irq;
523 dev->parent = &bus->host_pcmcia->dev;
524 #endif
525 break;
526 case SSB_BUSTYPE_SDIO:
527 #ifdef CONFIG_SSB_SDIOHOST
528 dev->parent = &bus->host_sdio->dev;
529 #endif
530 break;
531 case SSB_BUSTYPE_SSB:
532 dev->dma_mask = &dev->coherent_dma_mask;
533 sdev->dma_dev = dev;
534 break;
535 }
536
537 sdev->dev = dev;
538 err = device_register(dev);
539 if (err) {
540 ssb_printk(KERN_ERR PFX
541 "Could not register %s\n",
542 dev_name(dev));
543 /* Set dev to NULL to not unregister
544 * dev on error unwinding. */
545 sdev->dev = NULL;
546 kfree(devwrap);
547 goto error;
548 }
549 dev_idx++;
550 }
551
552 return 0;
553 error:
554 /* Unwind the already registered devices. */
555 ssb_devices_unregister(bus);
556 return err;
557 }
558
559 /* Needs ssb_buses_lock() */
560 static int ssb_attach_queued_buses(void)
561 {
562 struct ssb_bus *bus, *n;
563 int err = 0;
564 int drop_them_all = 0;
565
566 list_for_each_entry_safe(bus, n, &attach_queue, list) {
567 if (drop_them_all) {
568 list_del(&bus->list);
569 continue;
570 }
571 /* Can't init the PCIcore in ssb_bus_register(), as that
572 * is too early in boot for embedded systems
573 * (no udelay() available). So do it here in attach stage.
574 */
575 err = ssb_bus_powerup(bus, 0);
576 if (err)
577 goto error;
578 ssb_pcicore_init(&bus->pcicore);
579 ssb_bus_may_powerdown(bus);
580
581 err = ssb_devices_register(bus);
582 error:
583 if (err) {
584 drop_them_all = 1;
585 list_del(&bus->list);
586 continue;
587 }
588 list_move_tail(&bus->list, &buses);
589 }
590
591 return err;
592 }
593
594 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
595 {
596 struct ssb_bus *bus = dev->bus;
597
598 offset += dev->core_index * SSB_CORE_SIZE;
599 return readb(bus->mmio + offset);
600 }
601
602 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
603 {
604 struct ssb_bus *bus = dev->bus;
605
606 offset += dev->core_index * SSB_CORE_SIZE;
607 return readw(bus->mmio + offset);
608 }
609
610 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
611 {
612 struct ssb_bus *bus = dev->bus;
613
614 offset += dev->core_index * SSB_CORE_SIZE;
615 return readl(bus->mmio + offset);
616 }
617
618 #ifdef CONFIG_SSB_BLOCKIO
619 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
620 size_t count, u16 offset, u8 reg_width)
621 {
622 struct ssb_bus *bus = dev->bus;
623 void __iomem *addr;
624
625 offset += dev->core_index * SSB_CORE_SIZE;
626 addr = bus->mmio + offset;
627
628 switch (reg_width) {
629 case sizeof(u8): {
630 u8 *buf = buffer;
631
632 while (count) {
633 *buf = __raw_readb(addr);
634 buf++;
635 count--;
636 }
637 break;
638 }
639 case sizeof(u16): {
640 __le16 *buf = buffer;
641
642 SSB_WARN_ON(count & 1);
643 while (count) {
644 *buf = (__force __le16)__raw_readw(addr);
645 buf++;
646 count -= 2;
647 }
648 break;
649 }
650 case sizeof(u32): {
651 __le32 *buf = buffer;
652
653 SSB_WARN_ON(count & 3);
654 while (count) {
655 *buf = (__force __le32)__raw_readl(addr);
656 buf++;
657 count -= 4;
658 }
659 break;
660 }
661 default:
662 SSB_WARN_ON(1);
663 }
664 }
665 #endif /* CONFIG_SSB_BLOCKIO */
666
667 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
668 {
669 struct ssb_bus *bus = dev->bus;
670
671 offset += dev->core_index * SSB_CORE_SIZE;
672 writeb(value, bus->mmio + offset);
673 }
674
675 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
676 {
677 struct ssb_bus *bus = dev->bus;
678
679 offset += dev->core_index * SSB_CORE_SIZE;
680 writew(value, bus->mmio + offset);
681 }
682
683 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
684 {
685 struct ssb_bus *bus = dev->bus;
686
687 offset += dev->core_index * SSB_CORE_SIZE;
688 writel(value, bus->mmio + offset);
689 }
690
691 #ifdef CONFIG_SSB_BLOCKIO
692 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
693 size_t count, u16 offset, u8 reg_width)
694 {
695 struct ssb_bus *bus = dev->bus;
696 void __iomem *addr;
697
698 offset += dev->core_index * SSB_CORE_SIZE;
699 addr = bus->mmio + offset;
700
701 switch (reg_width) {
702 case sizeof(u8): {
703 const u8 *buf = buffer;
704
705 while (count) {
706 __raw_writeb(*buf, addr);
707 buf++;
708 count--;
709 }
710 break;
711 }
712 case sizeof(u16): {
713 const __le16 *buf = buffer;
714
715 SSB_WARN_ON(count & 1);
716 while (count) {
717 __raw_writew((__force u16)(*buf), addr);
718 buf++;
719 count -= 2;
720 }
721 break;
722 }
723 case sizeof(u32): {
724 const __le32 *buf = buffer;
725
726 SSB_WARN_ON(count & 3);
727 while (count) {
728 __raw_writel((__force u32)(*buf), addr);
729 buf++;
730 count -= 4;
731 }
732 break;
733 }
734 default:
735 SSB_WARN_ON(1);
736 }
737 }
738 #endif /* CONFIG_SSB_BLOCKIO */
739
740 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
741 static const struct ssb_bus_ops ssb_ssb_ops = {
742 .read8 = ssb_ssb_read8,
743 .read16 = ssb_ssb_read16,
744 .read32 = ssb_ssb_read32,
745 .write8 = ssb_ssb_write8,
746 .write16 = ssb_ssb_write16,
747 .write32 = ssb_ssb_write32,
748 #ifdef CONFIG_SSB_BLOCKIO
749 .block_read = ssb_ssb_block_read,
750 .block_write = ssb_ssb_block_write,
751 #endif
752 };
753
754 static int ssb_fetch_invariants(struct ssb_bus *bus,
755 ssb_invariants_func_t get_invariants)
756 {
757 struct ssb_init_invariants iv;
758 int err;
759
760 memset(&iv, 0, sizeof(iv));
761 err = get_invariants(bus, &iv);
762 if (err)
763 goto out;
764 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
765 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
766 bus->has_cardbus_slot = iv.has_cardbus_slot;
767 out:
768 return err;
769 }
770
771 static int ssb_bus_register(struct ssb_bus *bus,
772 ssb_invariants_func_t get_invariants,
773 unsigned long baseaddr)
774 {
775 int err;
776
777 spin_lock_init(&bus->bar_lock);
778 INIT_LIST_HEAD(&bus->list);
779 #ifdef CONFIG_SSB_EMBEDDED
780 spin_lock_init(&bus->gpio_lock);
781 #endif
782
783 /* Powerup the bus */
784 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
785 if (err)
786 goto out;
787
788 /* Init SDIO-host device (if any), before the scan */
789 err = ssb_sdio_init(bus);
790 if (err)
791 goto err_disable_xtal;
792
793 ssb_buses_lock();
794 bus->busnumber = next_busnumber;
795 /* Scan for devices (cores) */
796 err = ssb_bus_scan(bus, baseaddr);
797 if (err)
798 goto err_sdio_exit;
799
800 /* Init PCI-host device (if any) */
801 err = ssb_pci_init(bus);
802 if (err)
803 goto err_unmap;
804 /* Init PCMCIA-host device (if any) */
805 err = ssb_pcmcia_init(bus);
806 if (err)
807 goto err_pci_exit;
808
809 /* Initialize basic system devices (if available) */
810 err = ssb_bus_powerup(bus, 0);
811 if (err)
812 goto err_pcmcia_exit;
813 ssb_chipcommon_init(&bus->chipco);
814 ssb_mipscore_init(&bus->mipscore);
815 err = ssb_fetch_invariants(bus, get_invariants);
816 if (err) {
817 ssb_bus_may_powerdown(bus);
818 goto err_pcmcia_exit;
819 }
820 ssb_bus_may_powerdown(bus);
821
822 /* Queue it for attach.
823 * See the comment at the ssb_is_early_boot definition. */
824 list_add_tail(&bus->list, &attach_queue);
825 if (!ssb_is_early_boot) {
826 /* This is not early boot, so we must attach the bus now */
827 err = ssb_attach_queued_buses();
828 if (err)
829 goto err_dequeue;
830 }
831 next_busnumber++;
832 ssb_buses_unlock();
833
834 out:
835 return err;
836
837 err_dequeue:
838 list_del(&bus->list);
839 err_pcmcia_exit:
840 ssb_pcmcia_exit(bus);
841 err_pci_exit:
842 ssb_pci_exit(bus);
843 err_unmap:
844 ssb_iounmap(bus);
845 err_sdio_exit:
846 ssb_sdio_exit(bus);
847 err_disable_xtal:
848 ssb_buses_unlock();
849 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
850 return err;
851 }
852
853 #ifdef CONFIG_SSB_PCIHOST
854 int ssb_bus_pcibus_register(struct ssb_bus *bus,
855 struct pci_dev *host_pci)
856 {
857 int err;
858
859 bus->bustype = SSB_BUSTYPE_PCI;
860 bus->host_pci = host_pci;
861 bus->ops = &ssb_pci_ops;
862
863 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
864 if (!err) {
865 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
866 "PCI device %s\n", dev_name(&host_pci->dev));
867 } else {
868 ssb_printk(KERN_ERR PFX "Failed to register PCI version"
869 " of SSB with error %d\n", err);
870 }
871
872 return err;
873 }
874 EXPORT_SYMBOL(ssb_bus_pcibus_register);
875 #endif /* CONFIG_SSB_PCIHOST */
876
877 #ifdef CONFIG_SSB_PCMCIAHOST
878 int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
879 struct pcmcia_device *pcmcia_dev,
880 unsigned long baseaddr)
881 {
882 int err;
883
884 bus->bustype = SSB_BUSTYPE_PCMCIA;
885 bus->host_pcmcia = pcmcia_dev;
886 bus->ops = &ssb_pcmcia_ops;
887
888 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
889 if (!err) {
890 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
891 "PCMCIA device %s\n", pcmcia_dev->devname);
892 }
893
894 return err;
895 }
896 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
897 #endif /* CONFIG_SSB_PCMCIAHOST */
898
899 #ifdef CONFIG_SSB_SDIOHOST
900 int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
901 unsigned int quirks)
902 {
903 int err;
904
905 bus->bustype = SSB_BUSTYPE_SDIO;
906 bus->host_sdio = func;
907 bus->ops = &ssb_sdio_ops;
908 bus->quirks = quirks;
909
910 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
911 if (!err) {
912 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
913 "SDIO device %s\n", sdio_func_id(func));
914 }
915
916 return err;
917 }
918 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
919 #endif /* CONFIG_SSB_PCMCIAHOST */
920
921 int ssb_bus_ssbbus_register(struct ssb_bus *bus,
922 unsigned long baseaddr,
923 ssb_invariants_func_t get_invariants)
924 {
925 int err;
926
927 bus->bustype = SSB_BUSTYPE_SSB;
928 bus->ops = &ssb_ssb_ops;
929
930 err = ssb_bus_register(bus, get_invariants, baseaddr);
931 if (!err) {
932 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
933 "address 0x%08lX\n", baseaddr);
934 }
935
936 return err;
937 }
938
939 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
940 {
941 drv->drv.name = drv->name;
942 drv->drv.bus = &ssb_bustype;
943 drv->drv.owner = owner;
944
945 return driver_register(&drv->drv);
946 }
947 EXPORT_SYMBOL(__ssb_driver_register);
948
949 void ssb_driver_unregister(struct ssb_driver *drv)
950 {
951 driver_unregister(&drv->drv);
952 }
953 EXPORT_SYMBOL(ssb_driver_unregister);
954
955 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
956 {
957 struct ssb_bus *bus = dev->bus;
958 struct ssb_device *ent;
959 int i;
960
961 for (i = 0; i < bus->nr_devices; i++) {
962 ent = &(bus->devices[i]);
963 if (ent->id.vendor != dev->id.vendor)
964 continue;
965 if (ent->id.coreid != dev->id.coreid)
966 continue;
967
968 ent->devtypedata = data;
969 }
970 }
971 EXPORT_SYMBOL(ssb_set_devtypedata);
972
973 static u32 clkfactor_f6_resolve(u32 v)
974 {
975 /* map the magic values */
976 switch (v) {
977 case SSB_CHIPCO_CLK_F6_2:
978 return 2;
979 case SSB_CHIPCO_CLK_F6_3:
980 return 3;
981 case SSB_CHIPCO_CLK_F6_4:
982 return 4;
983 case SSB_CHIPCO_CLK_F6_5:
984 return 5;
985 case SSB_CHIPCO_CLK_F6_6:
986 return 6;
987 case SSB_CHIPCO_CLK_F6_7:
988 return 7;
989 }
990 return 0;
991 }
992
993 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
994 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
995 {
996 u32 n1, n2, clock, m1, m2, m3, mc;
997
998 n1 = (n & SSB_CHIPCO_CLK_N1);
999 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
1000
1001 switch (plltype) {
1002 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1003 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1004 return SSB_CHIPCO_CLK_T6_M0;
1005 return SSB_CHIPCO_CLK_T6_M1;
1006 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1007 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1008 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1009 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1010 n1 = clkfactor_f6_resolve(n1);
1011 n2 += SSB_CHIPCO_CLK_F5_BIAS;
1012 break;
1013 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
1014 n1 += SSB_CHIPCO_CLK_T2_BIAS;
1015 n2 += SSB_CHIPCO_CLK_T2_BIAS;
1016 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
1017 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
1018 break;
1019 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
1020 return 100000000;
1021 default:
1022 SSB_WARN_ON(1);
1023 }
1024
1025 switch (plltype) {
1026 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1027 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1028 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
1029 break;
1030 default:
1031 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
1032 }
1033 if (!clock)
1034 return 0;
1035
1036 m1 = (m & SSB_CHIPCO_CLK_M1);
1037 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
1038 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
1039 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
1040
1041 switch (plltype) {
1042 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1043 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1044 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1045 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1046 m1 = clkfactor_f6_resolve(m1);
1047 if ((plltype == SSB_PLLTYPE_1) ||
1048 (plltype == SSB_PLLTYPE_3))
1049 m2 += SSB_CHIPCO_CLK_F5_BIAS;
1050 else
1051 m2 = clkfactor_f6_resolve(m2);
1052 m3 = clkfactor_f6_resolve(m3);
1053
1054 switch (mc) {
1055 case SSB_CHIPCO_CLK_MC_BYPASS:
1056 return clock;
1057 case SSB_CHIPCO_CLK_MC_M1:
1058 return (clock / m1);
1059 case SSB_CHIPCO_CLK_MC_M1M2:
1060 return (clock / (m1 * m2));
1061 case SSB_CHIPCO_CLK_MC_M1M2M3:
1062 return (clock / (m1 * m2 * m3));
1063 case SSB_CHIPCO_CLK_MC_M1M3:
1064 return (clock / (m1 * m3));
1065 }
1066 return 0;
1067 case SSB_PLLTYPE_2:
1068 m1 += SSB_CHIPCO_CLK_T2_BIAS;
1069 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
1070 m3 += SSB_CHIPCO_CLK_T2_BIAS;
1071 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
1072 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
1073 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
1074
1075 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
1076 clock /= m1;
1077 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
1078 clock /= m2;
1079 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
1080 clock /= m3;
1081 return clock;
1082 default:
1083 SSB_WARN_ON(1);
1084 }
1085 return 0;
1086 }
1087
1088 /* Get the current speed the backplane is running at */
1089 u32 ssb_clockspeed(struct ssb_bus *bus)
1090 {
1091 u32 rate;
1092 u32 plltype;
1093 u32 clkctl_n, clkctl_m;
1094
1095 if (ssb_extif_available(&bus->extif))
1096 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1097 &clkctl_n, &clkctl_m);
1098 else if (bus->chipco.dev)
1099 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1100 &clkctl_n, &clkctl_m);
1101 else
1102 return 0;
1103
1104 if (bus->chip_id == 0x5365) {
1105 rate = 100000000;
1106 } else {
1107 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1108 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1109 rate /= 2;
1110 }
1111
1112 return rate;
1113 }
1114 EXPORT_SYMBOL(ssb_clockspeed);
1115
1116 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1117 {
1118 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1119
1120 /* The REJECT bit seems to be different for Backplane rev 2.3 */
1121 switch (rev) {
1122 case SSB_IDLOW_SSBREV_22:
1123 case SSB_IDLOW_SSBREV_24:
1124 case SSB_IDLOW_SSBREV_26:
1125 return SSB_TMSLOW_REJECT;
1126 case SSB_IDLOW_SSBREV_23:
1127 return SSB_TMSLOW_REJECT_23;
1128 case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1129 case SSB_IDLOW_SSBREV_27: /* same here */
1130 return SSB_TMSLOW_REJECT; /* this is a guess */
1131 default:
1132 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1133 WARN_ON(1);
1134 }
1135 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1136 }
1137
1138 int ssb_device_is_enabled(struct ssb_device *dev)
1139 {
1140 u32 val;
1141 u32 reject;
1142
1143 reject = ssb_tmslow_reject_bitmask(dev);
1144 val = ssb_read32(dev, SSB_TMSLOW);
1145 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1146
1147 return (val == SSB_TMSLOW_CLOCK);
1148 }
1149 EXPORT_SYMBOL(ssb_device_is_enabled);
1150
1151 static void ssb_flush_tmslow(struct ssb_device *dev)
1152 {
1153 /* Make _really_ sure the device has finished the TMSLOW
1154 * register write transaction, as we risk running into
1155 * a machine check exception otherwise.
1156 * Do this by reading the register back to commit the
1157 * PCI write and delay an additional usec for the device
1158 * to react to the change. */
1159 ssb_read32(dev, SSB_TMSLOW);
1160 udelay(1);
1161 }
1162
1163 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1164 {
1165 u32 val;
1166
1167 ssb_device_disable(dev, core_specific_flags);
1168 ssb_write32(dev, SSB_TMSLOW,
1169 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1170 SSB_TMSLOW_FGC | core_specific_flags);
1171 ssb_flush_tmslow(dev);
1172
1173 /* Clear SERR if set. This is a hw bug workaround. */
1174 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1175 ssb_write32(dev, SSB_TMSHIGH, 0);
1176
1177 val = ssb_read32(dev, SSB_IMSTATE);
1178 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1179 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1180 ssb_write32(dev, SSB_IMSTATE, val);
1181 }
1182
1183 ssb_write32(dev, SSB_TMSLOW,
1184 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1185 core_specific_flags);
1186 ssb_flush_tmslow(dev);
1187
1188 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1189 core_specific_flags);
1190 ssb_flush_tmslow(dev);
1191 }
1192 EXPORT_SYMBOL(ssb_device_enable);
1193
1194 /* Wait for bitmask in a register to get set or cleared.
1195 * timeout is in units of ten-microseconds */
1196 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1197 int timeout, int set)
1198 {
1199 int i;
1200 u32 val;
1201
1202 for (i = 0; i < timeout; i++) {
1203 val = ssb_read32(dev, reg);
1204 if (set) {
1205 if ((val & bitmask) == bitmask)
1206 return 0;
1207 } else {
1208 if (!(val & bitmask))
1209 return 0;
1210 }
1211 udelay(10);
1212 }
1213 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1214 "register %04X to %s.\n",
1215 bitmask, reg, (set ? "set" : "clear"));
1216
1217 return -ETIMEDOUT;
1218 }
1219
1220 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1221 {
1222 u32 reject, val;
1223
1224 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1225 return;
1226
1227 reject = ssb_tmslow_reject_bitmask(dev);
1228
1229 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1230 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1231 ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1232 ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1233
1234 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1235 val = ssb_read32(dev, SSB_IMSTATE);
1236 val |= SSB_IMSTATE_REJECT;
1237 ssb_write32(dev, SSB_IMSTATE, val);
1238 ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1239 0);
1240 }
1241
1242 ssb_write32(dev, SSB_TMSLOW,
1243 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1244 reject | SSB_TMSLOW_RESET |
1245 core_specific_flags);
1246 ssb_flush_tmslow(dev);
1247
1248 if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1249 val = ssb_read32(dev, SSB_IMSTATE);
1250 val &= ~SSB_IMSTATE_REJECT;
1251 ssb_write32(dev, SSB_IMSTATE, val);
1252 }
1253 }
1254
1255 ssb_write32(dev, SSB_TMSLOW,
1256 reject | SSB_TMSLOW_RESET |
1257 core_specific_flags);
1258 ssb_flush_tmslow(dev);
1259 }
1260 EXPORT_SYMBOL(ssb_device_disable);
1261
1262 u32 ssb_dma_translation(struct ssb_device *dev)
1263 {
1264 switch (dev->bus->bustype) {
1265 case SSB_BUSTYPE_SSB:
1266 return 0;
1267 case SSB_BUSTYPE_PCI:
1268 return SSB_PCI_DMA;
1269 default:
1270 __ssb_dma_not_implemented(dev);
1271 }
1272 return 0;
1273 }
1274 EXPORT_SYMBOL(ssb_dma_translation);
1275
1276 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1277 {
1278 struct ssb_chipcommon *cc;
1279 int err = 0;
1280
1281 /* On buses where more than one core may be working
1282 * at a time, we must not powerdown stuff if there are
1283 * still cores that may want to run. */
1284 if (bus->bustype == SSB_BUSTYPE_SSB)
1285 goto out;
1286
1287 cc = &bus->chipco;
1288
1289 if (!cc->dev)
1290 goto out;
1291 if (cc->dev->id.revision < 5)
1292 goto out;
1293
1294 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1295 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1296 if (err)
1297 goto error;
1298 out:
1299 #ifdef CONFIG_SSB_DEBUG
1300 bus->powered_up = 0;
1301 #endif
1302 return err;
1303 error:
1304 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1305 goto out;
1306 }
1307 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1308
1309 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1310 {
1311 int err;
1312 enum ssb_clkmode mode;
1313
1314 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1315 if (err)
1316 goto error;
1317
1318 #ifdef CONFIG_SSB_DEBUG
1319 bus->powered_up = 1;
1320 #endif
1321
1322 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1323 ssb_chipco_set_clockmode(&bus->chipco, mode);
1324
1325 return 0;
1326 error:
1327 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1328 return err;
1329 }
1330 EXPORT_SYMBOL(ssb_bus_powerup);
1331
1332 static void ssb_broadcast_value(struct ssb_device *dev,
1333 u32 address, u32 data)
1334 {
1335 #ifdef CONFIG_SSB_DRIVER_PCICORE
1336 /* This is used for both, PCI and ChipCommon core, so be careful. */
1337 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1338 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1339 #endif
1340
1341 ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1342 ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1343 ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1344 ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1345 }
1346
1347 void ssb_commit_settings(struct ssb_bus *bus)
1348 {
1349 struct ssb_device *dev;
1350
1351 #ifdef CONFIG_SSB_DRIVER_PCICORE
1352 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1353 #else
1354 dev = bus->chipco.dev;
1355 #endif
1356 if (WARN_ON(!dev))
1357 return;
1358 /* This forces an update of the cached registers. */
1359 ssb_broadcast_value(dev, 0xFD8, 0);
1360 }
1361 EXPORT_SYMBOL(ssb_commit_settings);
1362
1363 u32 ssb_admatch_base(u32 adm)
1364 {
1365 u32 base = 0;
1366
1367 switch (adm & SSB_ADM_TYPE) {
1368 case SSB_ADM_TYPE0:
1369 base = (adm & SSB_ADM_BASE0);
1370 break;
1371 case SSB_ADM_TYPE1:
1372 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1373 base = (adm & SSB_ADM_BASE1);
1374 break;
1375 case SSB_ADM_TYPE2:
1376 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1377 base = (adm & SSB_ADM_BASE2);
1378 break;
1379 default:
1380 SSB_WARN_ON(1);
1381 }
1382
1383 return base;
1384 }
1385 EXPORT_SYMBOL(ssb_admatch_base);
1386
1387 u32 ssb_admatch_size(u32 adm)
1388 {
1389 u32 size = 0;
1390
1391 switch (adm & SSB_ADM_TYPE) {
1392 case SSB_ADM_TYPE0:
1393 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1394 break;
1395 case SSB_ADM_TYPE1:
1396 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1397 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1398 break;
1399 case SSB_ADM_TYPE2:
1400 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1401 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1402 break;
1403 default:
1404 SSB_WARN_ON(1);
1405 }
1406 size = (1 << (size + 1));
1407
1408 return size;
1409 }
1410 EXPORT_SYMBOL(ssb_admatch_size);
1411
1412 static int __init ssb_modinit(void)
1413 {
1414 int err;
1415
1416 /* See the comment at the ssb_is_early_boot definition */
1417 ssb_is_early_boot = 0;
1418 err = bus_register(&ssb_bustype);
1419 if (err)
1420 return err;
1421
1422 /* Maybe we already registered some buses at early boot.
1423 * Check for this and attach them
1424 */
1425 ssb_buses_lock();
1426 err = ssb_attach_queued_buses();
1427 ssb_buses_unlock();
1428 if (err) {
1429 bus_unregister(&ssb_bustype);
1430 goto out;
1431 }
1432
1433 err = b43_pci_ssb_bridge_init();
1434 if (err) {
1435 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1436 "initialization failed\n");
1437 /* don't fail SSB init because of this */
1438 err = 0;
1439 }
1440 err = ssb_gige_init();
1441 if (err) {
1442 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1443 "driver initialization failed\n");
1444 /* don't fail SSB init because of this */
1445 err = 0;
1446 }
1447 out:
1448 return err;
1449 }
1450 /* ssb must be initialized after PCI but before the ssb drivers.
1451 * That means we must use some initcall between subsys_initcall
1452 * and device_initcall. */
1453 fs_initcall(ssb_modinit);
1454
1455 static void __exit ssb_modexit(void)
1456 {
1457 ssb_gige_exit();
1458 b43_pci_ssb_bridge_exit();
1459 bus_unregister(&ssb_bustype);
1460 }
1461 module_exit(ssb_modexit)
Linux with added FPC-III support