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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / tty / serial / pch_uart.c
blob101eda9f1965c776f61728c2fca93bf77f97007d
1 /*
2 *Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
3 *
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
7 *
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
12 *
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17 #include <linux/serial_reg.h>
18 #include <linux/slab.h>
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/serial_core.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/dmi.h>
25
26 #include <linux/dmaengine.h>
27 #include <linux/pch_dma.h>
28
29 enum {
30 PCH_UART_HANDLED_RX_INT_SHIFT,
31 PCH_UART_HANDLED_TX_INT_SHIFT,
32 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
33 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
34 PCH_UART_HANDLED_MS_INT_SHIFT,
35 };
36
37 enum {
38 PCH_UART_8LINE,
39 PCH_UART_2LINE,
40 };
41
42 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
43
44 /* Set the max number of UART port
45 * Intel EG20T PCH: 4 port
46 * OKI SEMICONDUCTOR ML7213 IOH: 3 port
47 */
48 #define PCH_UART_NR 4
49
50 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
51 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
52 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
53 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
54 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
55 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
56 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
57
58 #define PCH_UART_RBR 0x00
59 #define PCH_UART_THR 0x00
60
61 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
62 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
63 #define PCH_UART_IER_ERBFI 0x00000001
64 #define PCH_UART_IER_ETBEI 0x00000002
65 #define PCH_UART_IER_ELSI 0x00000004
66 #define PCH_UART_IER_EDSSI 0x00000008
67
68 #define PCH_UART_IIR_IP 0x00000001
69 #define PCH_UART_IIR_IID 0x00000006
70 #define PCH_UART_IIR_MSI 0x00000000
71 #define PCH_UART_IIR_TRI 0x00000002
72 #define PCH_UART_IIR_RRI 0x00000004
73 #define PCH_UART_IIR_REI 0x00000006
74 #define PCH_UART_IIR_TOI 0x00000008
75 #define PCH_UART_IIR_FIFO256 0x00000020
76 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
77 #define PCH_UART_IIR_FE 0x000000C0
78
79 #define PCH_UART_FCR_FIFOE 0x00000001
80 #define PCH_UART_FCR_RFR 0x00000002
81 #define PCH_UART_FCR_TFR 0x00000004
82 #define PCH_UART_FCR_DMS 0x00000008
83 #define PCH_UART_FCR_FIFO256 0x00000020
84 #define PCH_UART_FCR_RFTL 0x000000C0
85
86 #define PCH_UART_FCR_RFTL1 0x00000000
87 #define PCH_UART_FCR_RFTL64 0x00000040
88 #define PCH_UART_FCR_RFTL128 0x00000080
89 #define PCH_UART_FCR_RFTL224 0x000000C0
90 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
91 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
92 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
93 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
94 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
95 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
96 #define PCH_UART_FCR_RFTL_SHIFT 6
97
98 #define PCH_UART_LCR_WLS 0x00000003
99 #define PCH_UART_LCR_STB 0x00000004
100 #define PCH_UART_LCR_PEN 0x00000008
101 #define PCH_UART_LCR_EPS 0x00000010
102 #define PCH_UART_LCR_SP 0x00000020
103 #define PCH_UART_LCR_SB 0x00000040
104 #define PCH_UART_LCR_DLAB 0x00000080
105 #define PCH_UART_LCR_NP 0x00000000
106 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
107 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
108 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
109 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
110 PCH_UART_LCR_SP)
111
112 #define PCH_UART_LCR_5BIT 0x00000000
113 #define PCH_UART_LCR_6BIT 0x00000001
114 #define PCH_UART_LCR_7BIT 0x00000002
115 #define PCH_UART_LCR_8BIT 0x00000003
116
117 #define PCH_UART_MCR_DTR 0x00000001
118 #define PCH_UART_MCR_RTS 0x00000002
119 #define PCH_UART_MCR_OUT 0x0000000C
120 #define PCH_UART_MCR_LOOP 0x00000010
121 #define PCH_UART_MCR_AFE 0x00000020
122
123 #define PCH_UART_LSR_DR 0x00000001
124 #define PCH_UART_LSR_ERR (1<<7)
125
126 #define PCH_UART_MSR_DCTS 0x00000001
127 #define PCH_UART_MSR_DDSR 0x00000002
128 #define PCH_UART_MSR_TERI 0x00000004
129 #define PCH_UART_MSR_DDCD 0x00000008
130 #define PCH_UART_MSR_CTS 0x00000010
131 #define PCH_UART_MSR_DSR 0x00000020
132 #define PCH_UART_MSR_RI 0x00000040
133 #define PCH_UART_MSR_DCD 0x00000080
134 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
135 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
136
137 #define PCH_UART_DLL 0x00
138 #define PCH_UART_DLM 0x01
139
140 #define DIV_ROUND(a, b) (((a) + ((b)/2)) / (b))
141
142 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
143 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
144 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
145 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
146 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
147
148 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
149 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
150 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
151 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
152 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
153 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
154 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
155 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
156 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
157 #define PCH_UART_HAL_STB1 0
158 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
159
160 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
161 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
162 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
163 PCH_UART_HAL_CLR_RX_FIFO)
164
165 #define PCH_UART_HAL_DMA_MODE0 0
166 #define PCH_UART_HAL_FIFO_DIS 0
167 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
168 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
169 PCH_UART_FCR_FIFO256)
170 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
171 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
172 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
173 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
174 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
175 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
176 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
177 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
178 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
179 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
180 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
181 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
182 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
183 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
184
185 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
186 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
187 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
188 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
189 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
190
191 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
192 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
193 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
194 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
195 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
196
197 #define PCI_VENDOR_ID_ROHM 0x10DB
198
199 struct pch_uart_buffer {
200 unsigned char *buf;
201 int size;
202 };
203
204 struct eg20t_port {
205 struct uart_port port;
206 int port_type;
207 void __iomem *membase;
208 resource_size_t mapbase;
209 unsigned int iobase;
210 struct pci_dev *pdev;
211 int fifo_size;
212 int base_baud;
213 int start_tx;
214 int start_rx;
215 int tx_empty;
216 int int_dis_flag;
217 int trigger;
218 int trigger_level;
219 struct pch_uart_buffer rxbuf;
220 unsigned int dmsr;
221 unsigned int fcr;
222 unsigned int mcr;
223 unsigned int use_dma;
224 unsigned int use_dma_flag;
225 struct dma_async_tx_descriptor *desc_tx;
226 struct dma_async_tx_descriptor *desc_rx;
227 struct pch_dma_slave param_tx;
228 struct pch_dma_slave param_rx;
229 struct dma_chan *chan_tx;
230 struct dma_chan *chan_rx;
231 struct scatterlist *sg_tx_p;
232 int nent;
233 struct scatterlist sg_rx;
234 int tx_dma_use;
235 void *rx_buf_virt;
236 dma_addr_t rx_buf_dma;
237 };
238
239 /**
240 * struct pch_uart_driver_data - private data structure for UART-DMA
241 * @port_type: The number of DMA channel
242 * @line_no: UART port line number (0, 1, 2...)
243 */
244 struct pch_uart_driver_data {
245 int port_type;
246 int line_no;
247 };
248
249 enum pch_uart_num_t {
250 pch_et20t_uart0 = 0,
251 pch_et20t_uart1,
252 pch_et20t_uart2,
253 pch_et20t_uart3,
254 pch_ml7213_uart0,
255 pch_ml7213_uart1,
256 pch_ml7213_uart2,
257 pch_ml7223_uart0,
258 pch_ml7223_uart1,
259 pch_ml7831_uart0,
260 pch_ml7831_uart1,
261 };
262
263 static struct pch_uart_driver_data drv_dat[] = {
264 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
265 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
266 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
267 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
268 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
269 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
270 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
271 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
272 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
273 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
274 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
275 };
276
277 static unsigned int default_baud = 9600;
278 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
279 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
280 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
281 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
282
283 static void pch_uart_hal_request(struct pci_dev *pdev, int fifosize,
284 int base_baud)
285 {
286 struct eg20t_port *priv = pci_get_drvdata(pdev);
287
288 priv->trigger_level = 1;
289 priv->fcr = 0;
290 }
291
292 static unsigned int get_msr(struct eg20t_port *priv, void __iomem *base)
293 {
294 unsigned int msr = ioread8(base + UART_MSR);
295 priv->dmsr |= msr & PCH_UART_MSR_DELTA;
296
297 return msr;
298 }
299
300 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
301 unsigned int flag)
302 {
303 u8 ier = ioread8(priv->membase + UART_IER);
304 ier |= flag & PCH_UART_IER_MASK;
305 iowrite8(ier, priv->membase + UART_IER);
306 }
307
308 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
309 unsigned int flag)
310 {
311 u8 ier = ioread8(priv->membase + UART_IER);
312 ier &= ~(flag & PCH_UART_IER_MASK);
313 iowrite8(ier, priv->membase + UART_IER);
314 }
315
316 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
317 unsigned int parity, unsigned int bits,
318 unsigned int stb)
319 {
320 unsigned int dll, dlm, lcr;
321 int div;
322
323 div = DIV_ROUND(priv->base_baud / 16, baud);
324 if (div < 0 || USHRT_MAX <= div) {
325 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
326 return -EINVAL;
327 }
328
329 dll = (unsigned int)div & 0x00FFU;
330 dlm = ((unsigned int)div >> 8) & 0x00FFU;
331
332 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
333 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
334 return -EINVAL;
335 }
336
337 if (bits & ~PCH_UART_LCR_WLS) {
338 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
339 return -EINVAL;
340 }
341
342 if (stb & ~PCH_UART_LCR_STB) {
343 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
344 return -EINVAL;
345 }
346
347 lcr = parity;
348 lcr |= bits;
349 lcr |= stb;
350
351 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
352 __func__, baud, div, lcr, jiffies);
353 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
354 iowrite8(dll, priv->membase + PCH_UART_DLL);
355 iowrite8(dlm, priv->membase + PCH_UART_DLM);
356 iowrite8(lcr, priv->membase + UART_LCR);
357
358 return 0;
359 }
360
361 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
362 unsigned int flag)
363 {
364 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
365 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
366 __func__, flag);
367 return -EINVAL;
368 }
369
370 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
371 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
372 priv->membase + UART_FCR);
373 iowrite8(priv->fcr, priv->membase + UART_FCR);
374
375 return 0;
376 }
377
378 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
379 unsigned int dmamode,
380 unsigned int fifo_size, unsigned int trigger)
381 {
382 u8 fcr;
383
384 if (dmamode & ~PCH_UART_FCR_DMS) {
385 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
386 __func__, dmamode);
387 return -EINVAL;
388 }
389
390 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
391 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
392 __func__, fifo_size);
393 return -EINVAL;
394 }
395
396 if (trigger & ~PCH_UART_FCR_RFTL) {
397 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
398 __func__, trigger);
399 return -EINVAL;
400 }
401
402 switch (priv->fifo_size) {
403 case 256:
404 priv->trigger_level =
405 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
406 break;
407 case 64:
408 priv->trigger_level =
409 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
410 break;
411 case 16:
412 priv->trigger_level =
413 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
414 break;
415 default:
416 priv->trigger_level =
417 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
418 break;
419 }
420 fcr =
421 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
422 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
423 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
424 priv->membase + UART_FCR);
425 iowrite8(fcr, priv->membase + UART_FCR);
426 priv->fcr = fcr;
427
428 return 0;
429 }
430
431 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
432 {
433 priv->dmsr = 0;
434 return get_msr(priv, priv->membase);
435 }
436
437 static void pch_uart_hal_write(struct eg20t_port *priv,
438 const unsigned char *buf, int tx_size)
439 {
440 int i;
441 unsigned int thr;
442
443 for (i = 0; i < tx_size;) {
444 thr = buf[i++];
445 iowrite8(thr, priv->membase + PCH_UART_THR);
446 }
447 }
448
449 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
450 int rx_size)
451 {
452 int i;
453 u8 rbr, lsr;
454
455 lsr = ioread8(priv->membase + UART_LSR);
456 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
457 i < rx_size && lsr & UART_LSR_DR;
458 lsr = ioread8(priv->membase + UART_LSR)) {
459 rbr = ioread8(priv->membase + PCH_UART_RBR);
460 buf[i++] = rbr;
461 }
462 return i;
463 }
464
465 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
466 {
467 unsigned int iir;
468 int ret;
469
470 iir = ioread8(priv->membase + UART_IIR);
471 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
472 return ret;
473 }
474
475 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
476 {
477 return ioread8(priv->membase + UART_LSR);
478 }
479
480 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
481 {
482 unsigned int lcr;
483
484 lcr = ioread8(priv->membase + UART_LCR);
485 if (on)
486 lcr |= PCH_UART_LCR_SB;
487 else
488 lcr &= ~PCH_UART_LCR_SB;
489
490 iowrite8(lcr, priv->membase + UART_LCR);
491 }
492
493 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
494 int size)
495 {
496 struct uart_port *port;
497 struct tty_struct *tty;
498
499 port = &priv->port;
500 tty = tty_port_tty_get(&port->state->port);
501 if (!tty) {
502 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
503 return -EBUSY;
504 }
505
506 tty_insert_flip_string(tty, buf, size);
507 tty_flip_buffer_push(tty);
508 tty_kref_put(tty);
509
510 return 0;
511 }
512
513 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
514 {
515 int ret;
516 struct uart_port *port = &priv->port;
517
518 if (port->x_char) {
519 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
520 __func__, port->x_char, jiffies);
521 buf[0] = port->x_char;
522 port->x_char = 0;
523 ret = 1;
524 } else {
525 ret = 0;
526 }
527
528 return ret;
529 }
530
531 static int dma_push_rx(struct eg20t_port *priv, int size)
532 {
533 struct tty_struct *tty;
534 int room;
535 struct uart_port *port = &priv->port;
536
537 port = &priv->port;
538 tty = tty_port_tty_get(&port->state->port);
539 if (!tty) {
540 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
541 return 0;
542 }
543
544 room = tty_buffer_request_room(tty, size);
545
546 if (room < size)
547 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
548 size - room);
549 if (!room)
550 return room;
551
552 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
553
554 port->icount.rx += room;
555 tty_kref_put(tty);
556
557 return room;
558 }
559
560 static void pch_free_dma(struct uart_port *port)
561 {
562 struct eg20t_port *priv;
563 priv = container_of(port, struct eg20t_port, port);
564
565 if (priv->chan_tx) {
566 dma_release_channel(priv->chan_tx);
567 priv->chan_tx = NULL;
568 }
569 if (priv->chan_rx) {
570 dma_release_channel(priv->chan_rx);
571 priv->chan_rx = NULL;
572 }
573 if (sg_dma_address(&priv->sg_rx))
574 dma_free_coherent(port->dev, port->fifosize,
575 sg_virt(&priv->sg_rx),
576 sg_dma_address(&priv->sg_rx));
577
578 return;
579 }
580
581 static bool filter(struct dma_chan *chan, void *slave)
582 {
583 struct pch_dma_slave *param = slave;
584
585 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
586 chan->device->dev)) {
587 chan->private = param;
588 return true;
589 } else {
590 return false;
591 }
592 }
593
594 static void pch_request_dma(struct uart_port *port)
595 {
596 dma_cap_mask_t mask;
597 struct dma_chan *chan;
598 struct pci_dev *dma_dev;
599 struct pch_dma_slave *param;
600 struct eg20t_port *priv =
601 container_of(port, struct eg20t_port, port);
602 dma_cap_zero(mask);
603 dma_cap_set(DMA_SLAVE, mask);
604
605 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
606 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
607 information */
608 /* Set Tx DMA */
609 param = &priv->param_tx;
610 param->dma_dev = &dma_dev->dev;
611 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
612
613 param->tx_reg = port->mapbase + UART_TX;
614 chan = dma_request_channel(mask, filter, param);
615 if (!chan) {
616 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
617 __func__);
618 return;
619 }
620 priv->chan_tx = chan;
621
622 /* Set Rx DMA */
623 param = &priv->param_rx;
624 param->dma_dev = &dma_dev->dev;
625 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
626
627 param->rx_reg = port->mapbase + UART_RX;
628 chan = dma_request_channel(mask, filter, param);
629 if (!chan) {
630 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
631 __func__);
632 dma_release_channel(priv->chan_tx);
633 priv->chan_tx = NULL;
634 return;
635 }
636
637 /* Get Consistent memory for DMA */
638 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
639 &priv->rx_buf_dma, GFP_KERNEL);
640 priv->chan_rx = chan;
641 }
642
643 static void pch_dma_rx_complete(void *arg)
644 {
645 struct eg20t_port *priv = arg;
646 struct uart_port *port = &priv->port;
647 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
648 int count;
649
650 if (!tty) {
651 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
652 return;
653 }
654
655 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
656 count = dma_push_rx(priv, priv->trigger_level);
657 if (count)
658 tty_flip_buffer_push(tty);
659 tty_kref_put(tty);
660 async_tx_ack(priv->desc_rx);
661 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
662 }
663
664 static void pch_dma_tx_complete(void *arg)
665 {
666 struct eg20t_port *priv = arg;
667 struct uart_port *port = &priv->port;
668 struct circ_buf *xmit = &port->state->xmit;
669 struct scatterlist *sg = priv->sg_tx_p;
670 int i;
671
672 for (i = 0; i < priv->nent; i++, sg++) {
673 xmit->tail += sg_dma_len(sg);
674 port->icount.tx += sg_dma_len(sg);
675 }
676 xmit->tail &= UART_XMIT_SIZE - 1;
677 async_tx_ack(priv->desc_tx);
678 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
679 priv->tx_dma_use = 0;
680 priv->nent = 0;
681 kfree(priv->sg_tx_p);
682 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
683 }
684
685 static int pop_tx(struct eg20t_port *priv, int size)
686 {
687 int count = 0;
688 struct uart_port *port = &priv->port;
689 struct circ_buf *xmit = &port->state->xmit;
690
691 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
692 goto pop_tx_end;
693
694 do {
695 int cnt_to_end =
696 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
697 int sz = min(size - count, cnt_to_end);
698 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
699 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
700 count += sz;
701 } while (!uart_circ_empty(xmit) && count < size);
702
703 pop_tx_end:
704 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
705 count, size - count, jiffies);
706
707 return count;
708 }
709
710 static int handle_rx_to(struct eg20t_port *priv)
711 {
712 struct pch_uart_buffer *buf;
713 int rx_size;
714 int ret;
715 if (!priv->start_rx) {
716 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
717 return 0;
718 }
719 buf = &priv->rxbuf;
720 do {
721 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
722 ret = push_rx(priv, buf->buf, rx_size);
723 if (ret)
724 return 0;
725 } while (rx_size == buf->size);
726
727 return PCH_UART_HANDLED_RX_INT;
728 }
729
730 static int handle_rx(struct eg20t_port *priv)
731 {
732 return handle_rx_to(priv);
733 }
734
735 static int dma_handle_rx(struct eg20t_port *priv)
736 {
737 struct uart_port *port = &priv->port;
738 struct dma_async_tx_descriptor *desc;
739 struct scatterlist *sg;
740
741 priv = container_of(port, struct eg20t_port, port);
742 sg = &priv->sg_rx;
743
744 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
745
746 sg_dma_len(sg) = priv->trigger_level;
747
748 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
749 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
750 ~PAGE_MASK);
751
752 sg_dma_address(sg) = priv->rx_buf_dma;
753
754 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx,
755 sg, 1, DMA_FROM_DEVICE,
756 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
757
758 if (!desc)
759 return 0;
760
761 priv->desc_rx = desc;
762 desc->callback = pch_dma_rx_complete;
763 desc->callback_param = priv;
764 desc->tx_submit(desc);
765 dma_async_issue_pending(priv->chan_rx);
766
767 return PCH_UART_HANDLED_RX_INT;
768 }
769
770 static unsigned int handle_tx(struct eg20t_port *priv)
771 {
772 struct uart_port *port = &priv->port;
773 struct circ_buf *xmit = &port->state->xmit;
774 int fifo_size;
775 int tx_size;
776 int size;
777 int tx_empty;
778
779 if (!priv->start_tx) {
780 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
781 __func__, jiffies);
782 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
783 priv->tx_empty = 1;
784 return 0;
785 }
786
787 fifo_size = max(priv->fifo_size, 1);
788 tx_empty = 1;
789 if (pop_tx_x(priv, xmit->buf)) {
790 pch_uart_hal_write(priv, xmit->buf, 1);
791 port->icount.tx++;
792 tx_empty = 0;
793 fifo_size--;
794 }
795 size = min(xmit->head - xmit->tail, fifo_size);
796 if (size < 0)
797 size = fifo_size;
798
799 tx_size = pop_tx(priv, size);
800 if (tx_size > 0) {
801 port->icount.tx += tx_size;
802 tx_empty = 0;
803 }
804
805 priv->tx_empty = tx_empty;
806
807 if (tx_empty) {
808 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
809 uart_write_wakeup(port);
810 }
811
812 return PCH_UART_HANDLED_TX_INT;
813 }
814
815 static unsigned int dma_handle_tx(struct eg20t_port *priv)
816 {
817 struct uart_port *port = &priv->port;
818 struct circ_buf *xmit = &port->state->xmit;
819 struct scatterlist *sg;
820 int nent;
821 int fifo_size;
822 int tx_empty;
823 struct dma_async_tx_descriptor *desc;
824 int num;
825 int i;
826 int bytes;
827 int size;
828 int rem;
829
830 if (!priv->start_tx) {
831 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
832 __func__, jiffies);
833 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
834 priv->tx_empty = 1;
835 return 0;
836 }
837
838 if (priv->tx_dma_use) {
839 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
840 __func__, jiffies);
841 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
842 priv->tx_empty = 1;
843 return 0;
844 }
845
846 fifo_size = max(priv->fifo_size, 1);
847 tx_empty = 1;
848 if (pop_tx_x(priv, xmit->buf)) {
849 pch_uart_hal_write(priv, xmit->buf, 1);
850 port->icount.tx++;
851 tx_empty = 0;
852 fifo_size--;
853 }
854
855 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
856 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
857 xmit->tail, UART_XMIT_SIZE));
858 if (!bytes) {
859 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
860 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
861 uart_write_wakeup(port);
862 return 0;
863 }
864
865 if (bytes > fifo_size) {
866 num = bytes / fifo_size + 1;
867 size = fifo_size;
868 rem = bytes % fifo_size;
869 } else {
870 num = 1;
871 size = bytes;
872 rem = bytes;
873 }
874
875 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
876 __func__, num, size, rem);
877
878 priv->tx_dma_use = 1;
879
880 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
881
882 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
883 sg = priv->sg_tx_p;
884
885 for (i = 0; i < num; i++, sg++) {
886 if (i == (num - 1))
887 sg_set_page(sg, virt_to_page(xmit->buf),
888 rem, fifo_size * i);
889 else
890 sg_set_page(sg, virt_to_page(xmit->buf),
891 size, fifo_size * i);
892 }
893
894 sg = priv->sg_tx_p;
895 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
896 if (!nent) {
897 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
898 return 0;
899 }
900 priv->nent = nent;
901
902 for (i = 0; i < nent; i++, sg++) {
903 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
904 fifo_size * i;
905 sg_dma_address(sg) = (sg_dma_address(sg) &
906 ~(UART_XMIT_SIZE - 1)) + sg->offset;
907 if (i == (nent - 1))
908 sg_dma_len(sg) = rem;
909 else
910 sg_dma_len(sg) = size;
911 }
912
913 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx,
914 priv->sg_tx_p, nent, DMA_TO_DEVICE,
915 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
916 if (!desc) {
917 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
918 __func__);
919 return 0;
920 }
921 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
922 priv->desc_tx = desc;
923 desc->callback = pch_dma_tx_complete;
924 desc->callback_param = priv;
925
926 desc->tx_submit(desc);
927
928 dma_async_issue_pending(priv->chan_tx);
929
930 return PCH_UART_HANDLED_TX_INT;
931 }
932
933 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
934 {
935 u8 fcr = ioread8(priv->membase + UART_FCR);
936
937 /* Reset FIFO */
938 fcr |= UART_FCR_CLEAR_RCVR;
939 iowrite8(fcr, priv->membase + UART_FCR);
940
941 if (lsr & PCH_UART_LSR_ERR)
942 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
943
944 if (lsr & UART_LSR_FE)
945 dev_err(&priv->pdev->dev, "Framing Error\n");
946
947 if (lsr & UART_LSR_PE)
948 dev_err(&priv->pdev->dev, "Parity Error\n");
949
950 if (lsr & UART_LSR_OE)
951 dev_err(&priv->pdev->dev, "Overrun Error\n");
952 }
953
954 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
955 {
956 struct eg20t_port *priv = dev_id;
957 unsigned int handled;
958 u8 lsr;
959 int ret = 0;
960 unsigned int iid;
961 unsigned long flags;
962
963 spin_lock_irqsave(&priv->port.lock, flags);
964 handled = 0;
965 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
966 switch (iid) {
967 case PCH_UART_IID_RLS: /* Receiver Line Status */
968 lsr = pch_uart_hal_get_line_status(priv);
969 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
970 UART_LSR_PE | UART_LSR_OE)) {
971 pch_uart_err_ir(priv, lsr);
972 ret = PCH_UART_HANDLED_RX_ERR_INT;
973 }
974 break;
975 case PCH_UART_IID_RDR: /* Received Data Ready */
976 if (priv->use_dma) {
977 pch_uart_hal_disable_interrupt(priv,
978 PCH_UART_HAL_RX_INT);
979 ret = dma_handle_rx(priv);
980 if (!ret)
981 pch_uart_hal_enable_interrupt(priv,
982 PCH_UART_HAL_RX_INT);
983 } else {
984 ret = handle_rx(priv);
985 }
986 break;
987 case PCH_UART_IID_RDR_TO: /* Received Data Ready
988 (FIFO Timeout) */
989 ret = handle_rx_to(priv);
990 break;
991 case PCH_UART_IID_THRE: /* Transmitter Holding Register
992 Empty */
993 if (priv->use_dma)
994 ret = dma_handle_tx(priv);
995 else
996 ret = handle_tx(priv);
997 break;
998 case PCH_UART_IID_MS: /* Modem Status */
999 ret = PCH_UART_HANDLED_MS_INT;
1000 break;
1001 default: /* Never junp to this label */
1002 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1003 iid, jiffies);
1004 ret = -1;
1005 break;
1006 }
1007 handled |= (unsigned int)ret;
1008 }
1009 if (handled == 0 && iid <= 1) {
1010 if (priv->int_dis_flag)
1011 priv->int_dis_flag = 0;
1012 }
1013
1014 spin_unlock_irqrestore(&priv->port.lock, flags);
1015 return IRQ_RETVAL(handled);
1016 }
1017
1018 /* This function tests whether the transmitter fifo and shifter for the port
1019 described by 'port' is empty. */
1020 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1021 {
1022 struct eg20t_port *priv;
1023 int ret;
1024 priv = container_of(port, struct eg20t_port, port);
1025 if (priv->tx_empty)
1026 ret = TIOCSER_TEMT;
1027 else
1028 ret = 0;
1029
1030 return ret;
1031 }
1032
1033 /* Returns the current state of modem control inputs. */
1034 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1035 {
1036 struct eg20t_port *priv;
1037 u8 modem;
1038 unsigned int ret = 0;
1039
1040 priv = container_of(port, struct eg20t_port, port);
1041 modem = pch_uart_hal_get_modem(priv);
1042
1043 if (modem & UART_MSR_DCD)
1044 ret |= TIOCM_CAR;
1045
1046 if (modem & UART_MSR_RI)
1047 ret |= TIOCM_RNG;
1048
1049 if (modem & UART_MSR_DSR)
1050 ret |= TIOCM_DSR;
1051
1052 if (modem & UART_MSR_CTS)
1053 ret |= TIOCM_CTS;
1054
1055 return ret;
1056 }
1057
1058 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1059 {
1060 u32 mcr = 0;
1061 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1062
1063 if (mctrl & TIOCM_DTR)
1064 mcr |= UART_MCR_DTR;
1065 if (mctrl & TIOCM_RTS)
1066 mcr |= UART_MCR_RTS;
1067 if (mctrl & TIOCM_LOOP)
1068 mcr |= UART_MCR_LOOP;
1069
1070 if (priv->mcr & UART_MCR_AFE)
1071 mcr |= UART_MCR_AFE;
1072
1073 if (mctrl)
1074 iowrite8(mcr, priv->membase + UART_MCR);
1075 }
1076
1077 static void pch_uart_stop_tx(struct uart_port *port)
1078 {
1079 struct eg20t_port *priv;
1080 priv = container_of(port, struct eg20t_port, port);
1081 priv->start_tx = 0;
1082 priv->tx_dma_use = 0;
1083 }
1084
1085 static void pch_uart_start_tx(struct uart_port *port)
1086 {
1087 struct eg20t_port *priv;
1088
1089 priv = container_of(port, struct eg20t_port, port);
1090
1091 if (priv->use_dma) {
1092 if (priv->tx_dma_use) {
1093 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1094 __func__);
1095 return;
1096 }
1097 }
1098
1099 priv->start_tx = 1;
1100 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1101 }
1102
1103 static void pch_uart_stop_rx(struct uart_port *port)
1104 {
1105 struct eg20t_port *priv;
1106 priv = container_of(port, struct eg20t_port, port);
1107 priv->start_rx = 0;
1108 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1109 priv->int_dis_flag = 1;
1110 }
1111
1112 /* Enable the modem status interrupts. */
1113 static void pch_uart_enable_ms(struct uart_port *port)
1114 {
1115 struct eg20t_port *priv;
1116 priv = container_of(port, struct eg20t_port, port);
1117 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1118 }
1119
1120 /* Control the transmission of a break signal. */
1121 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1122 {
1123 struct eg20t_port *priv;
1124 unsigned long flags;
1125
1126 priv = container_of(port, struct eg20t_port, port);
1127 spin_lock_irqsave(&port->lock, flags);
1128 pch_uart_hal_set_break(priv, ctl);
1129 spin_unlock_irqrestore(&port->lock, flags);
1130 }
1131
1132 /* Grab any interrupt resources and initialise any low level driver state. */
1133 static int pch_uart_startup(struct uart_port *port)
1134 {
1135 struct eg20t_port *priv;
1136 int ret;
1137 int fifo_size;
1138 int trigger_level;
1139
1140 priv = container_of(port, struct eg20t_port, port);
1141 priv->tx_empty = 1;
1142
1143 if (port->uartclk)
1144 priv->base_baud = port->uartclk;
1145 else
1146 port->uartclk = priv->base_baud;
1147
1148 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1149 ret = pch_uart_hal_set_line(priv, default_baud,
1150 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1151 PCH_UART_HAL_STB1);
1152 if (ret)
1153 return ret;
1154
1155 switch (priv->fifo_size) {
1156 case 256:
1157 fifo_size = PCH_UART_HAL_FIFO256;
1158 break;
1159 case 64:
1160 fifo_size = PCH_UART_HAL_FIFO64;
1161 break;
1162 case 16:
1163 fifo_size = PCH_UART_HAL_FIFO16;
1164 case 1:
1165 default:
1166 fifo_size = PCH_UART_HAL_FIFO_DIS;
1167 break;
1168 }
1169
1170 switch (priv->trigger) {
1171 case PCH_UART_HAL_TRIGGER1:
1172 trigger_level = 1;
1173 break;
1174 case PCH_UART_HAL_TRIGGER_L:
1175 trigger_level = priv->fifo_size / 4;
1176 break;
1177 case PCH_UART_HAL_TRIGGER_M:
1178 trigger_level = priv->fifo_size / 2;
1179 break;
1180 case PCH_UART_HAL_TRIGGER_H:
1181 default:
1182 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1183 break;
1184 }
1185
1186 priv->trigger_level = trigger_level;
1187 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1188 fifo_size, priv->trigger);
1189 if (ret < 0)
1190 return ret;
1191
1192 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1193 KBUILD_MODNAME, priv);
1194 if (ret < 0)
1195 return ret;
1196
1197 if (priv->use_dma)
1198 pch_request_dma(port);
1199
1200 priv->start_rx = 1;
1201 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1202 uart_update_timeout(port, CS8, default_baud);
1203
1204 return 0;
1205 }
1206
1207 static void pch_uart_shutdown(struct uart_port *port)
1208 {
1209 struct eg20t_port *priv;
1210 int ret;
1211
1212 priv = container_of(port, struct eg20t_port, port);
1213 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1214 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1215 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1216 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1217 if (ret)
1218 dev_err(priv->port.dev,
1219 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1220
1221 pch_free_dma(port);
1222
1223 free_irq(priv->port.irq, priv);
1224 }
1225
1226 /* Change the port parameters, including word length, parity, stop
1227 *bits. Update read_status_mask and ignore_status_mask to indicate
1228 *the types of events we are interested in receiving. */
1229 static void pch_uart_set_termios(struct uart_port *port,
1230 struct ktermios *termios, struct ktermios *old)
1231 {
1232 int baud;
1233 int rtn;
1234 unsigned int parity, bits, stb;
1235 struct eg20t_port *priv;
1236 unsigned long flags;
1237
1238 priv = container_of(port, struct eg20t_port, port);
1239 switch (termios->c_cflag & CSIZE) {
1240 case CS5:
1241 bits = PCH_UART_HAL_5BIT;
1242 break;
1243 case CS6:
1244 bits = PCH_UART_HAL_6BIT;
1245 break;
1246 case CS7:
1247 bits = PCH_UART_HAL_7BIT;
1248 break;
1249 default: /* CS8 */
1250 bits = PCH_UART_HAL_8BIT;
1251 break;
1252 }
1253 if (termios->c_cflag & CSTOPB)
1254 stb = PCH_UART_HAL_STB2;
1255 else
1256 stb = PCH_UART_HAL_STB1;
1257
1258 if (termios->c_cflag & PARENB) {
1259 if (!(termios->c_cflag & PARODD))
1260 parity = PCH_UART_HAL_PARITY_ODD;
1261 else
1262 parity = PCH_UART_HAL_PARITY_EVEN;
1263
1264 } else {
1265 parity = PCH_UART_HAL_PARITY_NONE;
1266 }
1267
1268 /* Only UART0 has auto hardware flow function */
1269 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1270 priv->mcr |= UART_MCR_AFE;
1271 else
1272 priv->mcr &= ~UART_MCR_AFE;
1273
1274 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1275
1276 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1277
1278 spin_lock_irqsave(&port->lock, flags);
1279
1280 uart_update_timeout(port, termios->c_cflag, baud);
1281 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1282 if (rtn)
1283 goto out;
1284
1285 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1286 /* Don't rewrite B0 */
1287 if (tty_termios_baud_rate(termios))
1288 tty_termios_encode_baud_rate(termios, baud, baud);
1289
1290 out:
1291 spin_unlock_irqrestore(&port->lock, flags);
1292 }
1293
1294 static const char *pch_uart_type(struct uart_port *port)
1295 {
1296 return KBUILD_MODNAME;
1297 }
1298
1299 static void pch_uart_release_port(struct uart_port *port)
1300 {
1301 struct eg20t_port *priv;
1302
1303 priv = container_of(port, struct eg20t_port, port);
1304 pci_iounmap(priv->pdev, priv->membase);
1305 pci_release_regions(priv->pdev);
1306 }
1307
1308 static int pch_uart_request_port(struct uart_port *port)
1309 {
1310 struct eg20t_port *priv;
1311 int ret;
1312 void __iomem *membase;
1313
1314 priv = container_of(port, struct eg20t_port, port);
1315 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1316 if (ret < 0)
1317 return -EBUSY;
1318
1319 membase = pci_iomap(priv->pdev, 1, 0);
1320 if (!membase) {
1321 pci_release_regions(priv->pdev);
1322 return -EBUSY;
1323 }
1324 priv->membase = port->membase = membase;
1325
1326 return 0;
1327 }
1328
1329 static void pch_uart_config_port(struct uart_port *port, int type)
1330 {
1331 struct eg20t_port *priv;
1332
1333 priv = container_of(port, struct eg20t_port, port);
1334 if (type & UART_CONFIG_TYPE) {
1335 port->type = priv->port_type;
1336 pch_uart_request_port(port);
1337 }
1338 }
1339
1340 static int pch_uart_verify_port(struct uart_port *port,
1341 struct serial_struct *serinfo)
1342 {
1343 struct eg20t_port *priv;
1344
1345 priv = container_of(port, struct eg20t_port, port);
1346 if (serinfo->flags & UPF_LOW_LATENCY) {
1347 dev_info(priv->port.dev,
1348 "PCH UART : Use PIO Mode (without DMA)\n");
1349 priv->use_dma = 0;
1350 serinfo->flags &= ~UPF_LOW_LATENCY;
1351 } else {
1352 #ifndef CONFIG_PCH_DMA
1353 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1354 __func__);
1355 return -EOPNOTSUPP;
1356 #endif
1357 priv->use_dma_flag = 1;
1358 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1359 if (!priv->use_dma)
1360 pch_request_dma(port);
1361 priv->use_dma = 1;
1362 }
1363
1364 return 0;
1365 }
1366
1367 static struct uart_ops pch_uart_ops = {
1368 .tx_empty = pch_uart_tx_empty,
1369 .set_mctrl = pch_uart_set_mctrl,
1370 .get_mctrl = pch_uart_get_mctrl,
1371 .stop_tx = pch_uart_stop_tx,
1372 .start_tx = pch_uart_start_tx,
1373 .stop_rx = pch_uart_stop_rx,
1374 .enable_ms = pch_uart_enable_ms,
1375 .break_ctl = pch_uart_break_ctl,
1376 .startup = pch_uart_startup,
1377 .shutdown = pch_uart_shutdown,
1378 .set_termios = pch_uart_set_termios,
1379 /* .pm = pch_uart_pm, Not supported yet */
1380 /* .set_wake = pch_uart_set_wake, Not supported yet */
1381 .type = pch_uart_type,
1382 .release_port = pch_uart_release_port,
1383 .request_port = pch_uart_request_port,
1384 .config_port = pch_uart_config_port,
1385 .verify_port = pch_uart_verify_port
1386 };
1387
1388 static struct uart_driver pch_uart_driver = {
1389 .owner = THIS_MODULE,
1390 .driver_name = KBUILD_MODNAME,
1391 .dev_name = PCH_UART_DRIVER_DEVICE,
1392 .major = 0,
1393 .minor = 0,
1394 .nr = PCH_UART_NR,
1395 };
1396
1397 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1398 const struct pci_device_id *id)
1399 {
1400 struct eg20t_port *priv;
1401 int ret;
1402 unsigned int iobase;
1403 unsigned int mapbase;
1404 unsigned char *rxbuf;
1405 int fifosize, base_baud;
1406 int port_type;
1407 struct pch_uart_driver_data *board;
1408 const char *board_name;
1409
1410 board = &drv_dat[id->driver_data];
1411 port_type = board->port_type;
1412
1413 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1414 if (priv == NULL)
1415 goto init_port_alloc_err;
1416
1417 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1418 if (!rxbuf)
1419 goto init_port_free_txbuf;
1420
1421 base_baud = 1843200; /* 1.8432MHz */
1422
1423 /* quirk for CM-iTC board */
1424 board_name = dmi_get_system_info(DMI_BOARD_NAME);
1425 if (board_name && strstr(board_name, "CM-iTC"))
1426 base_baud = 192000000; /* 192.0MHz */
1427
1428 switch (port_type) {
1429 case PORT_UNKNOWN:
1430 fifosize = 256; /* EG20T/ML7213: UART0 */
1431 break;
1432 case PORT_8250:
1433 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1434 break;
1435 default:
1436 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1437 goto init_port_hal_free;
1438 }
1439
1440 iobase = pci_resource_start(pdev, 0);
1441 mapbase = pci_resource_start(pdev, 1);
1442 priv->mapbase = mapbase;
1443 priv->iobase = iobase;
1444 priv->pdev = pdev;
1445 priv->tx_empty = 1;
1446 priv->rxbuf.buf = rxbuf;
1447 priv->rxbuf.size = PAGE_SIZE;
1448
1449 priv->fifo_size = fifosize;
1450 priv->base_baud = base_baud;
1451 priv->port_type = PORT_MAX_8250 + port_type + 1;
1452 priv->port.dev = &pdev->dev;
1453 priv->port.iobase = iobase;
1454 priv->port.membase = NULL;
1455 priv->port.mapbase = mapbase;
1456 priv->port.irq = pdev->irq;
1457 priv->port.iotype = UPIO_PORT;
1458 priv->port.ops = &pch_uart_ops;
1459 priv->port.flags = UPF_BOOT_AUTOCONF;
1460 priv->port.fifosize = fifosize;
1461 priv->port.line = board->line_no;
1462 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1463
1464 spin_lock_init(&priv->port.lock);
1465
1466 pci_set_drvdata(pdev, priv);
1467 pch_uart_hal_request(pdev, fifosize, base_baud);
1468
1469 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1470 if (ret < 0)
1471 goto init_port_hal_free;
1472
1473 return priv;
1474
1475 init_port_hal_free:
1476 free_page((unsigned long)rxbuf);
1477 init_port_free_txbuf:
1478 kfree(priv);
1479 init_port_alloc_err:
1480
1481 return NULL;
1482 }
1483
1484 static void pch_uart_exit_port(struct eg20t_port *priv)
1485 {
1486 uart_remove_one_port(&pch_uart_driver, &priv->port);
1487 pci_set_drvdata(priv->pdev, NULL);
1488 free_page((unsigned long)priv->rxbuf.buf);
1489 }
1490
1491 static void pch_uart_pci_remove(struct pci_dev *pdev)
1492 {
1493 struct eg20t_port *priv;
1494
1495 priv = (struct eg20t_port *)pci_get_drvdata(pdev);
1496 pch_uart_exit_port(priv);
1497 pci_disable_device(pdev);
1498 kfree(priv);
1499 return;
1500 }
1501 #ifdef CONFIG_PM
1502 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1503 {
1504 struct eg20t_port *priv = pci_get_drvdata(pdev);
1505
1506 uart_suspend_port(&pch_uart_driver, &priv->port);
1507
1508 pci_save_state(pdev);
1509 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1510 return 0;
1511 }
1512
1513 static int pch_uart_pci_resume(struct pci_dev *pdev)
1514 {
1515 struct eg20t_port *priv = pci_get_drvdata(pdev);
1516 int ret;
1517
1518 pci_set_power_state(pdev, PCI_D0);
1519 pci_restore_state(pdev);
1520
1521 ret = pci_enable_device(pdev);
1522 if (ret) {
1523 dev_err(&pdev->dev,
1524 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1525 return ret;
1526 }
1527
1528 uart_resume_port(&pch_uart_driver, &priv->port);
1529
1530 return 0;
1531 }
1532 #else
1533 #define pch_uart_pci_suspend NULL
1534 #define pch_uart_pci_resume NULL
1535 #endif
1536
1537 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1538 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1539 .driver_data = pch_et20t_uart0},
1540 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1541 .driver_data = pch_et20t_uart1},
1542 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1543 .driver_data = pch_et20t_uart2},
1544 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1545 .driver_data = pch_et20t_uart3},
1546 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1547 .driver_data = pch_ml7213_uart0},
1548 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1549 .driver_data = pch_ml7213_uart1},
1550 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1551 .driver_data = pch_ml7213_uart2},
1552 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1553 .driver_data = pch_ml7223_uart0},
1554 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1555 .driver_data = pch_ml7223_uart1},
1556 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1557 .driver_data = pch_ml7831_uart0},
1558 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1559 .driver_data = pch_ml7831_uart1},
1560 {0,},
1561 };
1562
1563 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1564 const struct pci_device_id *id)
1565 {
1566 int ret;
1567 struct eg20t_port *priv;
1568
1569 ret = pci_enable_device(pdev);
1570 if (ret < 0)
1571 goto probe_error;
1572
1573 priv = pch_uart_init_port(pdev, id);
1574 if (!priv) {
1575 ret = -EBUSY;
1576 goto probe_disable_device;
1577 }
1578 pci_set_drvdata(pdev, priv);
1579
1580 return ret;
1581
1582 probe_disable_device:
1583 pci_disable_device(pdev);
1584 probe_error:
1585 return ret;
1586 }
1587
1588 static struct pci_driver pch_uart_pci_driver = {
1589 .name = "pch_uart",
1590 .id_table = pch_uart_pci_id,
1591 .probe = pch_uart_pci_probe,
1592 .remove = __devexit_p(pch_uart_pci_remove),
1593 .suspend = pch_uart_pci_suspend,
1594 .resume = pch_uart_pci_resume,
1595 };
1596
1597 static int __init pch_uart_module_init(void)
1598 {
1599 int ret;
1600
1601 /* register as UART driver */
1602 ret = uart_register_driver(&pch_uart_driver);
1603 if (ret < 0)
1604 return ret;
1605
1606 /* register as PCI driver */
1607 ret = pci_register_driver(&pch_uart_pci_driver);
1608 if (ret < 0)
1609 uart_unregister_driver(&pch_uart_driver);
1610
1611 return ret;
1612 }
1613 module_init(pch_uart_module_init);
1614
1615 static void __exit pch_uart_module_exit(void)
1616 {
1617 pci_unregister_driver(&pch_uart_pci_driver);
1618 uart_unregister_driver(&pch_uart_driver);
1619 }
1620 module_exit(pch_uart_module_exit);
1621
1622 MODULE_LICENSE("GPL v2");
1623 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1624 module_param(default_baud, uint, S_IRUGO);
Linux with added FPC-III support