drivers/tty/serial/pmac_zilog.h

   1 #ifndef __PMAC_ZILOG_H__
   2 #define __PMAC_ZILOG_H__
   3
   4 #ifdef CONFIG_PPC_PMAC
   5 #define pmz_debug(fmt, arg...)  dev_dbg(&uap->dev->ofdev.dev, fmt, ## arg)
   6 #define pmz_error(fmt, arg...)  dev_err(&uap->dev->ofdev.dev, fmt, ## arg)
   7 #define pmz_info(fmt, arg...)   dev_info(&uap->dev->ofdev.dev, fmt, ## arg)
   8 #else
   9 #define pmz_debug(fmt, arg...)  dev_dbg(&uap->node->dev, fmt, ## arg)
  10 #define pmz_error(fmt, arg...)  dev_err(&uap->node->dev, fmt, ## arg)
  11 #define pmz_info(fmt, arg...)   dev_info(&uap->node->dev, fmt, ## arg)
  12 #endif
  13
  14 /*
  15  * At most 2 ESCCs with 2 ports each
  16  */
  17 #define MAX_ZS_PORTS    4
  18
  19 /*
  20  * We wrap our port structure around the generic uart_port.
  21  */
  22 #define NUM_ZSREGS    17
  23
  24 struct uart_pmac_port {
  25         struct uart_port                port;
  26         struct uart_pmac_port           *mate;
  27
  28 #ifdef CONFIG_PPC_PMAC
  29         /* macio_dev for the escc holding this port (maybe be null on
  30          * early inited port)
  31          */
  32         struct macio_dev                *dev;
  33         /* device node to this port, this points to one of 2 childs
  34          * of "escc" node (ie. ch-a or ch-b)
  35          */
  36         struct device_node              *node;
  37 #else
  38         struct platform_device          *node;
  39 #endif
  40
  41         /* Port type as obtained from device tree (IRDA, modem, ...) */
  42         int                             port_type;
  43         u8                              curregs[NUM_ZSREGS];
  44
  45         unsigned int                    flags;
  46 #define PMACZILOG_FLAG_IS_CONS          0x00000001
  47 #define PMACZILOG_FLAG_IS_KGDB          0x00000002
  48 #define PMACZILOG_FLAG_MODEM_STATUS     0x00000004
  49 #define PMACZILOG_FLAG_IS_CHANNEL_A     0x00000008
  50 #define PMACZILOG_FLAG_REGS_HELD        0x00000010
  51 #define PMACZILOG_FLAG_TX_STOPPED       0x00000020
  52 #define PMACZILOG_FLAG_TX_ACTIVE        0x00000040
  53 #define PMACZILOG_FLAG_ENABLED          0x00000080
  54 #define PMACZILOG_FLAG_IS_IRDA          0x00000100
  55 #define PMACZILOG_FLAG_IS_INTMODEM      0x00000200
  56 #define PMACZILOG_FLAG_HAS_DMA          0x00000400
  57 #define PMACZILOG_FLAG_RSRC_REQUESTED   0x00000800
  58 #define PMACZILOG_FLAG_IS_ASLEEP        0x00001000
  59 #define PMACZILOG_FLAG_IS_OPEN          0x00002000
  60 #define PMACZILOG_FLAG_IS_IRQ_ON        0x00004000
  61 #define PMACZILOG_FLAG_IS_EXTCLK        0x00008000
  62 #define PMACZILOG_FLAG_BREAK            0x00010000
  63
  64         unsigned char                   parity_mask;
  65         unsigned char                   prev_status;
  66
  67         volatile u8                     __iomem *control_reg;
  68         volatile u8                     __iomem *data_reg;
  69
  70 #ifdef CONFIG_PPC_PMAC
  71         unsigned int                    tx_dma_irq;
  72         unsigned int                    rx_dma_irq;
  73         volatile struct dbdma_regs      __iomem *tx_dma_regs;
  74         volatile struct dbdma_regs      __iomem *rx_dma_regs;
  75 #endif
  76
  77         struct ktermios                 termios_cache;
  78 };
  79
  80 #define to_pmz(p) ((struct uart_pmac_port *)(p))
  81
  82 static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
  83 {
  84         if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
  85                 return uap;
  86         return uap->mate;
  87 }
  88
  89 /*
  90  * Register accessors. Note that we don't need to enforce a recovery
  91  * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
  92  * though if we try to use this driver on older machines, we might have
  93  * to add it back
  94  */
  95 static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
  96 {
  97         if (reg != 0)
  98                 writeb(reg, port->control_reg);
  99         return readb(port->control_reg);
 100 }
 101
 102 static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
 103 {
 104         if (reg != 0)
 105                 writeb(reg, port->control_reg);
 106         writeb(value, port->control_reg);
 107 }
 108
 109 static inline u8 read_zsdata(struct uart_pmac_port *port)
 110 {
 111         return readb(port->data_reg);
 112 }
 113
 114 static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
 115 {
 116         writeb(data, port->data_reg);
 117 }
 118
 119 static inline void zssync(struct uart_pmac_port *port)
 120 {
 121         (void)readb(port->control_reg);
 122 }
 123
 124 /* Conversion routines to/from brg time constants from/to bits
 125  * per second.
 126  */
 127 #define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
 128 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
 129
 130 #define ZS_CLOCK         3686400        /* Z8530 RTxC input clock rate */
 131
 132 /* The Zilog register set */
 133
 134 #define FLAG    0x7e
 135
 136 /* Write Register 0 */
 137 #define R0      0               /* Register selects */
 138 #define R1      1
 139 #define R2      2
 140 #define R3      3
 141 #define R4      4
 142 #define R5      5
 143 #define R6      6
 144 #define R7      7
 145 #define R8      8
 146 #define R9      9
 147 #define R10     10
 148 #define R11     11
 149 #define R12     12
 150 #define R13     13
 151 #define R14     14
 152 #define R15     15
 153 #define R7P     16
 154
 155 #define NULLCODE        0       /* Null Code */
 156 #define POINT_HIGH      0x8     /* Select upper half of registers */
 157 #define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
 158 #define SEND_ABORT      0x18    /* HDLC Abort */
 159 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
 160 #define RES_Tx_P        0x28    /* Reset TxINT Pending */
 161 #define ERR_RES         0x30    /* Error Reset */
 162 #define RES_H_IUS       0x38    /* Reset highest IUS */
 163
 164 #define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
 165 #define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
 166 #define RES_EOM_L       0xC0    /* Reset EOM latch */
 167
 168 /* Write Register 1 */
 169
 170 #define EXT_INT_ENAB    0x1     /* Ext Int Enable */
 171 #define TxINT_ENAB      0x2     /* Tx Int Enable */
 172 #define PAR_SPEC        0x4     /* Parity is special condition */
 173
 174 #define RxINT_DISAB     0       /* Rx Int Disable */
 175 #define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
 176 #define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
 177 #define INT_ERR_Rx      0x18    /* Int on error only */
 178 #define RxINT_MASK      0x18
 179
 180 #define WT_RDY_RT       0x20    /* W/Req reflects recv if 1, xmit if 0 */
 181 #define WT_FN_RDYFN     0x40    /* W/Req pin is DMA request if 1, wait if 0 */
 182 #define WT_RDY_ENAB     0x80    /* Enable W/Req pin */
 183
 184 /* Write Register #2 (Interrupt Vector) */
 185
 186 /* Write Register 3 */
 187
 188 #define RxENABLE        0x1     /* Rx Enable */
 189 #define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
 190 #define ADD_SM          0x4     /* Address Search Mode (SDLC) */
 191 #define RxCRC_ENAB      0x8     /* Rx CRC Enable */
 192 #define ENT_HM          0x10    /* Enter Hunt Mode */
 193 #define AUTO_ENAB       0x20    /* Auto Enables */
 194 #define Rx5             0x0     /* Rx 5 Bits/Character */
 195 #define Rx7             0x40    /* Rx 7 Bits/Character */
 196 #define Rx6             0x80    /* Rx 6 Bits/Character */
 197 #define Rx8             0xc0    /* Rx 8 Bits/Character */
 198 #define RxN_MASK        0xc0
 199
 200 /* Write Register 4 */
 201
 202 #define PAR_ENAB        0x1     /* Parity Enable */
 203 #define PAR_EVEN        0x2     /* Parity Even/Odd* */
 204
 205 #define SYNC_ENAB       0       /* Sync Modes Enable */
 206 #define SB1             0x4     /* 1 stop bit/char */
 207 #define SB15            0x8     /* 1.5 stop bits/char */
 208 #define SB2             0xc     /* 2 stop bits/char */
 209 #define SB_MASK         0xc
 210
 211 #define MONSYNC         0       /* 8 Bit Sync character */
 212 #define BISYNC          0x10    /* 16 bit sync character */
 213 #define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 214 #define EXTSYNC         0x30    /* External Sync Mode */
 215
 216 #define X1CLK           0x0     /* x1 clock mode */
 217 #define X16CLK          0x40    /* x16 clock mode */
 218 #define X32CLK          0x80    /* x32 clock mode */
 219 #define X64CLK          0xC0    /* x64 clock mode */
 220 #define XCLK_MASK       0xC0
 221
 222 /* Write Register 5 */
 223
 224 #define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 225 #define RTS             0x2     /* RTS */
 226 #define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 227 #define TxENABLE        0x8     /* Tx Enable */
 228 #define SND_BRK         0x10    /* Send Break */
 229 #define Tx5             0x0     /* Tx 5 bits (or less)/character */
 230 #define Tx7             0x20    /* Tx 7 bits/character */
 231 #define Tx6             0x40    /* Tx 6 bits/character */
 232 #define Tx8             0x60    /* Tx 8 bits/character */
 233 #define TxN_MASK        0x60
 234 #define DTR             0x80    /* DTR */
 235
 236 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 237
 238 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 239
 240 /* Write Register 7' (Some enhanced feature control) */
 241 #define ENEXREAD        0x40    /* Enable read of some write registers */
 242
 243 /* Write Register 8 (transmit buffer) */
 244
 245 /* Write Register 9 (Master interrupt control) */
 246 #define VIS     1       /* Vector Includes Status */
 247 #define NV      2       /* No Vector */
 248 #define DLC     4       /* Disable Lower Chain */
 249 #define MIE     8       /* Master Interrupt Enable */
 250 #define STATHI  0x10    /* Status high */
 251 #define NORESET 0       /* No reset on write to R9 */
 252 #define CHRB    0x40    /* Reset channel B */
 253 #define CHRA    0x80    /* Reset channel A */
 254 #define FHWRES  0xc0    /* Force hardware reset */
 255
 256 /* Write Register 10 (misc control bits) */
 257 #define BIT6    1       /* 6 bit/8bit sync */
 258 #define LOOPMODE 2      /* SDLC Loop mode */
 259 #define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
 260 #define MARKIDLE 8      /* Mark/flag on idle */
 261 #define GAOP    0x10    /* Go active on poll */
 262 #define NRZ     0       /* NRZ mode */
 263 #define NRZI    0x20    /* NRZI mode */
 264 #define FM1     0x40    /* FM1 (transition = 1) */
 265 #define FM0     0x60    /* FM0 (transition = 0) */
 266 #define CRCPS   0x80    /* CRC Preset I/O */
 267
 268 /* Write Register 11 (Clock Mode control) */
 269 #define TRxCXT  0       /* TRxC = Xtal output */
 270 #define TRxCTC  1       /* TRxC = Transmit clock */
 271 #define TRxCBR  2       /* TRxC = BR Generator Output */
 272 #define TRxCDP  3       /* TRxC = DPLL output */
 273 #define TRxCOI  4       /* TRxC O/I */
 274 #define TCRTxCP 0       /* Transmit clock = RTxC pin */
 275 #define TCTRxCP 8       /* Transmit clock = TRxC pin */
 276 #define TCBR    0x10    /* Transmit clock = BR Generator output */
 277 #define TCDPLL  0x18    /* Transmit clock = DPLL output */
 278 #define RCRTxCP 0       /* Receive clock = RTxC pin */
 279 #define RCTRxCP 0x20    /* Receive clock = TRxC pin */
 280 #define RCBR    0x40    /* Receive clock = BR Generator output */
 281 #define RCDPLL  0x60    /* Receive clock = DPLL output */
 282 #define RTxCX   0x80    /* RTxC Xtal/No Xtal */
 283
 284 /* Write Register 12 (lower byte of baud rate generator time constant) */
 285
 286 /* Write Register 13 (upper byte of baud rate generator time constant) */
 287
 288 /* Write Register 14 (Misc control bits) */
 289 #define BRENAB  1       /* Baud rate generator enable */
 290 #define BRSRC   2       /* Baud rate generator source */
 291 #define DTRREQ  4       /* DTR/Request function */
 292 #define AUTOECHO 8      /* Auto Echo */
 293 #define LOOPBAK 0x10    /* Local loopback */
 294 #define SEARCH  0x20    /* Enter search mode */
 295 #define RMC     0x40    /* Reset missing clock */
 296 #define DISDPLL 0x60    /* Disable DPLL */
 297 #define SSBR    0x80    /* Set DPLL source = BR generator */
 298 #define SSRTxC  0xa0    /* Set DPLL source = RTxC */
 299 #define SFMM    0xc0    /* Set FM mode */
 300 #define SNRZI   0xe0    /* Set NRZI mode */
 301
 302 /* Write Register 15 (external/status interrupt control) */
 303 #define EN85C30 1       /* Enable some 85c30-enhanced registers */
 304 #define ZCIE    2       /* Zero count IE */
 305 #define ENSTFIFO 4      /* Enable status FIFO (SDLC) */
 306 #define DCDIE   8       /* DCD IE */
 307 #define SYNCIE  0x10    /* Sync/hunt IE */
 308 #define CTSIE   0x20    /* CTS IE */
 309 #define TxUIE   0x40    /* Tx Underrun/EOM IE */
 310 #define BRKIE   0x80    /* Break/Abort IE */
 311
 312
 313 /* Read Register 0 */
 314 #define Rx_CH_AV        0x1     /* Rx Character Available */
 315 #define ZCOUNT          0x2     /* Zero count */
 316 #define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 317 #define DCD             0x8     /* DCD */
 318 #define SYNC_HUNT       0x10    /* Sync/hunt */
 319 #define CTS             0x20    /* CTS */
 320 #define TxEOM           0x40    /* Tx underrun */
 321 #define BRK_ABRT        0x80    /* Break/Abort */
 322
 323 /* Read Register 1 */
 324 #define ALL_SNT         0x1     /* All sent */
 325 /* Residue Data for 8 Rx bits/char programmed */
 326 #define RES3            0x8     /* 0/3 */
 327 #define RES4            0x4     /* 0/4 */
 328 #define RES5            0xc     /* 0/5 */
 329 #define RES6            0x2     /* 0/6 */
 330 #define RES7            0xa     /* 0/7 */
 331 #define RES8            0x6     /* 0/8 */
 332 #define RES18           0xe     /* 1/8 */
 333 #define RES28           0x0     /* 2/8 */
 334 /* Special Rx Condition Interrupts */
 335 #define PAR_ERR         0x10    /* Parity error */
 336 #define Rx_OVR          0x20    /* Rx Overrun Error */
 337 #define CRC_ERR         0x40    /* CRC/Framing Error */
 338 #define END_FR          0x80    /* End of Frame (SDLC) */
 339
 340 /* Read Register 2 (channel b only) - Interrupt vector */
 341 #define CHB_Tx_EMPTY    0x00
 342 #define CHB_EXT_STAT    0x02
 343 #define CHB_Rx_AVAIL    0x04
 344 #define CHB_SPECIAL     0x06
 345 #define CHA_Tx_EMPTY    0x08
 346 #define CHA_EXT_STAT    0x0a
 347 #define CHA_Rx_AVAIL    0x0c
 348 #define CHA_SPECIAL     0x0e
 349 #define STATUS_MASK     0x06
 350
 351 /* Read Register 3 (interrupt pending register) ch a only */
 352 #define CHBEXT  0x1             /* Channel B Ext/Stat IP */
 353 #define CHBTxIP 0x2             /* Channel B Tx IP */
 354 #define CHBRxIP 0x4             /* Channel B Rx IP */
 355 #define CHAEXT  0x8             /* Channel A Ext/Stat IP */
 356 #define CHATxIP 0x10            /* Channel A Tx IP */
 357 #define CHARxIP 0x20            /* Channel A Rx IP */
 358
 359 /* Read Register 8 (receive data register) */
 360
 361 /* Read Register 10  (misc status bits) */
 362 #define ONLOOP  2               /* On loop */
 363 #define LOOPSEND 0x10           /* Loop sending */
 364 #define CLK2MIS 0x40            /* Two clocks missing */
 365 #define CLK1MIS 0x80            /* One clock missing */
 366
 367 /* Read Register 12 (lower byte of baud rate generator constant) */
 368
 369 /* Read Register 13 (upper byte of baud rate generator constant) */
 370
 371 /* Read Register 15 (value of WR 15) */
 372
 373 /* Misc macros */
 374 #define ZS_CLEARERR(port)    (write_zsreg(port, 0, ERR_RES))
 375 #define ZS_CLEARFIFO(port)   do { volatile unsigned char garbage; \
 376                                      garbage = read_zsdata(port); \
 377                                      garbage = read_zsdata(port); \
 378                                      garbage = read_zsdata(port); \
 379                                 } while(0)
 380
 381 #define ZS_IS_CONS(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
 382 #define ZS_IS_KGDB(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
 383 #define ZS_IS_CHANNEL_A(UP)             ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
 384 #define ZS_REGS_HELD(UP)                ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
 385 #define ZS_TX_STOPPED(UP)               ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
 386 #define ZS_TX_ACTIVE(UP)                ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
 387 #define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
 388 #define ZS_IS_IRDA(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
 389 #define ZS_IS_INTMODEM(UP)              ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
 390 #define ZS_HAS_DMA(UP)                  ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
 391 #define ZS_IS_ASLEEP(UP)                ((UP)->flags & PMACZILOG_FLAG_IS_ASLEEP)
 392 #define ZS_IS_OPEN(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
 393 #define ZS_IS_IRQ_ON(UP)                ((UP)->flags & PMACZILOG_FLAG_IS_IRQ_ON)
 394 #define ZS_IS_EXTCLK(UP)                ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
 395
 396 #endif /* __PMAC_ZILOG_H__ */