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ARM: 7409/1: Do not call flush_cache_user_range with mmap_sem held
[linux/fpc-iii.git] / drivers / tty / serial / sa1100.c
blobef7a21a6a01b1997702c49a7559b13f03007c0d7
1 /*
2 * Driver for SA11x0 serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #define SUPPORT_SYSRQ
25 #endif
26
27 #include <linux/module.h>
28 #include <linux/ioport.h>
29 #include <linux/init.h>
30 #include <linux/console.h>
31 #include <linux/sysrq.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/io.h>
38
39 #include <asm/irq.h>
40 #include <mach/hardware.h>
41 #include <asm/mach/serial_sa1100.h>
42
43 /* We've been assigned a range on the "Low-density serial ports" major */
44 #define SERIAL_SA1100_MAJOR 204
45 #define MINOR_START 5
46
47 #define NR_PORTS 3
48
49 #define SA1100_ISR_PASS_LIMIT 256
50
51 /*
52 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
53 */
54 #define SM_TO_UTSR0(x) ((x) & 0xff)
55 #define SM_TO_UTSR1(x) ((x) >> 8)
56 #define UTSR0_TO_SM(x) ((x))
57 #define UTSR1_TO_SM(x) ((x) << 8)
58
59 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
60 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
61 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
62 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
63 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
64 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
65 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
66
67 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
68 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
69 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
70 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
71 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
72 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
73 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
74
75 /*
76 * This is the size of our serial port register set.
77 */
78 #define UART_PORT_SIZE 0x24
79
80 /*
81 * This determines how often we check the modem status signals
82 * for any change. They generally aren't connected to an IRQ
83 * so we have to poll them. We also check immediately before
84 * filling the TX fifo incase CTS has been dropped.
85 */
86 #define MCTRL_TIMEOUT (250*HZ/1000)
87
88 struct sa1100_port {
89 struct uart_port port;
90 struct timer_list timer;
91 unsigned int old_status;
92 };
93
94 /*
95 * Handle any change of modem status signal since we were last called.
96 */
97 static void sa1100_mctrl_check(struct sa1100_port *sport)
98 {
99 unsigned int status, changed;
100
101 status = sport->port.ops->get_mctrl(&sport->port);
102 changed = status ^ sport->old_status;
103
104 if (changed == 0)
105 return;
106
107 sport->old_status = status;
108
109 if (changed & TIOCM_RI)
110 sport->port.icount.rng++;
111 if (changed & TIOCM_DSR)
112 sport->port.icount.dsr++;
113 if (changed & TIOCM_CAR)
114 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
115 if (changed & TIOCM_CTS)
116 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
117
118 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
119 }
120
121 /*
122 * This is our per-port timeout handler, for checking the
123 * modem status signals.
124 */
125 static void sa1100_timeout(unsigned long data)
126 {
127 struct sa1100_port *sport = (struct sa1100_port *)data;
128 unsigned long flags;
129
130 if (sport->port.state) {
131 spin_lock_irqsave(&sport->port.lock, flags);
132 sa1100_mctrl_check(sport);
133 spin_unlock_irqrestore(&sport->port.lock, flags);
134
135 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
136 }
137 }
138
139 /*
140 * interrupts disabled on entry
141 */
142 static void sa1100_stop_tx(struct uart_port *port)
143 {
144 struct sa1100_port *sport = (struct sa1100_port *)port;
145 u32 utcr3;
146
147 utcr3 = UART_GET_UTCR3(sport);
148 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
149 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
150 }
151
152 /*
153 * port locked and interrupts disabled
154 */
155 static void sa1100_start_tx(struct uart_port *port)
156 {
157 struct sa1100_port *sport = (struct sa1100_port *)port;
158 u32 utcr3;
159
160 utcr3 = UART_GET_UTCR3(sport);
161 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
162 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
163 }
164
165 /*
166 * Interrupts enabled
167 */
168 static void sa1100_stop_rx(struct uart_port *port)
169 {
170 struct sa1100_port *sport = (struct sa1100_port *)port;
171 u32 utcr3;
172
173 utcr3 = UART_GET_UTCR3(sport);
174 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
175 }
176
177 /*
178 * Set the modem control timer to fire immediately.
179 */
180 static void sa1100_enable_ms(struct uart_port *port)
181 {
182 struct sa1100_port *sport = (struct sa1100_port *)port;
183
184 mod_timer(&sport->timer, jiffies);
185 }
186
187 static void
188 sa1100_rx_chars(struct sa1100_port *sport)
189 {
190 struct tty_struct *tty = sport->port.state->port.tty;
191 unsigned int status, ch, flg;
192
193 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
194 UTSR0_TO_SM(UART_GET_UTSR0(sport));
195 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
196 ch = UART_GET_CHAR(sport);
197
198 sport->port.icount.rx++;
199
200 flg = TTY_NORMAL;
201
202 /*
203 * note that the error handling code is
204 * out of the main execution path
205 */
206 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
207 if (status & UTSR1_TO_SM(UTSR1_PRE))
208 sport->port.icount.parity++;
209 else if (status & UTSR1_TO_SM(UTSR1_FRE))
210 sport->port.icount.frame++;
211 if (status & UTSR1_TO_SM(UTSR1_ROR))
212 sport->port.icount.overrun++;
213
214 status &= sport->port.read_status_mask;
215
216 if (status & UTSR1_TO_SM(UTSR1_PRE))
217 flg = TTY_PARITY;
218 else if (status & UTSR1_TO_SM(UTSR1_FRE))
219 flg = TTY_FRAME;
220
221 #ifdef SUPPORT_SYSRQ
222 sport->port.sysrq = 0;
223 #endif
224 }
225
226 if (uart_handle_sysrq_char(&sport->port, ch))
227 goto ignore_char;
228
229 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
230
231 ignore_char:
232 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
233 UTSR0_TO_SM(UART_GET_UTSR0(sport));
234 }
235 tty_flip_buffer_push(tty);
236 }
237
238 static void sa1100_tx_chars(struct sa1100_port *sport)
239 {
240 struct circ_buf *xmit = &sport->port.state->xmit;
241
242 if (sport->port.x_char) {
243 UART_PUT_CHAR(sport, sport->port.x_char);
244 sport->port.icount.tx++;
245 sport->port.x_char = 0;
246 return;
247 }
248
249 /*
250 * Check the modem control lines before
251 * transmitting anything.
252 */
253 sa1100_mctrl_check(sport);
254
255 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
256 sa1100_stop_tx(&sport->port);
257 return;
258 }
259
260 /*
261 * Tried using FIFO (not checking TNF) for fifo fill:
262 * still had the '4 bytes repeated' problem.
263 */
264 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
265 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
266 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
267 sport->port.icount.tx++;
268 if (uart_circ_empty(xmit))
269 break;
270 }
271
272 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
273 uart_write_wakeup(&sport->port);
274
275 if (uart_circ_empty(xmit))
276 sa1100_stop_tx(&sport->port);
277 }
278
279 static irqreturn_t sa1100_int(int irq, void *dev_id)
280 {
281 struct sa1100_port *sport = dev_id;
282 unsigned int status, pass_counter = 0;
283
284 spin_lock(&sport->port.lock);
285 status = UART_GET_UTSR0(sport);
286 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
287 do {
288 if (status & (UTSR0_RFS | UTSR0_RID)) {
289 /* Clear the receiver idle bit, if set */
290 if (status & UTSR0_RID)
291 UART_PUT_UTSR0(sport, UTSR0_RID);
292 sa1100_rx_chars(sport);
293 }
294
295 /* Clear the relevant break bits */
296 if (status & (UTSR0_RBB | UTSR0_REB))
297 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
298
299 if (status & UTSR0_RBB)
300 sport->port.icount.brk++;
301
302 if (status & UTSR0_REB)
303 uart_handle_break(&sport->port);
304
305 if (status & UTSR0_TFS)
306 sa1100_tx_chars(sport);
307 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
308 break;
309 status = UART_GET_UTSR0(sport);
310 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
311 ~UTSR0_TFS;
312 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
313 spin_unlock(&sport->port.lock);
314
315 return IRQ_HANDLED;
316 }
317
318 /*
319 * Return TIOCSER_TEMT when transmitter is not busy.
320 */
321 static unsigned int sa1100_tx_empty(struct uart_port *port)
322 {
323 struct sa1100_port *sport = (struct sa1100_port *)port;
324
325 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
326 }
327
328 static unsigned int sa1100_get_mctrl(struct uart_port *port)
329 {
330 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
331 }
332
333 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
334 {
335 }
336
337 /*
338 * Interrupts always disabled.
339 */
340 static void sa1100_break_ctl(struct uart_port *port, int break_state)
341 {
342 struct sa1100_port *sport = (struct sa1100_port *)port;
343 unsigned long flags;
344 unsigned int utcr3;
345
346 spin_lock_irqsave(&sport->port.lock, flags);
347 utcr3 = UART_GET_UTCR3(sport);
348 if (break_state == -1)
349 utcr3 |= UTCR3_BRK;
350 else
351 utcr3 &= ~UTCR3_BRK;
352 UART_PUT_UTCR3(sport, utcr3);
353 spin_unlock_irqrestore(&sport->port.lock, flags);
354 }
355
356 static int sa1100_startup(struct uart_port *port)
357 {
358 struct sa1100_port *sport = (struct sa1100_port *)port;
359 int retval;
360
361 /*
362 * Allocate the IRQ
363 */
364 retval = request_irq(sport->port.irq, sa1100_int, 0,
365 "sa11x0-uart", sport);
366 if (retval)
367 return retval;
368
369 /*
370 * Finally, clear and enable interrupts
371 */
372 UART_PUT_UTSR0(sport, -1);
373 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
374
375 /*
376 * Enable modem status interrupts
377 */
378 spin_lock_irq(&sport->port.lock);
379 sa1100_enable_ms(&sport->port);
380 spin_unlock_irq(&sport->port.lock);
381
382 return 0;
383 }
384
385 static void sa1100_shutdown(struct uart_port *port)
386 {
387 struct sa1100_port *sport = (struct sa1100_port *)port;
388
389 /*
390 * Stop our timer.
391 */
392 del_timer_sync(&sport->timer);
393
394 /*
395 * Free the interrupt
396 */
397 free_irq(sport->port.irq, sport);
398
399 /*
400 * Disable all interrupts, port and break condition.
401 */
402 UART_PUT_UTCR3(sport, 0);
403 }
404
405 static void
406 sa1100_set_termios(struct uart_port *port, struct ktermios *termios,
407 struct ktermios *old)
408 {
409 struct sa1100_port *sport = (struct sa1100_port *)port;
410 unsigned long flags;
411 unsigned int utcr0, old_utcr3, baud, quot;
412 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
413
414 /*
415 * We only support CS7 and CS8.
416 */
417 while ((termios->c_cflag & CSIZE) != CS7 &&
418 (termios->c_cflag & CSIZE) != CS8) {
419 termios->c_cflag &= ~CSIZE;
420 termios->c_cflag |= old_csize;
421 old_csize = CS8;
422 }
423
424 if ((termios->c_cflag & CSIZE) == CS8)
425 utcr0 = UTCR0_DSS;
426 else
427 utcr0 = 0;
428
429 if (termios->c_cflag & CSTOPB)
430 utcr0 |= UTCR0_SBS;
431 if (termios->c_cflag & PARENB) {
432 utcr0 |= UTCR0_PE;
433 if (!(termios->c_cflag & PARODD))
434 utcr0 |= UTCR0_OES;
435 }
436
437 /*
438 * Ask the core to calculate the divisor for us.
439 */
440 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
441 quot = uart_get_divisor(port, baud);
442
443 spin_lock_irqsave(&sport->port.lock, flags);
444
445 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
446 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
447 if (termios->c_iflag & INPCK)
448 sport->port.read_status_mask |=
449 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
450 if (termios->c_iflag & (BRKINT | PARMRK))
451 sport->port.read_status_mask |=
452 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
453
454 /*
455 * Characters to ignore
456 */
457 sport->port.ignore_status_mask = 0;
458 if (termios->c_iflag & IGNPAR)
459 sport->port.ignore_status_mask |=
460 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
461 if (termios->c_iflag & IGNBRK) {
462 sport->port.ignore_status_mask |=
463 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
464 /*
465 * If we're ignoring parity and break indicators,
466 * ignore overruns too (for real raw support).
467 */
468 if (termios->c_iflag & IGNPAR)
469 sport->port.ignore_status_mask |=
470 UTSR1_TO_SM(UTSR1_ROR);
471 }
472
473 del_timer_sync(&sport->timer);
474
475 /*
476 * Update the per-port timeout.
477 */
478 uart_update_timeout(port, termios->c_cflag, baud);
479
480 /*
481 * disable interrupts and drain transmitter
482 */
483 old_utcr3 = UART_GET_UTCR3(sport);
484 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
485
486 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
487 barrier();
488
489 /* then, disable everything */
490 UART_PUT_UTCR3(sport, 0);
491
492 /* set the parity, stop bits and data size */
493 UART_PUT_UTCR0(sport, utcr0);
494
495 /* set the baud rate */
496 quot -= 1;
497 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
498 UART_PUT_UTCR2(sport, (quot & 0xff));
499
500 UART_PUT_UTSR0(sport, -1);
501
502 UART_PUT_UTCR3(sport, old_utcr3);
503
504 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
505 sa1100_enable_ms(&sport->port);
506
507 spin_unlock_irqrestore(&sport->port.lock, flags);
508 }
509
510 static const char *sa1100_type(struct uart_port *port)
511 {
512 struct sa1100_port *sport = (struct sa1100_port *)port;
513
514 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
515 }
516
517 /*
518 * Release the memory region(s) being used by 'port'.
519 */
520 static void sa1100_release_port(struct uart_port *port)
521 {
522 struct sa1100_port *sport = (struct sa1100_port *)port;
523
524 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
525 }
526
527 /*
528 * Request the memory region(s) being used by 'port'.
529 */
530 static int sa1100_request_port(struct uart_port *port)
531 {
532 struct sa1100_port *sport = (struct sa1100_port *)port;
533
534 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
535 "sa11x0-uart") != NULL ? 0 : -EBUSY;
536 }
537
538 /*
539 * Configure/autoconfigure the port.
540 */
541 static void sa1100_config_port(struct uart_port *port, int flags)
542 {
543 struct sa1100_port *sport = (struct sa1100_port *)port;
544
545 if (flags & UART_CONFIG_TYPE &&
546 sa1100_request_port(&sport->port) == 0)
547 sport->port.type = PORT_SA1100;
548 }
549
550 /*
551 * Verify the new serial_struct (for TIOCSSERIAL).
552 * The only change we allow are to the flags and type, and
553 * even then only between PORT_SA1100 and PORT_UNKNOWN
554 */
555 static int
556 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
557 {
558 struct sa1100_port *sport = (struct sa1100_port *)port;
559 int ret = 0;
560
561 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
562 ret = -EINVAL;
563 if (sport->port.irq != ser->irq)
564 ret = -EINVAL;
565 if (ser->io_type != SERIAL_IO_MEM)
566 ret = -EINVAL;
567 if (sport->port.uartclk / 16 != ser->baud_base)
568 ret = -EINVAL;
569 if ((void *)sport->port.mapbase != ser->iomem_base)
570 ret = -EINVAL;
571 if (sport->port.iobase != ser->port)
572 ret = -EINVAL;
573 if (ser->hub6 != 0)
574 ret = -EINVAL;
575 return ret;
576 }
577
578 static struct uart_ops sa1100_pops = {
579 .tx_empty = sa1100_tx_empty,
580 .set_mctrl = sa1100_set_mctrl,
581 .get_mctrl = sa1100_get_mctrl,
582 .stop_tx = sa1100_stop_tx,
583 .start_tx = sa1100_start_tx,
584 .stop_rx = sa1100_stop_rx,
585 .enable_ms = sa1100_enable_ms,
586 .break_ctl = sa1100_break_ctl,
587 .startup = sa1100_startup,
588 .shutdown = sa1100_shutdown,
589 .set_termios = sa1100_set_termios,
590 .type = sa1100_type,
591 .release_port = sa1100_release_port,
592 .request_port = sa1100_request_port,
593 .config_port = sa1100_config_port,
594 .verify_port = sa1100_verify_port,
595 };
596
597 static struct sa1100_port sa1100_ports[NR_PORTS];
598
599 /*
600 * Setup the SA1100 serial ports. Note that we don't include the IrDA
601 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
602 *
603 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
604 * Which serial port this ends up being depends on the machine you're
605 * running this kernel on. I'm not convinced that this is a good idea,
606 * but that's the way it traditionally works.
607 *
608 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
609 * used here.
610 */
611 static void __init sa1100_init_ports(void)
612 {
613 static int first = 1;
614 int i;
615
616 if (!first)
617 return;
618 first = 0;
619
620 for (i = 0; i < NR_PORTS; i++) {
621 sa1100_ports[i].port.uartclk = 3686400;
622 sa1100_ports[i].port.ops = &sa1100_pops;
623 sa1100_ports[i].port.fifosize = 8;
624 sa1100_ports[i].port.line = i;
625 sa1100_ports[i].port.iotype = UPIO_MEM;
626 init_timer(&sa1100_ports[i].timer);
627 sa1100_ports[i].timer.function = sa1100_timeout;
628 sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
629 }
630
631 /*
632 * make transmit lines outputs, so that when the port
633 * is closed, the output is in the MARK state.
634 */
635 PPDR |= PPC_TXD1 | PPC_TXD3;
636 PPSR |= PPC_TXD1 | PPC_TXD3;
637 }
638
639 void __devinit sa1100_register_uart_fns(struct sa1100_port_fns *fns)
640 {
641 if (fns->get_mctrl)
642 sa1100_pops.get_mctrl = fns->get_mctrl;
643 if (fns->set_mctrl)
644 sa1100_pops.set_mctrl = fns->set_mctrl;
645
646 sa1100_pops.pm = fns->pm;
647 sa1100_pops.set_wake = fns->set_wake;
648 }
649
650 void __init sa1100_register_uart(int idx, int port)
651 {
652 if (idx >= NR_PORTS) {
653 printk(KERN_ERR "%s: bad index number %d\n", __func__, idx);
654 return;
655 }
656
657 switch (port) {
658 case 1:
659 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
660 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
661 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
662 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
663 break;
664
665 case 2:
666 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
667 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
668 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
669 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
670 break;
671
672 case 3:
673 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
674 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
675 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
676 sa1100_ports[idx].port.flags = UPF_BOOT_AUTOCONF;
677 break;
678
679 default:
680 printk(KERN_ERR "%s: bad port number %d\n", __func__, port);
681 }
682 }
683
684
685 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
686 static void sa1100_console_putchar(struct uart_port *port, int ch)
687 {
688 struct sa1100_port *sport = (struct sa1100_port *)port;
689
690 while (!(UART_GET_UTSR1(sport) & UTSR1_TNF))
691 barrier();
692 UART_PUT_CHAR(sport, ch);
693 }
694
695 /*
696 * Interrupts are disabled on entering
697 */
698 static void
699 sa1100_console_write(struct console *co, const char *s, unsigned int count)
700 {
701 struct sa1100_port *sport = &sa1100_ports[co->index];
702 unsigned int old_utcr3, status;
703
704 /*
705 * First, save UTCR3 and then disable interrupts
706 */
707 old_utcr3 = UART_GET_UTCR3(sport);
708 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
709 UTCR3_TXE);
710
711 uart_console_write(&sport->port, s, count, sa1100_console_putchar);
712
713 /*
714 * Finally, wait for transmitter to become empty
715 * and restore UTCR3
716 */
717 do {
718 status = UART_GET_UTSR1(sport);
719 } while (status & UTSR1_TBY);
720 UART_PUT_UTCR3(sport, old_utcr3);
721 }
722
723 /*
724 * If the port was already initialised (eg, by a boot loader),
725 * try to determine the current setup.
726 */
727 static void __init
728 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
729 int *parity, int *bits)
730 {
731 unsigned int utcr3;
732
733 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
734 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
735 /* ok, the port was enabled */
736 unsigned int utcr0, quot;
737
738 utcr0 = UART_GET_UTCR0(sport);
739
740 *parity = 'n';
741 if (utcr0 & UTCR0_PE) {
742 if (utcr0 & UTCR0_OES)
743 *parity = 'e';
744 else
745 *parity = 'o';
746 }
747
748 if (utcr0 & UTCR0_DSS)
749 *bits = 8;
750 else
751 *bits = 7;
752
753 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
754 quot &= 0xfff;
755 *baud = sport->port.uartclk / (16 * (quot + 1));
756 }
757 }
758
759 static int __init
760 sa1100_console_setup(struct console *co, char *options)
761 {
762 struct sa1100_port *sport;
763 int baud = 9600;
764 int bits = 8;
765 int parity = 'n';
766 int flow = 'n';
767
768 /*
769 * Check whether an invalid uart number has been specified, and
770 * if so, search for the first available port that does have
771 * console support.
772 */
773 if (co->index == -1 || co->index >= NR_PORTS)
774 co->index = 0;
775 sport = &sa1100_ports[co->index];
776
777 if (options)
778 uart_parse_options(options, &baud, &parity, &bits, &flow);
779 else
780 sa1100_console_get_options(sport, &baud, &parity, &bits);
781
782 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
783 }
784
785 static struct uart_driver sa1100_reg;
786 static struct console sa1100_console = {
787 .name = "ttySA",
788 .write = sa1100_console_write,
789 .device = uart_console_device,
790 .setup = sa1100_console_setup,
791 .flags = CON_PRINTBUFFER,
792 .index = -1,
793 .data = &sa1100_reg,
794 };
795
796 static int __init sa1100_rs_console_init(void)
797 {
798 sa1100_init_ports();
799 register_console(&sa1100_console);
800 return 0;
801 }
802 console_initcall(sa1100_rs_console_init);
803
804 #define SA1100_CONSOLE &sa1100_console
805 #else
806 #define SA1100_CONSOLE NULL
807 #endif
808
809 static struct uart_driver sa1100_reg = {
810 .owner = THIS_MODULE,
811 .driver_name = "ttySA",
812 .dev_name = "ttySA",
813 .major = SERIAL_SA1100_MAJOR,
814 .minor = MINOR_START,
815 .nr = NR_PORTS,
816 .cons = SA1100_CONSOLE,
817 };
818
819 static int sa1100_serial_suspend(struct platform_device *dev, pm_message_t state)
820 {
821 struct sa1100_port *sport = platform_get_drvdata(dev);
822
823 if (sport)
824 uart_suspend_port(&sa1100_reg, &sport->port);
825
826 return 0;
827 }
828
829 static int sa1100_serial_resume(struct platform_device *dev)
830 {
831 struct sa1100_port *sport = platform_get_drvdata(dev);
832
833 if (sport)
834 uart_resume_port(&sa1100_reg, &sport->port);
835
836 return 0;
837 }
838
839 static int sa1100_serial_probe(struct platform_device *dev)
840 {
841 struct resource *res = dev->resource;
842 int i;
843
844 for (i = 0; i < dev->num_resources; i++, res++)
845 if (res->flags & IORESOURCE_MEM)
846 break;
847
848 if (i < dev->num_resources) {
849 for (i = 0; i < NR_PORTS; i++) {
850 if (sa1100_ports[i].port.mapbase != res->start)
851 continue;
852
853 sa1100_ports[i].port.dev = &dev->dev;
854 uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
855 platform_set_drvdata(dev, &sa1100_ports[i]);
856 break;
857 }
858 }
859
860 return 0;
861 }
862
863 static int sa1100_serial_remove(struct platform_device *pdev)
864 {
865 struct sa1100_port *sport = platform_get_drvdata(pdev);
866
867 platform_set_drvdata(pdev, NULL);
868
869 if (sport)
870 uart_remove_one_port(&sa1100_reg, &sport->port);
871
872 return 0;
873 }
874
875 static struct platform_driver sa11x0_serial_driver = {
876 .probe = sa1100_serial_probe,
877 .remove = sa1100_serial_remove,
878 .suspend = sa1100_serial_suspend,
879 .resume = sa1100_serial_resume,
880 .driver = {
881 .name = "sa11x0-uart",
882 .owner = THIS_MODULE,
883 },
884 };
885
886 static int __init sa1100_serial_init(void)
887 {
888 int ret;
889
890 printk(KERN_INFO "Serial: SA11x0 driver\n");
891
892 sa1100_init_ports();
893
894 ret = uart_register_driver(&sa1100_reg);
895 if (ret == 0) {
896 ret = platform_driver_register(&sa11x0_serial_driver);
897 if (ret)
898 uart_unregister_driver(&sa1100_reg);
899 }
900 return ret;
901 }
902
903 static void __exit sa1100_serial_exit(void)
904 {
905 platform_driver_unregister(&sa11x0_serial_driver);
906 uart_unregister_driver(&sa1100_reg);
907 }
908
909 module_init(sa1100_serial_init);
910 module_exit(sa1100_serial_exit);
911
912 MODULE_AUTHOR("Deep Blue Solutions Ltd");
913 MODULE_DESCRIPTION("SA1100 generic serial port driver");
914 MODULE_LICENSE("GPL");
915 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
916 MODULE_ALIAS("platform:sa11x0-uart");
Linux with added FPC-III support