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Revert "uart: pl011: Introduce register look up table"
[linux/fpc-iii.git] / drivers / tty / serial / amba-pl011.c
blob29a291d3bf24b20372e03a16d0596e5184b152bd
1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #define SUPPORT_SYSRQ
35 #endif
36
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
60 #include <linux/io.h>
61 #include <linux/acpi.h>
62
63 #define UART_NR 14
64
65 #define SERIAL_AMBA_MAJOR 204
66 #define SERIAL_AMBA_MINOR 64
67 #define SERIAL_AMBA_NR UART_NR
68
69 #define AMBA_ISR_PASS_LIMIT 256
70
71 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
72 #define UART_DUMMY_DR_RX (1 << 16)
73
74 /* There is by now at least one vendor with differing details, so handle it */
75 struct vendor_data {
76 unsigned int ifls;
77 unsigned int lcrh_tx;
78 unsigned int lcrh_rx;
79 bool oversampling;
80 bool dma_threshold;
81 bool cts_event_workaround;
82 bool always_enabled;
83 bool fixed_options;
84
85 unsigned int (*get_fifosize)(struct amba_device *dev);
86 };
87
88 /* Max address offset of register in use is 0x48 */
89 #define REG_NR (0x48 >> 2)
90 #define IDX(x) (x >> 2)
91 enum reg_idx {
92 REG_DR = IDX(UART01x_DR),
93 REG_RSR = IDX(UART01x_RSR),
94 REG_ST_DMAWM = IDX(ST_UART011_DMAWM),
95 REG_FR = IDX(UART01x_FR),
96 REG_ST_LCRH_RX = IDX(ST_UART011_LCRH_RX),
97 REG_ILPR = IDX(UART01x_ILPR),
98 REG_IBRD = IDX(UART011_IBRD),
99 REG_FBRD = IDX(UART011_FBRD),
100 REG_LCRH = IDX(UART011_LCRH),
101 REG_CR = IDX(UART011_CR),
102 REG_IFLS = IDX(UART011_IFLS),
103 REG_IMSC = IDX(UART011_IMSC),
104 REG_RIS = IDX(UART011_RIS),
105 REG_MIS = IDX(UART011_MIS),
106 REG_ICR = IDX(UART011_ICR),
107 REG_DMACR = IDX(UART011_DMACR),
108 };
109
110 static unsigned int get_fifosize_arm(struct amba_device *dev)
111 {
112 return amba_rev(dev) < 3 ? 16 : 32;
113 }
114
115 static struct vendor_data vendor_arm = {
116 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
117 .lcrh_tx = REG_LCRH,
118 .lcrh_rx = REG_LCRH,
119 .oversampling = false,
120 .dma_threshold = false,
121 .cts_event_workaround = false,
122 .always_enabled = false,
123 .fixed_options = false,
124 .get_fifosize = get_fifosize_arm,
125 };
126
127 static struct vendor_data vendor_sbsa = {
128 .oversampling = false,
129 .dma_threshold = false,
130 .cts_event_workaround = false,
131 .always_enabled = true,
132 .fixed_options = true,
133 };
134
135 static unsigned int get_fifosize_st(struct amba_device *dev)
136 {
137 return 64;
138 }
139
140 static struct vendor_data vendor_st = {
141 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
142 .lcrh_tx = REG_LCRH,
143 .lcrh_rx = REG_ST_LCRH_RX,
144 .oversampling = true,
145 .dma_threshold = true,
146 .cts_event_workaround = true,
147 .always_enabled = false,
148 .fixed_options = false,
149 .get_fifosize = get_fifosize_st,
150 };
151
152 /* Deals with DMA transactions */
153
154 struct pl011_sgbuf {
155 struct scatterlist sg;
156 char *buf;
157 };
158
159 struct pl011_dmarx_data {
160 struct dma_chan *chan;
161 struct completion complete;
162 bool use_buf_b;
163 struct pl011_sgbuf sgbuf_a;
164 struct pl011_sgbuf sgbuf_b;
165 dma_cookie_t cookie;
166 bool running;
167 struct timer_list timer;
168 unsigned int last_residue;
169 unsigned long last_jiffies;
170 bool auto_poll_rate;
171 unsigned int poll_rate;
172 unsigned int poll_timeout;
173 };
174
175 struct pl011_dmatx_data {
176 struct dma_chan *chan;
177 struct scatterlist sg;
178 char *buf;
179 bool queued;
180 };
181
182 /*
183 * We wrap our port structure around the generic uart_port.
184 */
185 struct uart_amba_port {
186 struct uart_port port;
187 struct clk *clk;
188 const struct vendor_data *vendor;
189 unsigned int dmacr; /* dma control reg */
190 unsigned int im; /* interrupt mask */
191 unsigned int old_status;
192 unsigned int fifosize; /* vendor-specific */
193 unsigned int lcrh_tx; /* vendor-specific */
194 unsigned int lcrh_rx; /* vendor-specific */
195 unsigned int old_cr; /* state during shutdown */
196 bool autorts;
197 unsigned int fixed_baud; /* vendor-set fixed baud rate */
198 char type[12];
199 #ifdef CONFIG_DMA_ENGINE
200 /* DMA stuff */
201 bool using_tx_dma;
202 bool using_rx_dma;
203 struct pl011_dmarx_data dmarx;
204 struct pl011_dmatx_data dmatx;
205 bool dma_probed;
206 #endif
207 };
208
209 static unsigned int pl011_readw(struct uart_amba_port *uap, int index)
210 {
211 WARN_ON(index > REG_NR);
212 return readw_relaxed(uap->port.membase + (index << 2));
213 }
214
215 static void pl011_writew(struct uart_amba_port *uap, int val, int index)
216 {
217 WARN_ON(index > REG_NR);
218 writew_relaxed(val, uap->port.membase + (index << 2));
219 }
220
221 static void pl011_writeb(struct uart_amba_port *uap, u8 val, int index)
222 {
223 WARN_ON(index > REG_NR);
224 writeb_relaxed(val, uap->port.membase + (index << 2));
225 }
226
227 /*
228 * Reads up to 256 characters from the FIFO or until it's empty and
229 * inserts them into the TTY layer. Returns the number of characters
230 * read from the FIFO.
231 */
232 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
233 {
234 u16 status, ch;
235 unsigned int flag, max_count = 256;
236 int fifotaken = 0;
237
238 while (max_count--) {
239 status = pl011_readw(uap, REG_FR);
240 if (status & UART01x_FR_RXFE)
241 break;
242
243 /* Take chars from the FIFO and update status */
244 ch = pl011_readw(uap, REG_DR) |
245 UART_DUMMY_DR_RX;
246 flag = TTY_NORMAL;
247 uap->port.icount.rx++;
248 fifotaken++;
249
250 if (unlikely(ch & UART_DR_ERROR)) {
251 if (ch & UART011_DR_BE) {
252 ch &= ~(UART011_DR_FE | UART011_DR_PE);
253 uap->port.icount.brk++;
254 if (uart_handle_break(&uap->port))
255 continue;
256 } else if (ch & UART011_DR_PE)
257 uap->port.icount.parity++;
258 else if (ch & UART011_DR_FE)
259 uap->port.icount.frame++;
260 if (ch & UART011_DR_OE)
261 uap->port.icount.overrun++;
262
263 ch &= uap->port.read_status_mask;
264
265 if (ch & UART011_DR_BE)
266 flag = TTY_BREAK;
267 else if (ch & UART011_DR_PE)
268 flag = TTY_PARITY;
269 else if (ch & UART011_DR_FE)
270 flag = TTY_FRAME;
271 }
272
273 if (uart_handle_sysrq_char(&uap->port, ch & 255))
274 continue;
275
276 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
277 }
278
279 return fifotaken;
280 }
281
282
283 /*
284 * All the DMA operation mode stuff goes inside this ifdef.
285 * This assumes that you have a generic DMA device interface,
286 * no custom DMA interfaces are supported.
287 */
288 #ifdef CONFIG_DMA_ENGINE
289
290 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
291
292 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
293 enum dma_data_direction dir)
294 {
295 dma_addr_t dma_addr;
296
297 sg->buf = dma_alloc_coherent(chan->device->dev,
298 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
299 if (!sg->buf)
300 return -ENOMEM;
301
302 sg_init_table(&sg->sg, 1);
303 sg_set_page(&sg->sg, phys_to_page(dma_addr),
304 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
305 sg_dma_address(&sg->sg) = dma_addr;
306 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
307
308 return 0;
309 }
310
311 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
312 enum dma_data_direction dir)
313 {
314 if (sg->buf) {
315 dma_free_coherent(chan->device->dev,
316 PL011_DMA_BUFFER_SIZE, sg->buf,
317 sg_dma_address(&sg->sg));
318 }
319 }
320
321 static void pl011_dma_probe(struct uart_amba_port *uap)
322 {
323 /* DMA is the sole user of the platform data right now */
324 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
325 struct device *dev = uap->port.dev;
326 struct dma_slave_config tx_conf = {
327 .dst_addr = uap->port.mapbase + REG_DR,
328 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
329 .direction = DMA_MEM_TO_DEV,
330 .dst_maxburst = uap->fifosize >> 1,
331 .device_fc = false,
332 };
333 struct dma_chan *chan;
334 dma_cap_mask_t mask;
335
336 uap->dma_probed = true;
337 chan = dma_request_slave_channel_reason(dev, "tx");
338 if (IS_ERR(chan)) {
339 if (PTR_ERR(chan) == -EPROBE_DEFER) {
340 uap->dma_probed = false;
341 return;
342 }
343
344 /* We need platform data */
345 if (!plat || !plat->dma_filter) {
346 dev_info(uap->port.dev, "no DMA platform data\n");
347 return;
348 }
349
350 /* Try to acquire a generic DMA engine slave TX channel */
351 dma_cap_zero(mask);
352 dma_cap_set(DMA_SLAVE, mask);
353
354 chan = dma_request_channel(mask, plat->dma_filter,
355 plat->dma_tx_param);
356 if (!chan) {
357 dev_err(uap->port.dev, "no TX DMA channel!\n");
358 return;
359 }
360 }
361
362 dmaengine_slave_config(chan, &tx_conf);
363 uap->dmatx.chan = chan;
364
365 dev_info(uap->port.dev, "DMA channel TX %s\n",
366 dma_chan_name(uap->dmatx.chan));
367
368 /* Optionally make use of an RX channel as well */
369 chan = dma_request_slave_channel(dev, "rx");
370
371 if (!chan && plat->dma_rx_param) {
372 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
373
374 if (!chan) {
375 dev_err(uap->port.dev, "no RX DMA channel!\n");
376 return;
377 }
378 }
379
380 if (chan) {
381 struct dma_slave_config rx_conf = {
382 .src_addr = uap->port.mapbase + REG_DR,
383 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
384 .direction = DMA_DEV_TO_MEM,
385 .src_maxburst = uap->fifosize >> 2,
386 .device_fc = false,
387 };
388 struct dma_slave_caps caps;
389
390 /*
391 * Some DMA controllers provide information on their capabilities.
392 * If the controller does, check for suitable residue processing
393 * otherwise assime all is well.
394 */
395 if (0 == dma_get_slave_caps(chan, &caps)) {
396 if (caps.residue_granularity ==
397 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
398 dma_release_channel(chan);
399 dev_info(uap->port.dev,
400 "RX DMA disabled - no residue processing\n");
401 return;
402 }
403 }
404 dmaengine_slave_config(chan, &rx_conf);
405 uap->dmarx.chan = chan;
406
407 uap->dmarx.auto_poll_rate = false;
408 if (plat && plat->dma_rx_poll_enable) {
409 /* Set poll rate if specified. */
410 if (plat->dma_rx_poll_rate) {
411 uap->dmarx.auto_poll_rate = false;
412 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
413 } else {
414 /*
415 * 100 ms defaults to poll rate if not
416 * specified. This will be adjusted with
417 * the baud rate at set_termios.
418 */
419 uap->dmarx.auto_poll_rate = true;
420 uap->dmarx.poll_rate = 100;
421 }
422 /* 3 secs defaults poll_timeout if not specified. */
423 if (plat->dma_rx_poll_timeout)
424 uap->dmarx.poll_timeout =
425 plat->dma_rx_poll_timeout;
426 else
427 uap->dmarx.poll_timeout = 3000;
428 } else if (!plat && dev->of_node) {
429 uap->dmarx.auto_poll_rate = of_property_read_bool(
430 dev->of_node, "auto-poll");
431 if (uap->dmarx.auto_poll_rate) {
432 u32 x;
433
434 if (0 == of_property_read_u32(dev->of_node,
435 "poll-rate-ms", &x))
436 uap->dmarx.poll_rate = x;
437 else
438 uap->dmarx.poll_rate = 100;
439 if (0 == of_property_read_u32(dev->of_node,
440 "poll-timeout-ms", &x))
441 uap->dmarx.poll_timeout = x;
442 else
443 uap->dmarx.poll_timeout = 3000;
444 }
445 }
446 dev_info(uap->port.dev, "DMA channel RX %s\n",
447 dma_chan_name(uap->dmarx.chan));
448 }
449 }
450
451 static void pl011_dma_remove(struct uart_amba_port *uap)
452 {
453 if (uap->dmatx.chan)
454 dma_release_channel(uap->dmatx.chan);
455 if (uap->dmarx.chan)
456 dma_release_channel(uap->dmarx.chan);
457 }
458
459 /* Forward declare these for the refill routine */
460 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
461 static void pl011_start_tx_pio(struct uart_amba_port *uap);
462
463 /*
464 * The current DMA TX buffer has been sent.
465 * Try to queue up another DMA buffer.
466 */
467 static void pl011_dma_tx_callback(void *data)
468 {
469 struct uart_amba_port *uap = data;
470 struct pl011_dmatx_data *dmatx = &uap->dmatx;
471 unsigned long flags;
472 u16 dmacr;
473
474 spin_lock_irqsave(&uap->port.lock, flags);
475 if (uap->dmatx.queued)
476 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
477 DMA_TO_DEVICE);
478
479 dmacr = uap->dmacr;
480 uap->dmacr = dmacr & ~UART011_TXDMAE;
481 pl011_writew(uap, uap->dmacr, REG_DMACR);
482
483 /*
484 * If TX DMA was disabled, it means that we've stopped the DMA for
485 * some reason (eg, XOFF received, or we want to send an X-char.)
486 *
487 * Note: we need to be careful here of a potential race between DMA
488 * and the rest of the driver - if the driver disables TX DMA while
489 * a TX buffer completing, we must update the tx queued status to
490 * get further refills (hence we check dmacr).
491 */
492 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
493 uart_circ_empty(&uap->port.state->xmit)) {
494 uap->dmatx.queued = false;
495 spin_unlock_irqrestore(&uap->port.lock, flags);
496 return;
497 }
498
499 if (pl011_dma_tx_refill(uap) <= 0)
500 /*
501 * We didn't queue a DMA buffer for some reason, but we
502 * have data pending to be sent. Re-enable the TX IRQ.
503 */
504 pl011_start_tx_pio(uap);
505
506 spin_unlock_irqrestore(&uap->port.lock, flags);
507 }
508
509 /*
510 * Try to refill the TX DMA buffer.
511 * Locking: called with port lock held and IRQs disabled.
512 * Returns:
513 * 1 if we queued up a TX DMA buffer.
514 * 0 if we didn't want to handle this by DMA
515 * <0 on error
516 */
517 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
518 {
519 struct pl011_dmatx_data *dmatx = &uap->dmatx;
520 struct dma_chan *chan = dmatx->chan;
521 struct dma_device *dma_dev = chan->device;
522 struct dma_async_tx_descriptor *desc;
523 struct circ_buf *xmit = &uap->port.state->xmit;
524 unsigned int count;
525
526 /*
527 * Try to avoid the overhead involved in using DMA if the
528 * transaction fits in the first half of the FIFO, by using
529 * the standard interrupt handling. This ensures that we
530 * issue a uart_write_wakeup() at the appropriate time.
531 */
532 count = uart_circ_chars_pending(xmit);
533 if (count < (uap->fifosize >> 1)) {
534 uap->dmatx.queued = false;
535 return 0;
536 }
537
538 /*
539 * Bodge: don't send the last character by DMA, as this
540 * will prevent XON from notifying us to restart DMA.
541 */
542 count -= 1;
543
544 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
545 if (count > PL011_DMA_BUFFER_SIZE)
546 count = PL011_DMA_BUFFER_SIZE;
547
548 if (xmit->tail < xmit->head)
549 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
550 else {
551 size_t first = UART_XMIT_SIZE - xmit->tail;
552 size_t second;
553
554 if (first > count)
555 first = count;
556 second = count - first;
557
558 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
559 if (second)
560 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
561 }
562
563 dmatx->sg.length = count;
564
565 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
566 uap->dmatx.queued = false;
567 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
568 return -EBUSY;
569 }
570
571 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
572 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
573 if (!desc) {
574 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
575 uap->dmatx.queued = false;
576 /*
577 * If DMA cannot be used right now, we complete this
578 * transaction via IRQ and let the TTY layer retry.
579 */
580 dev_dbg(uap->port.dev, "TX DMA busy\n");
581 return -EBUSY;
582 }
583
584 /* Some data to go along to the callback */
585 desc->callback = pl011_dma_tx_callback;
586 desc->callback_param = uap;
587
588 /* All errors should happen at prepare time */
589 dmaengine_submit(desc);
590
591 /* Fire the DMA transaction */
592 dma_dev->device_issue_pending(chan);
593
594 uap->dmacr |= UART011_TXDMAE;
595 pl011_writew(uap, uap->dmacr, REG_DMACR);
596 uap->dmatx.queued = true;
597
598 /*
599 * Now we know that DMA will fire, so advance the ring buffer
600 * with the stuff we just dispatched.
601 */
602 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
603 uap->port.icount.tx += count;
604
605 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
606 uart_write_wakeup(&uap->port);
607
608 return 1;
609 }
610
611 /*
612 * We received a transmit interrupt without a pending X-char but with
613 * pending characters.
614 * Locking: called with port lock held and IRQs disabled.
615 * Returns:
616 * false if we want to use PIO to transmit
617 * true if we queued a DMA buffer
618 */
619 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
620 {
621 if (!uap->using_tx_dma)
622 return false;
623
624 /*
625 * If we already have a TX buffer queued, but received a
626 * TX interrupt, it will be because we've just sent an X-char.
627 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
628 */
629 if (uap->dmatx.queued) {
630 uap->dmacr |= UART011_TXDMAE;
631 pl011_writew(uap, uap->dmacr, REG_DMACR);
632 uap->im &= ~UART011_TXIM;
633 pl011_writew(uap, uap->im, REG_IMSC);
634 return true;
635 }
636
637 /*
638 * We don't have a TX buffer queued, so try to queue one.
639 * If we successfully queued a buffer, mask the TX IRQ.
640 */
641 if (pl011_dma_tx_refill(uap) > 0) {
642 uap->im &= ~UART011_TXIM;
643 pl011_writew(uap, uap->im, REG_IMSC);
644 return true;
645 }
646 return false;
647 }
648
649 /*
650 * Stop the DMA transmit (eg, due to received XOFF).
651 * Locking: called with port lock held and IRQs disabled.
652 */
653 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
654 {
655 if (uap->dmatx.queued) {
656 uap->dmacr &= ~UART011_TXDMAE;
657 pl011_writew(uap, uap->dmacr, REG_DMACR);
658 }
659 }
660
661 /*
662 * Try to start a DMA transmit, or in the case of an XON/OFF
663 * character queued for send, try to get that character out ASAP.
664 * Locking: called with port lock held and IRQs disabled.
665 * Returns:
666 * false if we want the TX IRQ to be enabled
667 * true if we have a buffer queued
668 */
669 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
670 {
671 u16 dmacr;
672
673 if (!uap->using_tx_dma)
674 return false;
675
676 if (!uap->port.x_char) {
677 /* no X-char, try to push chars out in DMA mode */
678 bool ret = true;
679
680 if (!uap->dmatx.queued) {
681 if (pl011_dma_tx_refill(uap) > 0) {
682 uap->im &= ~UART011_TXIM;
683 pl011_writew(uap, uap->im, REG_IMSC);
684 } else
685 ret = false;
686 } else if (!(uap->dmacr & UART011_TXDMAE)) {
687 uap->dmacr |= UART011_TXDMAE;
688 pl011_writew(uap, uap->dmacr, REG_DMACR);
689 }
690 return ret;
691 }
692
693 /*
694 * We have an X-char to send. Disable DMA to prevent it loading
695 * the TX fifo, and then see if we can stuff it into the FIFO.
696 */
697 dmacr = uap->dmacr;
698 uap->dmacr &= ~UART011_TXDMAE;
699 pl011_writew(uap, uap->dmacr, REG_DMACR);
700
701 if (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF) {
702 /*
703 * No space in the FIFO, so enable the transmit interrupt
704 * so we know when there is space. Note that once we've
705 * loaded the character, we should just re-enable DMA.
706 */
707 return false;
708 }
709
710 pl011_writew(uap, uap->port.x_char, REG_DR);
711 uap->port.icount.tx++;
712 uap->port.x_char = 0;
713
714 /* Success - restore the DMA state */
715 uap->dmacr = dmacr;
716 pl011_writew(uap, dmacr, REG_DMACR);
717
718 return true;
719 }
720
721 /*
722 * Flush the transmit buffer.
723 * Locking: called with port lock held and IRQs disabled.
724 */
725 static void pl011_dma_flush_buffer(struct uart_port *port)
726 __releases(&uap->port.lock)
727 __acquires(&uap->port.lock)
728 {
729 struct uart_amba_port *uap =
730 container_of(port, struct uart_amba_port, port);
731
732 if (!uap->using_tx_dma)
733 return;
734
735 /* Avoid deadlock with the DMA engine callback */
736 spin_unlock(&uap->port.lock);
737 dmaengine_terminate_all(uap->dmatx.chan);
738 spin_lock(&uap->port.lock);
739 if (uap->dmatx.queued) {
740 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
741 DMA_TO_DEVICE);
742 uap->dmatx.queued = false;
743 uap->dmacr &= ~UART011_TXDMAE;
744 pl011_writew(uap, uap->dmacr, REG_DMACR);
745 }
746 }
747
748 static void pl011_dma_rx_callback(void *data);
749
750 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
751 {
752 struct dma_chan *rxchan = uap->dmarx.chan;
753 struct pl011_dmarx_data *dmarx = &uap->dmarx;
754 struct dma_async_tx_descriptor *desc;
755 struct pl011_sgbuf *sgbuf;
756
757 if (!rxchan)
758 return -EIO;
759
760 /* Start the RX DMA job */
761 sgbuf = uap->dmarx.use_buf_b ?
762 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
763 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
764 DMA_DEV_TO_MEM,
765 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
766 /*
767 * If the DMA engine is busy and cannot prepare a
768 * channel, no big deal, the driver will fall back
769 * to interrupt mode as a result of this error code.
770 */
771 if (!desc) {
772 uap->dmarx.running = false;
773 dmaengine_terminate_all(rxchan);
774 return -EBUSY;
775 }
776
777 /* Some data to go along to the callback */
778 desc->callback = pl011_dma_rx_callback;
779 desc->callback_param = uap;
780 dmarx->cookie = dmaengine_submit(desc);
781 dma_async_issue_pending(rxchan);
782
783 uap->dmacr |= UART011_RXDMAE;
784 pl011_writew(uap, uap->dmacr, REG_DMACR);
785 uap->dmarx.running = true;
786
787 uap->im &= ~UART011_RXIM;
788 pl011_writew(uap, uap->im, REG_IMSC);
789
790 return 0;
791 }
792
793 /*
794 * This is called when either the DMA job is complete, or
795 * the FIFO timeout interrupt occurred. This must be called
796 * with the port spinlock uap->port.lock held.
797 */
798 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
799 u32 pending, bool use_buf_b,
800 bool readfifo)
801 {
802 struct tty_port *port = &uap->port.state->port;
803 struct pl011_sgbuf *sgbuf = use_buf_b ?
804 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
805 int dma_count = 0;
806 u32 fifotaken = 0; /* only used for vdbg() */
807
808 struct pl011_dmarx_data *dmarx = &uap->dmarx;
809 int dmataken = 0;
810
811 if (uap->dmarx.poll_rate) {
812 /* The data can be taken by polling */
813 dmataken = sgbuf->sg.length - dmarx->last_residue;
814 /* Recalculate the pending size */
815 if (pending >= dmataken)
816 pending -= dmataken;
817 }
818
819 /* Pick the remain data from the DMA */
820 if (pending) {
821
822 /*
823 * First take all chars in the DMA pipe, then look in the FIFO.
824 * Note that tty_insert_flip_buf() tries to take as many chars
825 * as it can.
826 */
827 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
828 pending);
829
830 uap->port.icount.rx += dma_count;
831 if (dma_count < pending)
832 dev_warn(uap->port.dev,
833 "couldn't insert all characters (TTY is full?)\n");
834 }
835
836 /* Reset the last_residue for Rx DMA poll */
837 if (uap->dmarx.poll_rate)
838 dmarx->last_residue = sgbuf->sg.length;
839
840 /*
841 * Only continue with trying to read the FIFO if all DMA chars have
842 * been taken first.
843 */
844 if (dma_count == pending && readfifo) {
845 /* Clear any error flags */
846 pl011_writew(uap,
847 UART011_OEIS | UART011_BEIS | UART011_PEIS
848 | UART011_FEIS, REG_ICR);
849
850 /*
851 * If we read all the DMA'd characters, and we had an
852 * incomplete buffer, that could be due to an rx error, or
853 * maybe we just timed out. Read any pending chars and check
854 * the error status.
855 *
856 * Error conditions will only occur in the FIFO, these will
857 * trigger an immediate interrupt and stop the DMA job, so we
858 * will always find the error in the FIFO, never in the DMA
859 * buffer.
860 */
861 fifotaken = pl011_fifo_to_tty(uap);
862 }
863
864 spin_unlock(&uap->port.lock);
865 dev_vdbg(uap->port.dev,
866 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
867 dma_count, fifotaken);
868 tty_flip_buffer_push(port);
869 spin_lock(&uap->port.lock);
870 }
871
872 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
873 {
874 struct pl011_dmarx_data *dmarx = &uap->dmarx;
875 struct dma_chan *rxchan = dmarx->chan;
876 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
877 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
878 size_t pending;
879 struct dma_tx_state state;
880 enum dma_status dmastat;
881
882 /*
883 * Pause the transfer so we can trust the current counter,
884 * do this before we pause the PL011 block, else we may
885 * overflow the FIFO.
886 */
887 if (dmaengine_pause(rxchan))
888 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
889 dmastat = rxchan->device->device_tx_status(rxchan,
890 dmarx->cookie, &state);
891 if (dmastat != DMA_PAUSED)
892 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
893
894 /* Disable RX DMA - incoming data will wait in the FIFO */
895 uap->dmacr &= ~UART011_RXDMAE;
896 pl011_writew(uap, uap->dmacr, REG_DMACR);
897 uap->dmarx.running = false;
898
899 pending = sgbuf->sg.length - state.residue;
900 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
901 /* Then we terminate the transfer - we now know our residue */
902 dmaengine_terminate_all(rxchan);
903
904 /*
905 * This will take the chars we have so far and insert
906 * into the framework.
907 */
908 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
909
910 /* Switch buffer & re-trigger DMA job */
911 dmarx->use_buf_b = !dmarx->use_buf_b;
912 if (pl011_dma_rx_trigger_dma(uap)) {
913 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
914 "fall back to interrupt mode\n");
915 uap->im |= UART011_RXIM;
916 pl011_writew(uap, uap->im, REG_IMSC);
917 }
918 }
919
920 static void pl011_dma_rx_callback(void *data)
921 {
922 struct uart_amba_port *uap = data;
923 struct pl011_dmarx_data *dmarx = &uap->dmarx;
924 struct dma_chan *rxchan = dmarx->chan;
925 bool lastbuf = dmarx->use_buf_b;
926 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
927 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
928 size_t pending;
929 struct dma_tx_state state;
930 int ret;
931
932 /*
933 * This completion interrupt occurs typically when the
934 * RX buffer is totally stuffed but no timeout has yet
935 * occurred. When that happens, we just want the RX
936 * routine to flush out the secondary DMA buffer while
937 * we immediately trigger the next DMA job.
938 */
939 spin_lock_irq(&uap->port.lock);
940 /*
941 * Rx data can be taken by the UART interrupts during
942 * the DMA irq handler. So we check the residue here.
943 */
944 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
945 pending = sgbuf->sg.length - state.residue;
946 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
947 /* Then we terminate the transfer - we now know our residue */
948 dmaengine_terminate_all(rxchan);
949
950 uap->dmarx.running = false;
951 dmarx->use_buf_b = !lastbuf;
952 ret = pl011_dma_rx_trigger_dma(uap);
953
954 pl011_dma_rx_chars(uap, pending, lastbuf, false);
955 spin_unlock_irq(&uap->port.lock);
956 /*
957 * Do this check after we picked the DMA chars so we don't
958 * get some IRQ immediately from RX.
959 */
960 if (ret) {
961 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
962 "fall back to interrupt mode\n");
963 uap->im |= UART011_RXIM;
964 pl011_writew(uap, uap->im, REG_IMSC);
965 }
966 }
967
968 /*
969 * Stop accepting received characters, when we're shutting down or
970 * suspending this port.
971 * Locking: called with port lock held and IRQs disabled.
972 */
973 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
974 {
975 /* FIXME. Just disable the DMA enable */
976 uap->dmacr &= ~UART011_RXDMAE;
977 pl011_writew(uap, uap->dmacr, REG_DMACR);
978 }
979
980 /*
981 * Timer handler for Rx DMA polling.
982 * Every polling, It checks the residue in the dma buffer and transfer
983 * data to the tty. Also, last_residue is updated for the next polling.
984 */
985 static void pl011_dma_rx_poll(unsigned long args)
986 {
987 struct uart_amba_port *uap = (struct uart_amba_port *)args;
988 struct tty_port *port = &uap->port.state->port;
989 struct pl011_dmarx_data *dmarx = &uap->dmarx;
990 struct dma_chan *rxchan = uap->dmarx.chan;
991 unsigned long flags = 0;
992 unsigned int dmataken = 0;
993 unsigned int size = 0;
994 struct pl011_sgbuf *sgbuf;
995 int dma_count;
996 struct dma_tx_state state;
997
998 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
999 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1000 if (likely(state.residue < dmarx->last_residue)) {
1001 dmataken = sgbuf->sg.length - dmarx->last_residue;
1002 size = dmarx->last_residue - state.residue;
1003 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1004 size);
1005 if (dma_count == size)
1006 dmarx->last_residue = state.residue;
1007 dmarx->last_jiffies = jiffies;
1008 }
1009 tty_flip_buffer_push(port);
1010
1011 /*
1012 * If no data is received in poll_timeout, the driver will fall back
1013 * to interrupt mode. We will retrigger DMA at the first interrupt.
1014 */
1015 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1016 > uap->dmarx.poll_timeout) {
1017
1018 spin_lock_irqsave(&uap->port.lock, flags);
1019 pl011_dma_rx_stop(uap);
1020 uap->im |= UART011_RXIM;
1021 pl011_writew(uap, uap->im, REG_IMSC);
1022 spin_unlock_irqrestore(&uap->port.lock, flags);
1023
1024 uap->dmarx.running = false;
1025 dmaengine_terminate_all(rxchan);
1026 del_timer(&uap->dmarx.timer);
1027 } else {
1028 mod_timer(&uap->dmarx.timer,
1029 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1030 }
1031 }
1032
1033 static void pl011_dma_startup(struct uart_amba_port *uap)
1034 {
1035 int ret;
1036
1037 if (!uap->dma_probed)
1038 pl011_dma_probe(uap);
1039
1040 if (!uap->dmatx.chan)
1041 return;
1042
1043 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1044 if (!uap->dmatx.buf) {
1045 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1046 uap->port.fifosize = uap->fifosize;
1047 return;
1048 }
1049
1050 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1051
1052 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1053 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1054 uap->using_tx_dma = true;
1055
1056 if (!uap->dmarx.chan)
1057 goto skip_rx;
1058
1059 /* Allocate and map DMA RX buffers */
1060 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1061 DMA_FROM_DEVICE);
1062 if (ret) {
1063 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1064 "RX buffer A", ret);
1065 goto skip_rx;
1066 }
1067
1068 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1069 DMA_FROM_DEVICE);
1070 if (ret) {
1071 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1072 "RX buffer B", ret);
1073 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1074 DMA_FROM_DEVICE);
1075 goto skip_rx;
1076 }
1077
1078 uap->using_rx_dma = true;
1079
1080 skip_rx:
1081 /* Turn on DMA error (RX/TX will be enabled on demand) */
1082 uap->dmacr |= UART011_DMAONERR;
1083 pl011_writew(uap, uap->dmacr, REG_DMACR);
1084
1085 /*
1086 * ST Micro variants has some specific dma burst threshold
1087 * compensation. Set this to 16 bytes, so burst will only
1088 * be issued above/below 16 bytes.
1089 */
1090 if (uap->vendor->dma_threshold)
1091 pl011_writew(uap,
1092 ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1093 REG_ST_DMAWM);
1094
1095 if (uap->using_rx_dma) {
1096 if (pl011_dma_rx_trigger_dma(uap))
1097 dev_dbg(uap->port.dev, "could not trigger initial "
1098 "RX DMA job, fall back to interrupt mode\n");
1099 if (uap->dmarx.poll_rate) {
1100 init_timer(&(uap->dmarx.timer));
1101 uap->dmarx.timer.function = pl011_dma_rx_poll;
1102 uap->dmarx.timer.data = (unsigned long)uap;
1103 mod_timer(&uap->dmarx.timer,
1104 jiffies +
1105 msecs_to_jiffies(uap->dmarx.poll_rate));
1106 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1107 uap->dmarx.last_jiffies = jiffies;
1108 }
1109 }
1110 }
1111
1112 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1113 {
1114 if (!(uap->using_tx_dma || uap->using_rx_dma))
1115 return;
1116
1117 /* Disable RX and TX DMA */
1118 while (pl011_readw(uap, REG_FR) & UART01x_FR_BUSY)
1119 barrier();
1120
1121 spin_lock_irq(&uap->port.lock);
1122 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1123 pl011_writew(uap, uap->dmacr, REG_DMACR);
1124 spin_unlock_irq(&uap->port.lock);
1125
1126 if (uap->using_tx_dma) {
1127 /* In theory, this should already be done by pl011_dma_flush_buffer */
1128 dmaengine_terminate_all(uap->dmatx.chan);
1129 if (uap->dmatx.queued) {
1130 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1131 DMA_TO_DEVICE);
1132 uap->dmatx.queued = false;
1133 }
1134
1135 kfree(uap->dmatx.buf);
1136 uap->using_tx_dma = false;
1137 }
1138
1139 if (uap->using_rx_dma) {
1140 dmaengine_terminate_all(uap->dmarx.chan);
1141 /* Clean up the RX DMA */
1142 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1143 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1144 if (uap->dmarx.poll_rate)
1145 del_timer_sync(&uap->dmarx.timer);
1146 uap->using_rx_dma = false;
1147 }
1148 }
1149
1150 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1151 {
1152 return uap->using_rx_dma;
1153 }
1154
1155 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1156 {
1157 return uap->using_rx_dma && uap->dmarx.running;
1158 }
1159
1160 #else
1161 /* Blank functions if the DMA engine is not available */
1162 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1163 {
1164 }
1165
1166 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1167 {
1168 }
1169
1170 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1171 {
1172 }
1173
1174 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1175 {
1176 }
1177
1178 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1179 {
1180 return false;
1181 }
1182
1183 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1184 {
1185 }
1186
1187 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1188 {
1189 return false;
1190 }
1191
1192 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1193 {
1194 }
1195
1196 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1197 {
1198 }
1199
1200 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1201 {
1202 return -EIO;
1203 }
1204
1205 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1206 {
1207 return false;
1208 }
1209
1210 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1211 {
1212 return false;
1213 }
1214
1215 #define pl011_dma_flush_buffer NULL
1216 #endif
1217
1218 static void pl011_stop_tx(struct uart_port *port)
1219 {
1220 struct uart_amba_port *uap =
1221 container_of(port, struct uart_amba_port, port);
1222
1223 uap->im &= ~UART011_TXIM;
1224 pl011_writew(uap, uap->im, REG_IMSC);
1225 pl011_dma_tx_stop(uap);
1226 }
1227
1228 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1229
1230 /* Start TX with programmed I/O only (no DMA) */
1231 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1232 {
1233 uap->im |= UART011_TXIM;
1234 pl011_writew(uap, uap->im, REG_IMSC);
1235 pl011_tx_chars(uap, false);
1236 }
1237
1238 static void pl011_start_tx(struct uart_port *port)
1239 {
1240 struct uart_amba_port *uap =
1241 container_of(port, struct uart_amba_port, port);
1242
1243 if (!pl011_dma_tx_start(uap))
1244 pl011_start_tx_pio(uap);
1245 }
1246
1247 static void pl011_stop_rx(struct uart_port *port)
1248 {
1249 struct uart_amba_port *uap =
1250 container_of(port, struct uart_amba_port, port);
1251
1252 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1253 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1254 pl011_writew(uap, uap->im, REG_IMSC);
1255
1256 pl011_dma_rx_stop(uap);
1257 }
1258
1259 static void pl011_enable_ms(struct uart_port *port)
1260 {
1261 struct uart_amba_port *uap =
1262 container_of(port, struct uart_amba_port, port);
1263
1264 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1265 pl011_writew(uap, uap->im, REG_IMSC);
1266 }
1267
1268 static void pl011_rx_chars(struct uart_amba_port *uap)
1269 __releases(&uap->port.lock)
1270 __acquires(&uap->port.lock)
1271 {
1272 pl011_fifo_to_tty(uap);
1273
1274 spin_unlock(&uap->port.lock);
1275 tty_flip_buffer_push(&uap->port.state->port);
1276 /*
1277 * If we were temporarily out of DMA mode for a while,
1278 * attempt to switch back to DMA mode again.
1279 */
1280 if (pl011_dma_rx_available(uap)) {
1281 if (pl011_dma_rx_trigger_dma(uap)) {
1282 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1283 "fall back to interrupt mode again\n");
1284 uap->im |= UART011_RXIM;
1285 pl011_writew(uap, uap->im, REG_IMSC);
1286 } else {
1287 #ifdef CONFIG_DMA_ENGINE
1288 /* Start Rx DMA poll */
1289 if (uap->dmarx.poll_rate) {
1290 uap->dmarx.last_jiffies = jiffies;
1291 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1292 mod_timer(&uap->dmarx.timer,
1293 jiffies +
1294 msecs_to_jiffies(uap->dmarx.poll_rate));
1295 }
1296 #endif
1297 }
1298 }
1299 spin_lock(&uap->port.lock);
1300 }
1301
1302 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1303 bool from_irq)
1304 {
1305 if (unlikely(!from_irq) &&
1306 pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
1307 return false; /* unable to transmit character */
1308
1309 pl011_writew(uap, c, REG_DR);
1310 uap->port.icount.tx++;
1311
1312 return true;
1313 }
1314
1315 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1316 {
1317 struct circ_buf *xmit = &uap->port.state->xmit;
1318 int count = uap->fifosize >> 1;
1319
1320 if (uap->port.x_char) {
1321 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1322 return;
1323 uap->port.x_char = 0;
1324 --count;
1325 }
1326 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1327 pl011_stop_tx(&uap->port);
1328 return;
1329 }
1330
1331 /* If we are using DMA mode, try to send some characters. */
1332 if (pl011_dma_tx_irq(uap))
1333 return;
1334
1335 do {
1336 if (likely(from_irq) && count-- == 0)
1337 break;
1338
1339 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1340 break;
1341
1342 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1343 } while (!uart_circ_empty(xmit));
1344
1345 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1346 uart_write_wakeup(&uap->port);
1347
1348 if (uart_circ_empty(xmit))
1349 pl011_stop_tx(&uap->port);
1350 }
1351
1352 static void pl011_modem_status(struct uart_amba_port *uap)
1353 {
1354 unsigned int status, delta;
1355
1356 status = pl011_readw(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1357
1358 delta = status ^ uap->old_status;
1359 uap->old_status = status;
1360
1361 if (!delta)
1362 return;
1363
1364 if (delta & UART01x_FR_DCD)
1365 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1366
1367 if (delta & UART01x_FR_DSR)
1368 uap->port.icount.dsr++;
1369
1370 if (delta & UART01x_FR_CTS)
1371 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1372
1373 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1374 }
1375
1376 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1377 {
1378 unsigned int dummy_read;
1379
1380 if (!uap->vendor->cts_event_workaround)
1381 return;
1382
1383 /* workaround to make sure that all bits are unlocked.. */
1384 pl011_writew(uap, 0x00, REG_ICR);
1385
1386 /*
1387 * WA: introduce 26ns(1 uart clk) delay before W1C;
1388 * single apb access will incur 2 pclk(133.12Mhz) delay,
1389 * so add 2 dummy reads
1390 */
1391 dummy_read = pl011_readw(uap, REG_ICR);
1392 dummy_read = pl011_readw(uap, REG_ICR);
1393 }
1394
1395 static irqreturn_t pl011_int(int irq, void *dev_id)
1396 {
1397 struct uart_amba_port *uap = dev_id;
1398 unsigned long flags;
1399 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1400 u16 imsc;
1401 int handled = 0;
1402
1403 spin_lock_irqsave(&uap->port.lock, flags);
1404 imsc = pl011_readw(uap, REG_IMSC);
1405 status = pl011_readw(uap, REG_RIS) & imsc;
1406 if (status) {
1407 do {
1408 check_apply_cts_event_workaround(uap);
1409 pl011_writew(uap, status & ~(UART011_TXIS|UART011_RTIS|
1410 UART011_RXIS), REG_ICR);
1411
1412 if (status & (UART011_RTIS|UART011_RXIS)) {
1413 if (pl011_dma_rx_running(uap))
1414 pl011_dma_rx_irq(uap);
1415 else
1416 pl011_rx_chars(uap);
1417 }
1418 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1419 UART011_CTSMIS|UART011_RIMIS))
1420 pl011_modem_status(uap);
1421 if (status & UART011_TXIS)
1422 pl011_tx_chars(uap, true);
1423
1424 if (pass_counter-- == 0)
1425 break;
1426
1427 status = pl011_readw(uap, REG_RIS) & imsc;
1428 } while (status != 0);
1429 handled = 1;
1430 }
1431
1432 spin_unlock_irqrestore(&uap->port.lock, flags);
1433
1434 return IRQ_RETVAL(handled);
1435 }
1436
1437 static unsigned int pl011_tx_empty(struct uart_port *port)
1438 {
1439 struct uart_amba_port *uap =
1440 container_of(port, struct uart_amba_port, port);
1441 unsigned int status = pl011_readw(uap, REG_FR);
1442 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1443 }
1444
1445 static unsigned int pl011_get_mctrl(struct uart_port *port)
1446 {
1447 struct uart_amba_port *uap =
1448 container_of(port, struct uart_amba_port, port);
1449 unsigned int result = 0;
1450 unsigned int status = pl011_readw(uap, REG_FR);
1451
1452 #define TIOCMBIT(uartbit, tiocmbit) \
1453 if (status & uartbit) \
1454 result |= tiocmbit
1455
1456 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1457 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1458 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1459 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1460 #undef TIOCMBIT
1461 return result;
1462 }
1463
1464 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1465 {
1466 struct uart_amba_port *uap =
1467 container_of(port, struct uart_amba_port, port);
1468 unsigned int cr;
1469
1470 cr = pl011_readw(uap, REG_CR);
1471
1472 #define TIOCMBIT(tiocmbit, uartbit) \
1473 if (mctrl & tiocmbit) \
1474 cr |= uartbit; \
1475 else \
1476 cr &= ~uartbit
1477
1478 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1479 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1480 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1481 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1482 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1483
1484 if (uap->autorts) {
1485 /* We need to disable auto-RTS if we want to turn RTS off */
1486 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1487 }
1488 #undef TIOCMBIT
1489
1490 pl011_writew(uap, cr, REG_CR);
1491 }
1492
1493 static void pl011_break_ctl(struct uart_port *port, int break_state)
1494 {
1495 struct uart_amba_port *uap =
1496 container_of(port, struct uart_amba_port, port);
1497 unsigned long flags;
1498 unsigned int lcr_h;
1499
1500 spin_lock_irqsave(&uap->port.lock, flags);
1501 lcr_h = pl011_readw(uap, uap->lcrh_tx);
1502 if (break_state == -1)
1503 lcr_h |= UART01x_LCRH_BRK;
1504 else
1505 lcr_h &= ~UART01x_LCRH_BRK;
1506 pl011_writew(uap, lcr_h, uap->lcrh_tx);
1507 spin_unlock_irqrestore(&uap->port.lock, flags);
1508 }
1509
1510 #ifdef CONFIG_CONSOLE_POLL
1511
1512 static void pl011_quiesce_irqs(struct uart_port *port)
1513 {
1514 struct uart_amba_port *uap =
1515 container_of(port, struct uart_amba_port, port);
1516
1517 pl011_writew(uap, pl011_readw(uap, REG_MIS), REG_ICR);
1518 /*
1519 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1520 * we simply mask it. start_tx() will unmask it.
1521 *
1522 * Note we can race with start_tx(), and if the race happens, the
1523 * polling user might get another interrupt just after we clear it.
1524 * But it should be OK and can happen even w/o the race, e.g.
1525 * controller immediately got some new data and raised the IRQ.
1526 *
1527 * And whoever uses polling routines assumes that it manages the device
1528 * (including tx queue), so we're also fine with start_tx()'s caller
1529 * side.
1530 */
1531 pl011_writew(uap, pl011_readw(uap, REG_IMSC) & ~UART011_TXIM, REG_IMSC);
1532 }
1533
1534 static int pl011_get_poll_char(struct uart_port *port)
1535 {
1536 struct uart_amba_port *uap =
1537 container_of(port, struct uart_amba_port, port);
1538 unsigned int status;
1539
1540 /*
1541 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1542 * debugger.
1543 */
1544 pl011_quiesce_irqs(port);
1545
1546 status = pl011_readw(uap, REG_FR);
1547 if (status & UART01x_FR_RXFE)
1548 return NO_POLL_CHAR;
1549
1550 return pl011_readw(uap, REG_DR);
1551 }
1552
1553 static void pl011_put_poll_char(struct uart_port *port,
1554 unsigned char ch)
1555 {
1556 struct uart_amba_port *uap =
1557 container_of(port, struct uart_amba_port, port);
1558
1559 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
1560 barrier();
1561
1562 pl011_writew(uap, ch, REG_DR);
1563 }
1564
1565 #endif /* CONFIG_CONSOLE_POLL */
1566
1567 static int pl011_hwinit(struct uart_port *port)
1568 {
1569 struct uart_amba_port *uap =
1570 container_of(port, struct uart_amba_port, port);
1571 int retval;
1572
1573 /* Optionaly enable pins to be muxed in and configured */
1574 pinctrl_pm_select_default_state(port->dev);
1575
1576 /*
1577 * Try to enable the clock producer.
1578 */
1579 retval = clk_prepare_enable(uap->clk);
1580 if (retval)
1581 return retval;
1582
1583 uap->port.uartclk = clk_get_rate(uap->clk);
1584
1585 /* Clear pending error and receive interrupts */
1586 pl011_writew(uap, UART011_OEIS | UART011_BEIS | UART011_PEIS |
1587 UART011_FEIS | UART011_RTIS | UART011_RXIS, REG_ICR);
1588
1589 /*
1590 * Save interrupts enable mask, and enable RX interrupts in case if
1591 * the interrupt is used for NMI entry.
1592 */
1593 uap->im = pl011_readw(uap, REG_IMSC);
1594 pl011_writew(uap, UART011_RTIM | UART011_RXIM, REG_IMSC);
1595
1596 if (dev_get_platdata(uap->port.dev)) {
1597 struct amba_pl011_data *plat;
1598
1599 plat = dev_get_platdata(uap->port.dev);
1600 if (plat->init)
1601 plat->init();
1602 }
1603 return 0;
1604 }
1605
1606 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1607 {
1608 pl011_writew(uap, lcr_h, uap->lcrh_rx);
1609 if (uap->lcrh_rx != uap->lcrh_tx) {
1610 int i;
1611 /*
1612 * Wait 10 PCLKs before writing LCRH_TX register,
1613 * to get this delay write read only register 10 times
1614 */
1615 for (i = 0; i < 10; ++i)
1616 pl011_writew(uap, 0xff, REG_MIS);
1617 pl011_writew(uap, lcr_h, uap->lcrh_tx);
1618 }
1619 }
1620
1621 static int pl011_allocate_irq(struct uart_amba_port *uap)
1622 {
1623 pl011_writew(uap, uap->im, REG_IMSC);
1624
1625 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1626 }
1627
1628 /*
1629 * Enable interrupts, only timeouts when using DMA
1630 * if initial RX DMA job failed, start in interrupt mode
1631 * as well.
1632 */
1633 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1634 {
1635 spin_lock_irq(&uap->port.lock);
1636
1637 /* Clear out any spuriously appearing RX interrupts */
1638 pl011_writew(uap, UART011_RTIS | UART011_RXIS, REG_ICR);
1639 uap->im = UART011_RTIM;
1640 if (!pl011_dma_rx_running(uap))
1641 uap->im |= UART011_RXIM;
1642 pl011_writew(uap, uap->im, REG_IMSC);
1643 spin_unlock_irq(&uap->port.lock);
1644 }
1645
1646 static int pl011_startup(struct uart_port *port)
1647 {
1648 struct uart_amba_port *uap =
1649 container_of(port, struct uart_amba_port, port);
1650 unsigned int cr;
1651 int retval;
1652
1653 retval = pl011_hwinit(port);
1654 if (retval)
1655 goto clk_dis;
1656
1657 retval = pl011_allocate_irq(uap);
1658 if (retval)
1659 goto clk_dis;
1660
1661 pl011_writew(uap, uap->vendor->ifls, REG_IFLS);
1662
1663 spin_lock_irq(&uap->port.lock);
1664
1665 /* restore RTS and DTR */
1666 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1667 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1668 pl011_writew(uap, cr, REG_CR);
1669
1670 spin_unlock_irq(&uap->port.lock);
1671
1672 /*
1673 * initialise the old status of the modem signals
1674 */
1675 uap->old_status = pl011_readw(uap, REG_FR) &
1676 UART01x_FR_MODEM_ANY;
1677
1678 /* Startup DMA */
1679 pl011_dma_startup(uap);
1680
1681 pl011_enable_interrupts(uap);
1682
1683 return 0;
1684
1685 clk_dis:
1686 clk_disable_unprepare(uap->clk);
1687 return retval;
1688 }
1689
1690 static int sbsa_uart_startup(struct uart_port *port)
1691 {
1692 struct uart_amba_port *uap =
1693 container_of(port, struct uart_amba_port, port);
1694 int retval;
1695
1696 retval = pl011_hwinit(port);
1697 if (retval)
1698 return retval;
1699
1700 retval = pl011_allocate_irq(uap);
1701 if (retval)
1702 return retval;
1703
1704 /* The SBSA UART does not support any modem status lines. */
1705 uap->old_status = 0;
1706
1707 pl011_enable_interrupts(uap);
1708
1709 return 0;
1710 }
1711
1712 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1713 unsigned int lcrh)
1714 {
1715 unsigned long val;
1716
1717 val = pl011_readw(uap, lcrh);
1718 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1719 pl011_writew(uap, val, lcrh);
1720 }
1721
1722 /*
1723 * disable the port. It should not disable RTS and DTR.
1724 * Also RTS and DTR state should be preserved to restore
1725 * it during startup().
1726 */
1727 static void pl011_disable_uart(struct uart_amba_port *uap)
1728 {
1729 unsigned int cr;
1730
1731 uap->autorts = false;
1732 spin_lock_irq(&uap->port.lock);
1733 cr = pl011_readw(uap, REG_CR);
1734 uap->old_cr = cr;
1735 cr &= UART011_CR_RTS | UART011_CR_DTR;
1736 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1737 pl011_writew(uap, cr, REG_CR);
1738 spin_unlock_irq(&uap->port.lock);
1739
1740 /*
1741 * disable break condition and fifos
1742 */
1743 pl011_shutdown_channel(uap, uap->lcrh_rx);
1744 if (uap->lcrh_rx != uap->lcrh_tx)
1745 pl011_shutdown_channel(uap, uap->lcrh_tx);
1746 }
1747
1748 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1749 {
1750 spin_lock_irq(&uap->port.lock);
1751
1752 /* mask all interrupts and clear all pending ones */
1753 uap->im = 0;
1754 pl011_writew(uap, uap->im, REG_IMSC);
1755 pl011_writew(0xffff, REG_ICR);
1756
1757 spin_unlock_irq(&uap->port.lock);
1758 }
1759
1760 static void pl011_shutdown(struct uart_port *port)
1761 {
1762 struct uart_amba_port *uap =
1763 container_of(port, struct uart_amba_port, port);
1764
1765 pl011_disable_interrupts(uap);
1766
1767 pl011_dma_shutdown(uap);
1768
1769 free_irq(uap->port.irq, uap);
1770
1771 pl011_disable_uart(uap);
1772
1773 /*
1774 * Shut down the clock producer
1775 */
1776 clk_disable_unprepare(uap->clk);
1777 /* Optionally let pins go into sleep states */
1778 pinctrl_pm_select_sleep_state(port->dev);
1779
1780 if (dev_get_platdata(uap->port.dev)) {
1781 struct amba_pl011_data *plat;
1782
1783 plat = dev_get_platdata(uap->port.dev);
1784 if (plat->exit)
1785 plat->exit();
1786 }
1787
1788 if (uap->port.ops->flush_buffer)
1789 uap->port.ops->flush_buffer(port);
1790 }
1791
1792 static void sbsa_uart_shutdown(struct uart_port *port)
1793 {
1794 struct uart_amba_port *uap =
1795 container_of(port, struct uart_amba_port, port);
1796
1797 pl011_disable_interrupts(uap);
1798
1799 free_irq(uap->port.irq, uap);
1800
1801 if (uap->port.ops->flush_buffer)
1802 uap->port.ops->flush_buffer(port);
1803 }
1804
1805 static void
1806 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1807 {
1808 port->read_status_mask = UART011_DR_OE | 255;
1809 if (termios->c_iflag & INPCK)
1810 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1811 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1812 port->read_status_mask |= UART011_DR_BE;
1813
1814 /*
1815 * Characters to ignore
1816 */
1817 port->ignore_status_mask = 0;
1818 if (termios->c_iflag & IGNPAR)
1819 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1820 if (termios->c_iflag & IGNBRK) {
1821 port->ignore_status_mask |= UART011_DR_BE;
1822 /*
1823 * If we're ignoring parity and break indicators,
1824 * ignore overruns too (for real raw support).
1825 */
1826 if (termios->c_iflag & IGNPAR)
1827 port->ignore_status_mask |= UART011_DR_OE;
1828 }
1829
1830 /*
1831 * Ignore all characters if CREAD is not set.
1832 */
1833 if ((termios->c_cflag & CREAD) == 0)
1834 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1835 }
1836
1837 static void
1838 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1839 struct ktermios *old)
1840 {
1841 struct uart_amba_port *uap =
1842 container_of(port, struct uart_amba_port, port);
1843 unsigned int lcr_h, old_cr;
1844 unsigned long flags;
1845 unsigned int baud, quot, clkdiv;
1846
1847 if (uap->vendor->oversampling)
1848 clkdiv = 8;
1849 else
1850 clkdiv = 16;
1851
1852 /*
1853 * Ask the core to calculate the divisor for us.
1854 */
1855 baud = uart_get_baud_rate(port, termios, old, 0,
1856 port->uartclk / clkdiv);
1857 #ifdef CONFIG_DMA_ENGINE
1858 /*
1859 * Adjust RX DMA polling rate with baud rate if not specified.
1860 */
1861 if (uap->dmarx.auto_poll_rate)
1862 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1863 #endif
1864
1865 if (baud > port->uartclk/16)
1866 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1867 else
1868 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1869
1870 switch (termios->c_cflag & CSIZE) {
1871 case CS5:
1872 lcr_h = UART01x_LCRH_WLEN_5;
1873 break;
1874 case CS6:
1875 lcr_h = UART01x_LCRH_WLEN_6;
1876 break;
1877 case CS7:
1878 lcr_h = UART01x_LCRH_WLEN_7;
1879 break;
1880 default: // CS8
1881 lcr_h = UART01x_LCRH_WLEN_8;
1882 break;
1883 }
1884 if (termios->c_cflag & CSTOPB)
1885 lcr_h |= UART01x_LCRH_STP2;
1886 if (termios->c_cflag & PARENB) {
1887 lcr_h |= UART01x_LCRH_PEN;
1888 if (!(termios->c_cflag & PARODD))
1889 lcr_h |= UART01x_LCRH_EPS;
1890 }
1891 if (uap->fifosize > 1)
1892 lcr_h |= UART01x_LCRH_FEN;
1893
1894 spin_lock_irqsave(&port->lock, flags);
1895
1896 /*
1897 * Update the per-port timeout.
1898 */
1899 uart_update_timeout(port, termios->c_cflag, baud);
1900
1901 pl011_setup_status_masks(port, termios);
1902
1903 if (UART_ENABLE_MS(port, termios->c_cflag))
1904 pl011_enable_ms(port);
1905
1906 /* first, disable everything */
1907 old_cr = pl011_readw(uap, REG_CR);
1908 pl011_writew(uap, 0, REG_CR);
1909
1910 if (termios->c_cflag & CRTSCTS) {
1911 if (old_cr & UART011_CR_RTS)
1912 old_cr |= UART011_CR_RTSEN;
1913
1914 old_cr |= UART011_CR_CTSEN;
1915 uap->autorts = true;
1916 } else {
1917 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1918 uap->autorts = false;
1919 }
1920
1921 if (uap->vendor->oversampling) {
1922 if (baud > port->uartclk / 16)
1923 old_cr |= ST_UART011_CR_OVSFACT;
1924 else
1925 old_cr &= ~ST_UART011_CR_OVSFACT;
1926 }
1927
1928 /*
1929 * Workaround for the ST Micro oversampling variants to
1930 * increase the bitrate slightly, by lowering the divisor,
1931 * to avoid delayed sampling of start bit at high speeds,
1932 * else we see data corruption.
1933 */
1934 if (uap->vendor->oversampling) {
1935 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1936 quot -= 1;
1937 else if ((baud > 3250000) && (quot > 2))
1938 quot -= 2;
1939 }
1940 /* Set baud rate */
1941 pl011_writew(uap, quot & 0x3f, REG_FBRD);
1942 pl011_writew(uap, quot >> 6, REG_IBRD);
1943
1944 /*
1945 * ----------v----------v----------v----------v-----
1946 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1947 * REG_FBRD & REG_IBRD.
1948 * ----------^----------^----------^----------^-----
1949 */
1950 pl011_write_lcr_h(uap, lcr_h);
1951 pl011_writew(uap, old_cr, REG_CR);
1952
1953 spin_unlock_irqrestore(&port->lock, flags);
1954 }
1955
1956 static void
1957 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1958 struct ktermios *old)
1959 {
1960 struct uart_amba_port *uap =
1961 container_of(port, struct uart_amba_port, port);
1962 unsigned long flags;
1963
1964 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
1965
1966 /* The SBSA UART only supports 8n1 without hardware flow control. */
1967 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
1968 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
1969 termios->c_cflag |= CS8 | CLOCAL;
1970
1971 spin_lock_irqsave(&port->lock, flags);
1972 uart_update_timeout(port, CS8, uap->fixed_baud);
1973 pl011_setup_status_masks(port, termios);
1974 spin_unlock_irqrestore(&port->lock, flags);
1975 }
1976
1977 static const char *pl011_type(struct uart_port *port)
1978 {
1979 struct uart_amba_port *uap =
1980 container_of(port, struct uart_amba_port, port);
1981 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1982 }
1983
1984 /*
1985 * Release the memory region(s) being used by 'port'
1986 */
1987 static void pl011_release_port(struct uart_port *port)
1988 {
1989 release_mem_region(port->mapbase, SZ_4K);
1990 }
1991
1992 /*
1993 * Request the memory region(s) being used by 'port'
1994 */
1995 static int pl011_request_port(struct uart_port *port)
1996 {
1997 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1998 != NULL ? 0 : -EBUSY;
1999 }
2000
2001 /*
2002 * Configure/autoconfigure the port.
2003 */
2004 static void pl011_config_port(struct uart_port *port, int flags)
2005 {
2006 if (flags & UART_CONFIG_TYPE) {
2007 port->type = PORT_AMBA;
2008 pl011_request_port(port);
2009 }
2010 }
2011
2012 /*
2013 * verify the new serial_struct (for TIOCSSERIAL).
2014 */
2015 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2016 {
2017 int ret = 0;
2018 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2019 ret = -EINVAL;
2020 if (ser->irq < 0 || ser->irq >= nr_irqs)
2021 ret = -EINVAL;
2022 if (ser->baud_base < 9600)
2023 ret = -EINVAL;
2024 return ret;
2025 }
2026
2027 static struct uart_ops amba_pl011_pops = {
2028 .tx_empty = pl011_tx_empty,
2029 .set_mctrl = pl011_set_mctrl,
2030 .get_mctrl = pl011_get_mctrl,
2031 .stop_tx = pl011_stop_tx,
2032 .start_tx = pl011_start_tx,
2033 .stop_rx = pl011_stop_rx,
2034 .enable_ms = pl011_enable_ms,
2035 .break_ctl = pl011_break_ctl,
2036 .startup = pl011_startup,
2037 .shutdown = pl011_shutdown,
2038 .flush_buffer = pl011_dma_flush_buffer,
2039 .set_termios = pl011_set_termios,
2040 .type = pl011_type,
2041 .release_port = pl011_release_port,
2042 .request_port = pl011_request_port,
2043 .config_port = pl011_config_port,
2044 .verify_port = pl011_verify_port,
2045 #ifdef CONFIG_CONSOLE_POLL
2046 .poll_init = pl011_hwinit,
2047 .poll_get_char = pl011_get_poll_char,
2048 .poll_put_char = pl011_put_poll_char,
2049 #endif
2050 };
2051
2052 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2053 {
2054 }
2055
2056 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2057 {
2058 return 0;
2059 }
2060
2061 static const struct uart_ops sbsa_uart_pops = {
2062 .tx_empty = pl011_tx_empty,
2063 .set_mctrl = sbsa_uart_set_mctrl,
2064 .get_mctrl = sbsa_uart_get_mctrl,
2065 .stop_tx = pl011_stop_tx,
2066 .start_tx = pl011_start_tx,
2067 .stop_rx = pl011_stop_rx,
2068 .startup = sbsa_uart_startup,
2069 .shutdown = sbsa_uart_shutdown,
2070 .set_termios = sbsa_uart_set_termios,
2071 .type = pl011_type,
2072 .release_port = pl011_release_port,
2073 .request_port = pl011_request_port,
2074 .config_port = pl011_config_port,
2075 .verify_port = pl011_verify_port,
2076 #ifdef CONFIG_CONSOLE_POLL
2077 .poll_init = pl011_hwinit,
2078 .poll_get_char = pl011_get_poll_char,
2079 .poll_put_char = pl011_put_poll_char,
2080 #endif
2081 };
2082
2083 static struct uart_amba_port *amba_ports[UART_NR];
2084
2085 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2086
2087 static void pl011_console_putchar(struct uart_port *port, int ch)
2088 {
2089 struct uart_amba_port *uap =
2090 container_of(port, struct uart_amba_port, port);
2091
2092 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
2093 barrier();
2094 pl011_writew(uap, ch, REG_DR);
2095 }
2096
2097 static void
2098 pl011_console_write(struct console *co, const char *s, unsigned int count)
2099 {
2100 struct uart_amba_port *uap = amba_ports[co->index];
2101 unsigned int status, old_cr = 0, new_cr;
2102 unsigned long flags;
2103 int locked = 1;
2104
2105 clk_enable(uap->clk);
2106
2107 local_irq_save(flags);
2108 if (uap->port.sysrq)
2109 locked = 0;
2110 else if (oops_in_progress)
2111 locked = spin_trylock(&uap->port.lock);
2112 else
2113 spin_lock(&uap->port.lock);
2114
2115 /*
2116 * First save the CR then disable the interrupts
2117 */
2118 if (!uap->vendor->always_enabled) {
2119 old_cr = pl011_readw(uap, REG_CR);
2120 new_cr = old_cr & ~UART011_CR_CTSEN;
2121 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2122 pl011_writew(uap, new_cr, REG_CR);
2123 }
2124
2125 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2126
2127 /*
2128 * Finally, wait for transmitter to become empty
2129 * and restore the TCR
2130 */
2131 do {
2132 status = pl011_readw(uap, REG_FR);
2133 } while (status & UART01x_FR_BUSY);
2134 if (!uap->vendor->always_enabled)
2135 pl011_writew(uap, old_cr, REG_CR);
2136
2137 if (locked)
2138 spin_unlock(&uap->port.lock);
2139 local_irq_restore(flags);
2140
2141 clk_disable(uap->clk);
2142 }
2143
2144 static void __init
2145 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2146 int *parity, int *bits)
2147 {
2148 if (pl011_readw(uap, REG_CR) & UART01x_CR_UARTEN) {
2149 unsigned int lcr_h, ibrd, fbrd;
2150
2151 lcr_h = pl011_readw(uap, uap->lcrh_tx);
2152
2153 *parity = 'n';
2154 if (lcr_h & UART01x_LCRH_PEN) {
2155 if (lcr_h & UART01x_LCRH_EPS)
2156 *parity = 'e';
2157 else
2158 *parity = 'o';
2159 }
2160
2161 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2162 *bits = 7;
2163 else
2164 *bits = 8;
2165
2166 ibrd = pl011_readw(uap, REG_IBRD);
2167 fbrd = pl011_readw(uap, REG_FBRD);
2168
2169 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2170
2171 if (uap->vendor->oversampling) {
2172 if (pl011_readw(uap, REG_CR)
2173 & ST_UART011_CR_OVSFACT)
2174 *baud *= 2;
2175 }
2176 }
2177 }
2178
2179 static int __init pl011_console_setup(struct console *co, char *options)
2180 {
2181 struct uart_amba_port *uap;
2182 int baud = 38400;
2183 int bits = 8;
2184 int parity = 'n';
2185 int flow = 'n';
2186 int ret;
2187
2188 /*
2189 * Check whether an invalid uart number has been specified, and
2190 * if so, search for the first available port that does have
2191 * console support.
2192 */
2193 if (co->index >= UART_NR)
2194 co->index = 0;
2195 uap = amba_ports[co->index];
2196 if (!uap)
2197 return -ENODEV;
2198
2199 /* Allow pins to be muxed in and configured */
2200 pinctrl_pm_select_default_state(uap->port.dev);
2201
2202 ret = clk_prepare(uap->clk);
2203 if (ret)
2204 return ret;
2205
2206 if (dev_get_platdata(uap->port.dev)) {
2207 struct amba_pl011_data *plat;
2208
2209 plat = dev_get_platdata(uap->port.dev);
2210 if (plat->init)
2211 plat->init();
2212 }
2213
2214 uap->port.uartclk = clk_get_rate(uap->clk);
2215
2216 if (uap->vendor->fixed_options) {
2217 baud = uap->fixed_baud;
2218 } else {
2219 if (options)
2220 uart_parse_options(options,
2221 &baud, &parity, &bits, &flow);
2222 else
2223 pl011_console_get_options(uap, &baud, &parity, &bits);
2224 }
2225
2226 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2227 }
2228
2229 static struct uart_driver amba_reg;
2230 static struct console amba_console = {
2231 .name = "ttyAMA",
2232 .write = pl011_console_write,
2233 .device = uart_console_device,
2234 .setup = pl011_console_setup,
2235 .flags = CON_PRINTBUFFER,
2236 .index = -1,
2237 .data = &amba_reg,
2238 };
2239
2240 #define AMBA_CONSOLE (&amba_console)
2241
2242 static void pl011_putc(struct uart_port *port, int c)
2243 {
2244 struct uart_amba_port *uap =
2245 container_of(port, struct uart_amba_port, port);
2246
2247 while (pl011_readw(uap, REG_FR) & UART01x_FR_TXFF)
2248 ;
2249 pl011_writeb(uap, c, REG_DR);
2250 while (pl011_readw(uap, REG_FR) & UART01x_FR_BUSY)
2251 ;
2252 }
2253
2254 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2255 {
2256 struct earlycon_device *dev = con->data;
2257
2258 uart_console_write(&dev->port, s, n, pl011_putc);
2259 }
2260
2261 static int __init pl011_early_console_setup(struct earlycon_device *device,
2262 const char *opt)
2263 {
2264 if (!device->port.membase)
2265 return -ENODEV;
2266
2267 device->con->write = pl011_early_write;
2268 return 0;
2269 }
2270 EARLYCON_DECLARE(pl011, pl011_early_console_setup);
2271 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2272
2273 #else
2274 #define AMBA_CONSOLE NULL
2275 #endif
2276
2277 static struct uart_driver amba_reg = {
2278 .owner = THIS_MODULE,
2279 .driver_name = "ttyAMA",
2280 .dev_name = "ttyAMA",
2281 .major = SERIAL_AMBA_MAJOR,
2282 .minor = SERIAL_AMBA_MINOR,
2283 .nr = UART_NR,
2284 .cons = AMBA_CONSOLE,
2285 };
2286
2287 static int pl011_probe_dt_alias(int index, struct device *dev)
2288 {
2289 struct device_node *np;
2290 static bool seen_dev_with_alias = false;
2291 static bool seen_dev_without_alias = false;
2292 int ret = index;
2293
2294 if (!IS_ENABLED(CONFIG_OF))
2295 return ret;
2296
2297 np = dev->of_node;
2298 if (!np)
2299 return ret;
2300
2301 ret = of_alias_get_id(np, "serial");
2302 if (IS_ERR_VALUE(ret)) {
2303 seen_dev_without_alias = true;
2304 ret = index;
2305 } else {
2306 seen_dev_with_alias = true;
2307 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2308 dev_warn(dev, "requested serial port %d not available.\n", ret);
2309 ret = index;
2310 }
2311 }
2312
2313 if (seen_dev_with_alias && seen_dev_without_alias)
2314 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2315
2316 return ret;
2317 }
2318
2319 /* unregisters the driver also if no more ports are left */
2320 static void pl011_unregister_port(struct uart_amba_port *uap)
2321 {
2322 int i;
2323 bool busy = false;
2324
2325 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2326 if (amba_ports[i] == uap)
2327 amba_ports[i] = NULL;
2328 else if (amba_ports[i])
2329 busy = true;
2330 }
2331 pl011_dma_remove(uap);
2332 if (!busy)
2333 uart_unregister_driver(&amba_reg);
2334 }
2335
2336 static int pl011_find_free_port(void)
2337 {
2338 int i;
2339
2340 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2341 if (amba_ports[i] == NULL)
2342 return i;
2343
2344 return -EBUSY;
2345 }
2346
2347 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2348 struct resource *mmiobase, int index)
2349 {
2350 void __iomem *base;
2351
2352 base = devm_ioremap_resource(dev, mmiobase);
2353 if (IS_ERR(base))
2354 return PTR_ERR(base);
2355
2356 index = pl011_probe_dt_alias(index, dev);
2357
2358 uap->old_cr = 0;
2359 uap->port.dev = dev;
2360 uap->port.mapbase = mmiobase->start;
2361 uap->port.membase = base;
2362 uap->port.iotype = UPIO_MEM;
2363 uap->port.fifosize = uap->fifosize;
2364 uap->port.flags = UPF_BOOT_AUTOCONF;
2365 uap->port.line = index;
2366
2367 amba_ports[index] = uap;
2368
2369 return 0;
2370 }
2371
2372 static int pl011_register_port(struct uart_amba_port *uap)
2373 {
2374 int ret;
2375
2376 /* Ensure interrupts from this UART are masked and cleared */
2377 pl011_writew(uap, 0, REG_IMSC);
2378 pl011_writew(uap, 0xffff, REG_ICR);
2379
2380 if (!amba_reg.state) {
2381 ret = uart_register_driver(&amba_reg);
2382 if (ret < 0) {
2383 dev_err(uap->port.dev,
2384 "Failed to register AMBA-PL011 driver\n");
2385 return ret;
2386 }
2387 }
2388
2389 ret = uart_add_one_port(&amba_reg, &uap->port);
2390 if (ret)
2391 pl011_unregister_port(uap);
2392
2393 return ret;
2394 }
2395
2396 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2397 {
2398 struct uart_amba_port *uap;
2399 struct vendor_data *vendor = id->data;
2400 int portnr, ret;
2401
2402 portnr = pl011_find_free_port();
2403 if (portnr < 0)
2404 return portnr;
2405
2406 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2407 GFP_KERNEL);
2408 if (!uap)
2409 return -ENOMEM;
2410
2411 uap->clk = devm_clk_get(&dev->dev, NULL);
2412 if (IS_ERR(uap->clk))
2413 return PTR_ERR(uap->clk);
2414
2415 uap->vendor = vendor;
2416 uap->lcrh_rx = vendor->lcrh_rx;
2417 uap->lcrh_tx = vendor->lcrh_tx;
2418 uap->fifosize = vendor->get_fifosize(dev);
2419 uap->port.irq = dev->irq[0];
2420 uap->port.ops = &amba_pl011_pops;
2421
2422 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2423
2424 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2425 if (ret)
2426 return ret;
2427
2428 amba_set_drvdata(dev, uap);
2429
2430 return pl011_register_port(uap);
2431 }
2432
2433 static int pl011_remove(struct amba_device *dev)
2434 {
2435 struct uart_amba_port *uap = amba_get_drvdata(dev);
2436
2437 uart_remove_one_port(&amba_reg, &uap->port);
2438 pl011_unregister_port(uap);
2439 return 0;
2440 }
2441
2442 #ifdef CONFIG_PM_SLEEP
2443 static int pl011_suspend(struct device *dev)
2444 {
2445 struct uart_amba_port *uap = dev_get_drvdata(dev);
2446
2447 if (!uap)
2448 return -EINVAL;
2449
2450 return uart_suspend_port(&amba_reg, &uap->port);
2451 }
2452
2453 static int pl011_resume(struct device *dev)
2454 {
2455 struct uart_amba_port *uap = dev_get_drvdata(dev);
2456
2457 if (!uap)
2458 return -EINVAL;
2459
2460 return uart_resume_port(&amba_reg, &uap->port);
2461 }
2462 #endif
2463
2464 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2465
2466 static int sbsa_uart_probe(struct platform_device *pdev)
2467 {
2468 struct uart_amba_port *uap;
2469 struct resource *r;
2470 int portnr, ret;
2471 int baudrate;
2472
2473 /*
2474 * Check the mandatory baud rate parameter in the DT node early
2475 * so that we can easily exit with the error.
2476 */
2477 if (pdev->dev.of_node) {
2478 struct device_node *np = pdev->dev.of_node;
2479
2480 ret = of_property_read_u32(np, "current-speed", &baudrate);
2481 if (ret)
2482 return ret;
2483 } else {
2484 baudrate = 115200;
2485 }
2486
2487 portnr = pl011_find_free_port();
2488 if (portnr < 0)
2489 return portnr;
2490
2491 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2492 GFP_KERNEL);
2493 if (!uap)
2494 return -ENOMEM;
2495
2496 uap->vendor = &vendor_sbsa;
2497 uap->fifosize = 32;
2498 uap->port.irq = platform_get_irq(pdev, 0);
2499 uap->port.ops = &sbsa_uart_pops;
2500 uap->fixed_baud = baudrate;
2501
2502 snprintf(uap->type, sizeof(uap->type), "SBSA");
2503
2504 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2505
2506 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2507 if (ret)
2508 return ret;
2509
2510 platform_set_drvdata(pdev, uap);
2511
2512 return pl011_register_port(uap);
2513 }
2514
2515 static int sbsa_uart_remove(struct platform_device *pdev)
2516 {
2517 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2518
2519 uart_remove_one_port(&amba_reg, &uap->port);
2520 pl011_unregister_port(uap);
2521 return 0;
2522 }
2523
2524 static const struct of_device_id sbsa_uart_of_match[] = {
2525 { .compatible = "arm,sbsa-uart", },
2526 {},
2527 };
2528 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2529
2530 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2531 { "ARMH0011", 0 },
2532 {},
2533 };
2534 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2535
2536 static struct platform_driver arm_sbsa_uart_platform_driver = {
2537 .probe = sbsa_uart_probe,
2538 .remove = sbsa_uart_remove,
2539 .driver = {
2540 .name = "sbsa-uart",
2541 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2542 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2543 },
2544 };
2545
2546 static struct amba_id pl011_ids[] = {
2547 {
2548 .id = 0x00041011,
2549 .mask = 0x000fffff,
2550 .data = &vendor_arm,
2551 },
2552 {
2553 .id = 0x00380802,
2554 .mask = 0x00ffffff,
2555 .data = &vendor_st,
2556 },
2557 { 0, 0 },
2558 };
2559
2560 MODULE_DEVICE_TABLE(amba, pl011_ids);
2561
2562 static struct amba_driver pl011_driver = {
2563 .drv = {
2564 .name = "uart-pl011",
2565 .pm = &pl011_dev_pm_ops,
2566 },
2567 .id_table = pl011_ids,
2568 .probe = pl011_probe,
2569 .remove = pl011_remove,
2570 };
2571
2572 static int __init pl011_init(void)
2573 {
2574 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2575
2576 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2577 pr_warn("could not register SBSA UART platform driver\n");
2578 return amba_driver_register(&pl011_driver);
2579 }
2580
2581 static void __exit pl011_exit(void)
2582 {
2583 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2584 amba_driver_unregister(&pl011_driver);
2585 }
2586
2587 /*
2588 * While this can be a module, if builtin it's most likely the console
2589 * So let's leave module_exit but move module_init to an earlier place
2590 */
2591 arch_initcall(pl011_init);
2592 module_exit(pl011_exit);
2593
2594 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2595 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2596 MODULE_LICENSE("GPL");
Linux with added FPC-III support