arch/blackfin/mach-bf538/include/mach/irq.h

   1 /*
   2  * file:        include/asm-blackfin/mach-bf538/irq.h
   3  * based on:    include/asm-blackfin/mach-bf537/irq.h
   4  * author:      Michael Hennerich (michael.hennerich@analog.com)
   5  *
   6  * created:
   7  * description:
   8  *      system mmr register map
   9  * rev:
  10  *
  11  * modified:
  12  *
  13  *
  14  * bugs:         enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * this program is free software; you can redistribute it and/or modify
  17  * it under the terms of the gnu general public license as published by
  18  * the free software foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * this program is distributed in the hope that it will be useful,
  22  * but without any warranty; without even the implied warranty of
  23  * merchantability or fitness for a particular purpose.  see the
  24  * gnu general public license for more details.
  25  *
  26  * you should have received a copy of the gnu general public license
  27  * along with this program; see the file copying.
  28  * if not, write to the free software foundation,
  29  * 59 temple place - suite 330, boston, ma 02111-1307, usa.
  30  */
  31
  32 #ifndef _BF538_IRQ_H_
  33 #define _BF538_IRQ_H_
  34
  35 /*
  36  * Interrupt source definitions
  37         Event Source    Core Event Name
  38         Core        Emulation               **
  39         Events         (highest priority)  EMU         0
  40         Reset                   RST         1
  41         NMI                     NMI         2
  42         Exception               EVX         3
  43         Reserved                --          4
  44         Hardware Error          IVHW        5
  45         Core Timer              IVTMR       6 *
  46
  47         .....
  48
  49          Software Interrupt 1    IVG14       31
  50          Software Interrupt 2    --
  51          (lowest priority)  IVG15       32 *
  52 */
  53
  54 #define NR_PERI_INTS    (2 * 32)
  55
  56 /* The ABSTRACT IRQ definitions */
  57 /** the first seven of the following are fixed, the rest you change if you need to **/
  58 #define IRQ_EMU                 0       /* Emulation */
  59 #define IRQ_RST                 1       /* reset */
  60 #define IRQ_NMI                 2       /* Non Maskable */
  61 #define IRQ_EVX                 3       /* Exception */
  62 #define IRQ_UNUSED              4       /* - unused interrupt */
  63 #define IRQ_HWERR               5       /* Hardware Error */
  64 #define IRQ_CORETMR             6       /* Core timer */
  65
  66 #define BFIN_IRQ(x)             ((x) + 7)
  67
  68 #define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
  69 #define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
  70 #define IRQ_PPI_ERROR           BFIN_IRQ(2)     /* PPI Error */
  71 #define IRQ_SPORT0_ERROR        BFIN_IRQ(3)     /* SPORT0 Status */
  72 #define IRQ_SPORT1_ERROR        BFIN_IRQ(4)     /* SPORT1 Status */
  73 #define IRQ_SPI0_ERROR          BFIN_IRQ(5)     /* SPI0 Status */
  74 #define IRQ_UART0_ERROR         BFIN_IRQ(6)     /* UART0 Status */
  75 #define IRQ_RTC                 BFIN_IRQ(7)     /* RTC */
  76 #define IRQ_PPI                 BFIN_IRQ(8)     /* DMA Channel 0 (PPI) */
  77 #define IRQ_SPORT0_RX           BFIN_IRQ(9)     /* DMA 1 Channel (SPORT0 RX) */
  78 #define IRQ_SPORT0_TX           BFIN_IRQ(10)    /* DMA 2 Channel (SPORT0 TX) */
  79 #define IRQ_SPORT1_RX           BFIN_IRQ(11)    /* DMA 3 Channel (SPORT1 RX) */
  80 #define IRQ_SPORT1_TX           BFIN_IRQ(12)    /* DMA 4 Channel (SPORT1 TX) */
  81 #define IRQ_SPI0                BFIN_IRQ(13)    /* DMA 5 Channel (SPI0) */
  82 #define IRQ_UART0_RX            BFIN_IRQ(14)    /* DMA 6 Channel (UART0 RX) */
  83 #define IRQ_UART0_TX            BFIN_IRQ(15)    /* DMA 7 Channel (UART0 TX) */
  84 #define IRQ_TIMER0              BFIN_IRQ(16)    /* Timer 0 */
  85 #define IRQ_TIMER1              BFIN_IRQ(17)    /* Timer 1 */
  86 #define IRQ_TIMER2              BFIN_IRQ(18)    /* Timer 2 */
  87 #define IRQ_PORTF_INTA          BFIN_IRQ(19)    /* Port F Interrupt A */
  88 #define IRQ_PORTF_INTB          BFIN_IRQ(20)    /* Port F Interrupt B */
  89 #define IRQ_MEM0_DMA0           BFIN_IRQ(21)    /* MDMA0 Stream 0 */
  90 #define IRQ_MEM0_DMA1           BFIN_IRQ(22)    /* MDMA0 Stream 1 */
  91 #define IRQ_WATCH               BFIN_IRQ(23)    /* Software Watchdog Timer */
  92 #define IRQ_DMA1_ERROR          BFIN_IRQ(24)    /* DMA Error 1 (generic) */
  93 #define IRQ_SPORT2_ERROR        BFIN_IRQ(25)    /* SPORT2 Status */
  94 #define IRQ_SPORT3_ERROR        BFIN_IRQ(26)    /* SPORT3 Status */
  95 #define IRQ_SPI1_ERROR          BFIN_IRQ(28)    /* SPI1 Status */
  96 #define IRQ_SPI2_ERROR          BFIN_IRQ(29)    /* SPI2 Status */
  97 #define IRQ_UART1_ERROR         BFIN_IRQ(30)    /* UART1 Status */
  98 #define IRQ_UART2_ERROR         BFIN_IRQ(31)    /* UART2 Status */
  99 #define IRQ_CAN_ERROR           BFIN_IRQ(32)    /* CAN Status (Error) Interrupt */
 100 #define IRQ_SPORT2_RX           BFIN_IRQ(33)    /* DMA 8 Channel (SPORT2 RX) */
 101 #define IRQ_SPORT2_TX           BFIN_IRQ(34)    /* DMA 9 Channel (SPORT2 TX) */
 102 #define IRQ_SPORT3_RX           BFIN_IRQ(35)    /* DMA 10 Channel (SPORT3 RX) */
 103 #define IRQ_SPORT3_TX           BFIN_IRQ(36)    /* DMA 11 Channel (SPORT3 TX) */
 104 #define IRQ_SPI1                BFIN_IRQ(39)    /* DMA 14 Channel (SPI1) */
 105 #define IRQ_SPI2                BFIN_IRQ(40)    /* DMA 15 Channel (SPI2) */
 106 #define IRQ_UART1_RX            BFIN_IRQ(41)    /* DMA 16 Channel (UART1 RX) */
 107 #define IRQ_UART1_TX            BFIN_IRQ(42)    /* DMA 17 Channel (UART1 TX) */
 108 #define IRQ_UART2_RX            BFIN_IRQ(43)    /* DMA 18 Channel (UART2 RX) */
 109 #define IRQ_UART2_TX            BFIN_IRQ(44)    /* DMA 19 Channel (UART2 TX) */
 110 #define IRQ_TWI0                BFIN_IRQ(45)    /* TWI0 */
 111 #define IRQ_TWI1                BFIN_IRQ(46)    /* TWI1 */
 112 #define IRQ_CAN_RX              BFIN_IRQ(47)    /* CAN Receive Interrupt */
 113 #define IRQ_CAN_TX              BFIN_IRQ(48)    /* CAN Transmit Interrupt */
 114 #define IRQ_MEM1_DMA0           BFIN_IRQ(49)    /* MDMA1 Stream 0 */
 115 #define IRQ_MEM1_DMA1           BFIN_IRQ(50)    /* MDMA1 Stream 1 */
 116
 117 #define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
 118
 119 #define IRQ_PF0         71
 120 #define IRQ_PF1         72
 121 #define IRQ_PF2         73
 122 #define IRQ_PF3         74
 123 #define IRQ_PF4         75
 124 #define IRQ_PF5         76
 125 #define IRQ_PF6         77
 126 #define IRQ_PF7         78
 127 #define IRQ_PF8         79
 128 #define IRQ_PF9         80
 129 #define IRQ_PF10        81
 130 #define IRQ_PF11        82
 131 #define IRQ_PF12        83
 132 #define IRQ_PF13        84
 133 #define IRQ_PF14        85
 134 #define IRQ_PF15        86
 135
 136 #define GPIO_IRQ_BASE   IRQ_PF0
 137
 138 #define NR_IRQS     (IRQ_PF15+1)
 139
 140 #define IVG7            7
 141 #define IVG8            8
 142 #define IVG9            9
 143 #define IVG10           10
 144 #define IVG11           11
 145 #define IVG12           12
 146 #define IVG13           13
 147 #define IVG14           14
 148 #define IVG15           15
 149
 150 /* IAR0 BIT FIELDS */
 151 #define IRQ_PLL_WAKEUP_POS      0
 152 #define IRQ_DMA0_ERROR_POS      4
 153 #define IRQ_PPI_ERROR_POS       8
 154 #define IRQ_SPORT0_ERROR_POS    12
 155 #define IRQ_SPORT1_ERROR_POS    16
 156 #define IRQ_SPI0_ERROR_POS      20
 157 #define IRQ_UART0_ERROR_POS     24
 158 #define IRQ_RTC_POS             28
 159
 160 /* IAR1 BIT FIELDS */
 161 #define IRQ_PPI_POS             0
 162 #define IRQ_SPORT0_RX_POS       4
 163 #define IRQ_SPORT0_TX_POS       8
 164 #define IRQ_SPORT1_RX_POS       12
 165 #define IRQ_SPORT1_TX_POS       16
 166 #define IRQ_SPI0_POS            20
 167 #define IRQ_UART0_RX_POS        24
 168 #define IRQ_UART0_TX_POS        28
 169
 170 /* IAR2 BIT FIELDS */
 171 #define IRQ_TIMER0_POS          0
 172 #define IRQ_TIMER1_POS          4
 173 #define IRQ_TIMER2_POS          8
 174 #define IRQ_PORTF_INTA_POS      12
 175 #define IRQ_PORTF_INTB_POS      16
 176 #define IRQ_MEM0_DMA0_POS       20
 177 #define IRQ_MEM0_DMA1_POS       24
 178 #define IRQ_WATCH_POS           28
 179
 180 /* IAR3 BIT FIELDS */
 181 #define IRQ_DMA1_ERROR_POS      0
 182 #define IRQ_SPORT2_ERROR_POS    4
 183 #define IRQ_SPORT3_ERROR_POS    8
 184 #define IRQ_SPI1_ERROR_POS      16
 185 #define IRQ_SPI2_ERROR_POS      20
 186 #define IRQ_UART1_ERROR_POS     24
 187 #define IRQ_UART2_ERROR_POS     28
 188
 189 /* IAR4 BIT FIELDS */
 190 #define IRQ_CAN_ERROR_POS       0
 191 #define IRQ_SPORT2_RX_POS       4
 192 #define IRQ_SPORT2_TX_POS       8
 193 #define IRQ_SPORT3_RX_POS       12
 194 #define IRQ_SPORT3_TX_POS       16
 195 #define IRQ_SPI1_POS            28
 196
 197 /* IAR5 BIT FIELDS */
 198 #define IRQ_SPI2_POS            0
 199 #define IRQ_UART1_RX_POS        4
 200 #define IRQ_UART1_TX_POS        8
 201 #define IRQ_UART2_RX_POS        12
 202 #define IRQ_UART2_TX_POS        16
 203 #define IRQ_TWI0_POS            20
 204 #define IRQ_TWI1_POS            24
 205 #define IRQ_CAN_RX_POS          28
 206
 207 /* IAR6 BIT FIELDS */
 208 #define IRQ_CAN_TX_POS          0
 209 #define IRQ_MEM1_DMA0_POS       4
 210 #define IRQ_MEM1_DMA1_POS       8
 211 #endif                          /* _BF538_IRQ_H_ */