arch/sh/kernel/cpu/sh4/probe.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4/probe.c
   3  *
   4  * CPU Subtype Probing for SH-4.
   5  *
   6  * Copyright (C) 2001 - 2007  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/io.h>
  15 #include <asm/processor.h>
  16 #include <asm/cache.h>
  17
  18 int __init detect_cpu_and_cache_system(void)
  19 {
  20         unsigned long pvr, prr, cvr;
  21         unsigned long size;
  22
  23         static unsigned long sizes[16] = {
  24                 [1] = (1 << 12),
  25                 [2] = (1 << 13),
  26                 [4] = (1 << 14),
  27                 [8] = (1 << 15),
  28                 [9] = (1 << 16)
  29         };
  30
  31         pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
  32         prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
  33         cvr = (ctrl_inl(CCN_CVR));
  34
  35         /*
  36          * Setup some sane SH-4 defaults for the icache
  37          */
  38         boot_cpu_data.icache.way_incr           = (1 << 13);
  39         boot_cpu_data.icache.entry_shift        = 5;
  40         boot_cpu_data.icache.sets               = 256;
  41         boot_cpu_data.icache.ways               = 1;
  42         boot_cpu_data.icache.linesz             = L1_CACHE_BYTES;
  43
  44         /*
  45          * And again for the dcache ..
  46          */
  47         boot_cpu_data.dcache.way_incr           = (1 << 14);
  48         boot_cpu_data.dcache.entry_shift        = 5;
  49         boot_cpu_data.dcache.sets               = 512;
  50         boot_cpu_data.dcache.ways               = 1;
  51         boot_cpu_data.dcache.linesz             = L1_CACHE_BYTES;
  52
  53         /* We don't know the chip cut */
  54         boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;
  55
  56         /*
  57          * Setup some generic flags we can probe on SH-4A parts
  58          */
  59         if (((pvr >> 16) & 0xff) == 0x10) {
  60                 if ((cvr & 0x10000000) == 0)
  61                         boot_cpu_data.flags |= CPU_HAS_DSP;
  62
  63                 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
  64                 boot_cpu_data.cut_major = pvr & 0x7f;
  65
  66                 boot_cpu_data.icache.ways = 4;
  67                 boot_cpu_data.dcache.ways = 4;
  68         } else {
  69                 /* And some SH-4 defaults.. */
  70                 boot_cpu_data.flags |= CPU_HAS_PTEA;
  71         }
  72
  73         /* FPU detection works for everyone */
  74         if ((cvr & 0x20000000))
  75                 boot_cpu_data.flags |= CPU_HAS_FPU;
  76
  77         /* Mask off the upper chip ID */
  78         pvr &= 0xffff;
  79
  80         /*
  81          * Probe the underlying processor version/revision and
  82          * adjust cpu_data setup accordingly.
  83          */
  84         switch (pvr) {
  85         case 0x205:
  86                 boot_cpu_data.type = CPU_SH7750;
  87                 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
  88                                        CPU_HAS_PERF_COUNTER;
  89                 break;
  90         case 0x206:
  91                 boot_cpu_data.type = CPU_SH7750S;
  92                 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
  93                                        CPU_HAS_PERF_COUNTER;
  94                 break;
  95         case 0x1100:
  96                 boot_cpu_data.type = CPU_SH7751;
  97                 break;
  98         case 0x2001:
  99         case 0x2004:
 100                 boot_cpu_data.type = CPU_SH7770;
 101                 break;
 102         case 0x2006:
 103         case 0x200A:
 104                 if (prr == 0x61)
 105                         boot_cpu_data.type = CPU_SH7781;
 106                 else if (prr == 0xa1)
 107                         boot_cpu_data.type = CPU_SH7763;
 108                 else
 109                         boot_cpu_data.type = CPU_SH7780;
 110
 111                 break;
 112         case 0x3000:
 113         case 0x3003:
 114         case 0x3009:
 115                 boot_cpu_data.type = CPU_SH7343;
 116                 break;
 117         case 0x3004:
 118         case 0x3007:
 119                 boot_cpu_data.type = CPU_SH7785;
 120                 break;
 121         case 0x4004:
 122                 boot_cpu_data.type = CPU_SH7786;
 123                 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
 124                 break;
 125         case 0x3008:
 126                 switch (prr) {
 127                 case 0x50:
 128                 case 0x51:
 129                         boot_cpu_data.type = CPU_SH7723;
 130                         boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
 131                         break;
 132                 case 0x70:
 133                         boot_cpu_data.type = CPU_SH7366;
 134                         break;
 135                 case 0xa0:
 136                 case 0xa1:
 137                         boot_cpu_data.type = CPU_SH7722;
 138                         break;
 139                 }
 140                 break;
 141         case 0x300b:
 142                 boot_cpu_data.type = CPU_SH7724;
 143                 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
 144                 break;
 145         case 0x4000:    /* 1st cut */
 146         case 0x4001:    /* 2nd cut */
 147                 boot_cpu_data.type = CPU_SHX3;
 148                 break;
 149         case 0x700:
 150                 boot_cpu_data.type = CPU_SH4_501;
 151                 boot_cpu_data.icache.ways = 2;
 152                 boot_cpu_data.dcache.ways = 2;
 153                 break;
 154         case 0x600:
 155                 boot_cpu_data.type = CPU_SH4_202;
 156                 boot_cpu_data.icache.ways = 2;
 157                 boot_cpu_data.dcache.ways = 2;
 158                 break;
 159         case 0x500 ... 0x501:
 160                 switch (prr) {
 161                 case 0x10:
 162                         boot_cpu_data.type = CPU_SH7750R;
 163                         break;
 164                 case 0x11:
 165                         boot_cpu_data.type = CPU_SH7751R;
 166                         break;
 167                 case 0x50 ... 0x5f:
 168                         boot_cpu_data.type = CPU_SH7760;
 169                         break;
 170                 }
 171
 172                 boot_cpu_data.icache.ways = 2;
 173                 boot_cpu_data.dcache.ways = 2;
 174
 175                 break;
 176         default:
 177                 boot_cpu_data.type = CPU_SH_NONE;
 178                 break;
 179         }
 180
 181         /*
 182          * On anything that's not a direct-mapped cache, look to the CVR
 183          * for I/D-cache specifics.
 184          */
 185         if (boot_cpu_data.icache.ways > 1) {
 186                 size = sizes[(cvr >> 20) & 0xf];
 187                 boot_cpu_data.icache.way_incr   = (size >> 1);
 188                 boot_cpu_data.icache.sets       = (size >> 6);
 189
 190         }
 191
 192         /* And the rest of the D-cache */
 193         if (boot_cpu_data.dcache.ways > 1) {
 194                 size = sizes[(cvr >> 16) & 0xf];
 195                 boot_cpu_data.dcache.way_incr   = (size >> 1);
 196                 boot_cpu_data.dcache.sets       = (size >> 6);
 197         }
 198
 199         /*
 200          * SH-4A's have an optional PIPT L2.
 201          */
 202         if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
 203                 /*
 204                  * Verify that it really has something hooked up, this
 205                  * is the safety net for CPUs that have optional L2
 206                  * support yet do not implement it.
 207                  */
 208                 if ((cvr & 0xf) == 0)
 209                         boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
 210                 else {
 211                         /*
 212                          * Silicon and specifications have clearly never
 213                          * met..
 214                          */
 215                         cvr ^= 0xf;
 216
 217                         /*
 218                          * Size calculation is much more sensible
 219                          * than it is for the L1.
 220                          *
 221                          * Sizes are 128KB, 258KB, 512KB, and 1MB.
 222                          */
 223                         size = (cvr & 0xf) << 17;
 224
 225                         boot_cpu_data.scache.way_incr           = (1 << 16);
 226                         boot_cpu_data.scache.entry_shift        = 5;
 227                         boot_cpu_data.scache.ways               = 4;
 228                         boot_cpu_data.scache.linesz             = L1_CACHE_BYTES;
 229
 230                         boot_cpu_data.scache.entry_mask =
 231                                 (boot_cpu_data.scache.way_incr -
 232                                  boot_cpu_data.scache.linesz);
 233
 234                         boot_cpu_data.scache.sets       = size /
 235                                 (boot_cpu_data.scache.linesz *
 236                                  boot_cpu_data.scache.ways);
 237
 238                         boot_cpu_data.scache.way_size   =
 239                                 (boot_cpu_data.scache.sets *
 240                                  boot_cpu_data.scache.linesz);
 241                 }
 242         }
 243
 244         return 0;
 245 }