arch/x86/include/asm/apic.h

   1 #ifndef _ASM_X86_APIC_H
   2 #define _ASM_X86_APIC_H
   3
   4 #include <linux/cpumask.h>
   5 #include <linux/delay.h>
   6 #include <linux/pm.h>
   7
   8 #include <asm/alternative.h>
   9 #include <asm/cpufeature.h>
  10 #include <asm/processor.h>
  11 #include <asm/apicdef.h>
  12 #include <asm/atomic.h>
  13 #include <asm/fixmap.h>
  14 #include <asm/mpspec.h>
  15 #include <asm/system.h>
  16 #include <asm/msr.h>
  17
  18 #define ARCH_APICTIMER_STOPS_ON_C3      1
  19
  20 /*
  21  * Debugging macros
  22  */
  23 #define APIC_QUIET   0
  24 #define APIC_VERBOSE 1
  25 #define APIC_DEBUG   2
  26
  27 /*
  28  * Define the default level of output to be very little
  29  * This can be turned up by using apic=verbose for more
  30  * information and apic=debug for _lots_ of information.
  31  * apic_verbosity is defined in apic.c
  32  */
  33 #define apic_printk(v, s, a...) do {       \
  34                 if ((v) <= apic_verbosity) \
  35                         printk(s, ##a);    \
  36         } while (0)
  37
  38
  39 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
  40 extern void generic_apic_probe(void);
  41 #else
  42 static inline void generic_apic_probe(void)
  43 {
  44 }
  45 #endif
  46
  47 #ifdef CONFIG_X86_LOCAL_APIC
  48
  49 extern unsigned int apic_verbosity;
  50 extern int local_apic_timer_c2_ok;
  51
  52 extern int disable_apic;
  53
  54 #ifdef CONFIG_SMP
  55 extern void __inquire_remote_apic(int apicid);
  56 #else /* CONFIG_SMP */
  57 static inline void __inquire_remote_apic(int apicid)
  58 {
  59 }
  60 #endif /* CONFIG_SMP */
  61
  62 static inline void default_inquire_remote_apic(int apicid)
  63 {
  64         if (apic_verbosity >= APIC_DEBUG)
  65                 __inquire_remote_apic(apicid);
  66 }
  67
  68 /*
  69  * Basic functions accessing APICs.
  70  */
  71 #ifdef CONFIG_PARAVIRT
  72 #include <asm/paravirt.h>
  73 #else
  74 #define setup_boot_clock setup_boot_APIC_clock
  75 #define setup_secondary_clock setup_secondary_APIC_clock
  76 #endif
  77
  78 #ifdef CONFIG_X86_64
  79 extern int is_vsmp_box(void);
  80 #else
  81 static inline int is_vsmp_box(void)
  82 {
  83         return 0;
  84 }
  85 #endif
  86 extern void xapic_wait_icr_idle(void);
  87 extern u32 safe_xapic_wait_icr_idle(void);
  88 extern void xapic_icr_write(u32, u32);
  89 extern int setup_profiling_timer(unsigned int);
  90
  91 static inline void native_apic_mem_write(u32 reg, u32 v)
  92 {
  93         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
  94
  95         alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
  96                        ASM_OUTPUT2("=r" (v), "=m" (*addr)),
  97                        ASM_OUTPUT2("0" (v), "m" (*addr)));
  98 }
  99
 100 static inline u32 native_apic_mem_read(u32 reg)
 101 {
 102         return *((volatile u32 *)(APIC_BASE + reg));
 103 }
 104
 105 extern void native_apic_wait_icr_idle(void);
 106 extern u32 native_safe_apic_wait_icr_idle(void);
 107 extern void native_apic_icr_write(u32 low, u32 id);
 108 extern u64 native_apic_icr_read(void);
 109
 110 extern int x2apic_mode;
 111
 112 #ifdef CONFIG_X86_X2APIC
 113 /*
 114  * Make previous memory operations globally visible before
 115  * sending the IPI through x2apic wrmsr. We need a serializing instruction or
 116  * mfence for this.
 117  */
 118 static inline void x2apic_wrmsr_fence(void)
 119 {
 120         asm volatile("mfence" : : : "memory");
 121 }
 122
 123 static inline void native_apic_msr_write(u32 reg, u32 v)
 124 {
 125         if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
 126             reg == APIC_LVR)
 127                 return;
 128
 129         wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
 130 }
 131
 132 static inline u32 native_apic_msr_read(u32 reg)
 133 {
 134         u32 low, high;
 135
 136         if (reg == APIC_DFR)
 137                 return -1;
 138
 139         rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
 140         return low;
 141 }
 142
 143 static inline void native_x2apic_wait_icr_idle(void)
 144 {
 145         /* no need to wait for icr idle in x2apic */
 146         return;
 147 }
 148
 149 static inline u32 native_safe_x2apic_wait_icr_idle(void)
 150 {
 151         /* no need to wait for icr idle in x2apic */
 152         return 0;
 153 }
 154
 155 static inline void native_x2apic_icr_write(u32 low, u32 id)
 156 {
 157         wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
 158 }
 159
 160 static inline u64 native_x2apic_icr_read(void)
 161 {
 162         unsigned long val;
 163
 164         rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
 165         return val;
 166 }
 167
 168 extern int x2apic_phys;
 169 extern void check_x2apic(void);
 170 extern void enable_x2apic(void);
 171 extern void x2apic_icr_write(u32 low, u32 id);
 172 static inline int x2apic_enabled(void)
 173 {
 174         int msr, msr2;
 175
 176         if (!cpu_has_x2apic)
 177                 return 0;
 178
 179         rdmsr(MSR_IA32_APICBASE, msr, msr2);
 180         if (msr & X2APIC_ENABLE)
 181                 return 1;
 182         return 0;
 183 }
 184
 185 #define x2apic_supported()      (cpu_has_x2apic)
 186 static inline void x2apic_force_phys(void)
 187 {
 188         x2apic_phys = 1;
 189 }
 190 #else
 191 static inline void check_x2apic(void)
 192 {
 193 }
 194 static inline void enable_x2apic(void)
 195 {
 196 }
 197 static inline int x2apic_enabled(void)
 198 {
 199         return 0;
 200 }
 201 static inline void x2apic_force_phys(void)
 202 {
 203 }
 204
 205 #define x2apic_preenabled 0
 206 #define x2apic_supported()      0
 207 #endif
 208
 209 extern void enable_IR_x2apic(void);
 210
 211 extern int get_physical_broadcast(void);
 212
 213 extern void apic_disable(void);
 214 extern int lapic_get_maxlvt(void);
 215 extern void clear_local_APIC(void);
 216 extern void connect_bsp_APIC(void);
 217 extern void disconnect_bsp_APIC(int virt_wire_setup);
 218 extern void disable_local_APIC(void);
 219 extern void lapic_shutdown(void);
 220 extern int verify_local_APIC(void);
 221 extern void cache_APIC_registers(void);
 222 extern void sync_Arb_IDs(void);
 223 extern void init_bsp_APIC(void);
 224 extern void setup_local_APIC(void);
 225 extern void end_local_APIC_setup(void);
 226 extern void init_apic_mappings(void);
 227 extern void setup_boot_APIC_clock(void);
 228 extern void setup_secondary_APIC_clock(void);
 229 extern int APIC_init_uniprocessor(void);
 230 extern void enable_NMI_through_LVT0(void);
 231
 232 /*
 233  * On 32bit this is mach-xxx local
 234  */
 235 #ifdef CONFIG_X86_64
 236 extern void early_init_lapic_mapping(void);
 237 extern int apic_is_clustered_box(void);
 238 #else
 239 static inline int apic_is_clustered_box(void)
 240 {
 241         return 0;
 242 }
 243 #endif
 244
 245 extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
 246 extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
 247
 248
 249 #else /* !CONFIG_X86_LOCAL_APIC */
 250 static inline void lapic_shutdown(void) { }
 251 #define local_apic_timer_c2_ok          1
 252 static inline void init_apic_mappings(void) { }
 253 static inline void disable_local_APIC(void) { }
 254 static inline void apic_disable(void) { }
 255 #endif /* !CONFIG_X86_LOCAL_APIC */
 256
 257 #ifdef CONFIG_X86_64
 258 #define SET_APIC_ID(x)          (apic->set_apic_id(x))
 259 #else
 260
 261 #endif
 262
 263 /*
 264  * Copyright 2004 James Cleverdon, IBM.
 265  * Subject to the GNU Public License, v.2
 266  *
 267  * Generic APIC sub-arch data struct.
 268  *
 269  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
 270  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
 271  * James Cleverdon.
 272  */
 273 struct apic {
 274         char *name;
 275
 276         int (*probe)(void);
 277         int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
 278         int (*apic_id_registered)(void);
 279
 280         u32 irq_delivery_mode;
 281         u32 irq_dest_mode;
 282
 283         const struct cpumask *(*target_cpus)(void);
 284
 285         int disable_esr;
 286
 287         int dest_logical;
 288         unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid);
 289         unsigned long (*check_apicid_present)(int apicid);
 290
 291         void (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
 292         void (*init_apic_ldr)(void);
 293
 294         physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map);
 295
 296         void (*setup_apic_routing)(void);
 297         int (*multi_timer_check)(int apic, int irq);
 298         int (*apicid_to_node)(int logical_apicid);
 299         int (*cpu_to_logical_apicid)(int cpu);
 300         int (*cpu_present_to_apicid)(int mps_cpu);
 301         physid_mask_t (*apicid_to_cpu_present)(int phys_apicid);
 302         void (*setup_portio_remap)(void);
 303         int (*check_phys_apicid_present)(int boot_cpu_physical_apicid);
 304         void (*enable_apic_mode)(void);
 305         int (*phys_pkg_id)(int cpuid_apic, int index_msb);
 306
 307         /*
 308          * When one of the next two hooks returns 1 the apic
 309          * is switched to this. Essentially they are additional
 310          * probe functions:
 311          */
 312         int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
 313
 314         unsigned int (*get_apic_id)(unsigned long x);
 315         unsigned long (*set_apic_id)(unsigned int id);
 316         unsigned long apic_id_mask;
 317
 318         unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask);
 319         unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
 320                                                const struct cpumask *andmask);
 321
 322         /* ipi */
 323         void (*send_IPI_mask)(const struct cpumask *mask, int vector);
 324         void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
 325                                          int vector);
 326         void (*send_IPI_allbutself)(int vector);
 327         void (*send_IPI_all)(int vector);
 328         void (*send_IPI_self)(int vector);
 329
 330         /* wakeup_secondary_cpu */
 331         int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
 332
 333         int trampoline_phys_low;
 334         int trampoline_phys_high;
 335
 336         void (*wait_for_init_deassert)(atomic_t *deassert);
 337         void (*smp_callin_clear_local_apic)(void);
 338         void (*inquire_remote_apic)(int apicid);
 339
 340         /* apic ops */
 341         u32 (*read)(u32 reg);
 342         void (*write)(u32 reg, u32 v);
 343         u64 (*icr_read)(void);
 344         void (*icr_write)(u32 low, u32 high);
 345         void (*wait_icr_idle)(void);
 346         u32 (*safe_wait_icr_idle)(void);
 347 };
 348
 349 /*
 350  * Pointer to the local APIC driver in use on this system (there's
 351  * always just one such driver in use - the kernel decides via an
 352  * early probing process which one it picks - and then sticks to it):
 353  */
 354 extern struct apic *apic;
 355
 356 /*
 357  * APIC functionality to boot other CPUs - only used on SMP:
 358  */
 359 #ifdef CONFIG_SMP
 360 extern atomic_t init_deasserted;
 361 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
 362 #endif
 363
 364 static inline u32 apic_read(u32 reg)
 365 {
 366         return apic->read(reg);
 367 }
 368
 369 static inline void apic_write(u32 reg, u32 val)
 370 {
 371         apic->write(reg, val);
 372 }
 373
 374 static inline u64 apic_icr_read(void)
 375 {
 376         return apic->icr_read();
 377 }
 378
 379 static inline void apic_icr_write(u32 low, u32 high)
 380 {
 381         apic->icr_write(low, high);
 382 }
 383
 384 static inline void apic_wait_icr_idle(void)
 385 {
 386         apic->wait_icr_idle();
 387 }
 388
 389 static inline u32 safe_apic_wait_icr_idle(void)
 390 {
 391         return apic->safe_wait_icr_idle();
 392 }
 393
 394
 395 static inline void ack_APIC_irq(void)
 396 {
 397 #ifdef CONFIG_X86_LOCAL_APIC
 398         /*
 399          * ack_APIC_irq() actually gets compiled as a single instruction
 400          * ... yummie.
 401          */
 402
 403         /* Docs say use 0 for future compatibility */
 404         apic_write(APIC_EOI, 0);
 405 #endif
 406 }
 407
 408 static inline unsigned default_get_apic_id(unsigned long x)
 409 {
 410         unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
 411
 412         if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
 413                 return (x >> 24) & 0xFF;
 414         else
 415                 return (x >> 24) & 0x0F;
 416 }
 417
 418 /*
 419  * Warm reset vector default position:
 420  */
 421 #define DEFAULT_TRAMPOLINE_PHYS_LOW             0x467
 422 #define DEFAULT_TRAMPOLINE_PHYS_HIGH            0x469
 423
 424 #ifdef CONFIG_X86_64
 425 extern struct apic apic_flat;
 426 extern struct apic apic_physflat;
 427 extern struct apic apic_x2apic_cluster;
 428 extern struct apic apic_x2apic_phys;
 429 extern int default_acpi_madt_oem_check(char *, char *);
 430
 431 extern void apic_send_IPI_self(int vector);
 432
 433 extern struct apic apic_x2apic_uv_x;
 434 DECLARE_PER_CPU(int, x2apic_extra_bits);
 435
 436 extern int default_cpu_present_to_apicid(int mps_cpu);
 437 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 438 #endif
 439
 440 static inline void default_wait_for_init_deassert(atomic_t *deassert)
 441 {
 442         while (!atomic_read(deassert))
 443                 cpu_relax();
 444         return;
 445 }
 446
 447 extern void generic_bigsmp_probe(void);
 448
 449
 450 #ifdef CONFIG_X86_LOCAL_APIC
 451
 452 #include <asm/smp.h>
 453
 454 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
 455
 456 static inline const struct cpumask *default_target_cpus(void)
 457 {
 458 #ifdef CONFIG_SMP
 459         return cpu_online_mask;
 460 #else
 461         return cpumask_of(0);
 462 #endif
 463 }
 464
 465 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
 466
 467
 468 static inline unsigned int read_apic_id(void)
 469 {
 470         unsigned int reg;
 471
 472         reg = apic_read(APIC_ID);
 473
 474         return apic->get_apic_id(reg);
 475 }
 476
 477 extern void default_setup_apic_routing(void);
 478
 479 #ifdef CONFIG_X86_32
 480
 481 extern struct apic apic_default;
 482
 483 /*
 484  * Set up the logical destination ID.
 485  *
 486  * Intel recommends to set DFR, LDR and TPR before enabling
 487  * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
 488  * document number 292116).  So here it goes...
 489  */
 490 extern void default_init_apic_ldr(void);
 491
 492 static inline int default_apic_id_registered(void)
 493 {
 494         return physid_isset(read_apic_id(), phys_cpu_present_map);
 495 }
 496
 497 static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
 498 {
 499         return cpuid_apic >> index_msb;
 500 }
 501
 502 extern int default_apicid_to_node(int logical_apicid);
 503
 504 #endif
 505
 506 static inline unsigned int
 507 default_cpu_mask_to_apicid(const struct cpumask *cpumask)
 508 {
 509         return cpumask_bits(cpumask)[0] & APIC_ALL_CPUS;
 510 }
 511
 512 static inline unsigned int
 513 default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 514                                const struct cpumask *andmask)
 515 {
 516         unsigned long mask1 = cpumask_bits(cpumask)[0];
 517         unsigned long mask2 = cpumask_bits(andmask)[0];
 518         unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
 519
 520         return (unsigned int)(mask1 & mask2 & mask3);
 521 }
 522
 523 static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid)
 524 {
 525         return physid_isset(apicid, bitmap);
 526 }
 527
 528 static inline unsigned long default_check_apicid_present(int bit)
 529 {
 530         return physid_isset(bit, phys_cpu_present_map);
 531 }
 532
 533 static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map)
 534 {
 535         return phys_map;
 536 }
 537
 538 /* Mapping from cpu number to logical apicid */
 539 static inline int default_cpu_to_logical_apicid(int cpu)
 540 {
 541         return 1 << cpu;
 542 }
 543
 544 static inline int __default_cpu_present_to_apicid(int mps_cpu)
 545 {
 546         if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
 547                 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
 548         else
 549                 return BAD_APICID;
 550 }
 551
 552 static inline int
 553 __default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 554 {
 555         return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
 556 }
 557
 558 #ifdef CONFIG_X86_32
 559 static inline int default_cpu_present_to_apicid(int mps_cpu)
 560 {
 561         return __default_cpu_present_to_apicid(mps_cpu);
 562 }
 563
 564 static inline int
 565 default_check_phys_apicid_present(int boot_cpu_physical_apicid)
 566 {
 567         return __default_check_phys_apicid_present(boot_cpu_physical_apicid);
 568 }
 569 #else
 570 extern int default_cpu_present_to_apicid(int mps_cpu);
 571 extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid);
 572 #endif
 573
 574 static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid)
 575 {
 576         return physid_mask_of_physid(phys_apicid);
 577 }
 578
 579 #endif /* CONFIG_X86_LOCAL_APIC */
 580
 581 #ifdef CONFIG_X86_32
 582 extern u8 cpu_2_logical_apicid[NR_CPUS];
 583 #endif
 584
 585 #endif /* _ASM_X86_APIC_H */