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Merge tag 'm68knommu-for-v5.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / pci / controller / pci-aardvark.c
blob1559f79e63b6fa9be0446ac4b3f71244ffcb8f79
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
4 * 3700.
5 *
6 * Copyright (C) 2016 Marvell
7 *
8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
9 */
10
11 #include <linux/delay.h>
12 #include <linux/gpio.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/msi.h>
22 #include <linux/of_address.h>
23 #include <linux/of_gpio.h>
24 #include <linux/of_pci.h>
25
26 #include "../pci.h"
27 #include "../pci-bridge-emul.h"
28
29 /* PCIe core registers */
30 #define PCIE_CORE_DEV_ID_REG 0x0
31 #define PCIE_CORE_CMD_STATUS_REG 0x4
32 #define PCIE_CORE_CMD_IO_ACCESS_EN BIT(0)
33 #define PCIE_CORE_CMD_MEM_ACCESS_EN BIT(1)
34 #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2)
35 #define PCIE_CORE_DEV_REV_REG 0x8
36 #define PCIE_CORE_PCIEXP_CAP 0xc0
37 #define PCIE_CORE_ERR_CAPCTL_REG 0x118
38 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5)
39 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
40 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK BIT(7)
41 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV BIT(8)
42 #define PCIE_CORE_INT_A_ASSERT_ENABLE 1
43 #define PCIE_CORE_INT_B_ASSERT_ENABLE 2
44 #define PCIE_CORE_INT_C_ASSERT_ENABLE 3
45 #define PCIE_CORE_INT_D_ASSERT_ENABLE 4
46 /* PIO registers base address and register offsets */
47 #define PIO_BASE_ADDR 0x4000
48 #define PIO_CTRL (PIO_BASE_ADDR + 0x0)
49 #define PIO_CTRL_TYPE_MASK GENMASK(3, 0)
50 #define PIO_CTRL_ADDR_WIN_DISABLE BIT(24)
51 #define PIO_STAT (PIO_BASE_ADDR + 0x4)
52 #define PIO_COMPLETION_STATUS_SHIFT 7
53 #define PIO_COMPLETION_STATUS_MASK GENMASK(9, 7)
54 #define PIO_COMPLETION_STATUS_OK 0
55 #define PIO_COMPLETION_STATUS_UR 1
56 #define PIO_COMPLETION_STATUS_CRS 2
57 #define PIO_COMPLETION_STATUS_CA 4
58 #define PIO_NON_POSTED_REQ BIT(0)
59 #define PIO_ADDR_LS (PIO_BASE_ADDR + 0x8)
60 #define PIO_ADDR_MS (PIO_BASE_ADDR + 0xc)
61 #define PIO_WR_DATA (PIO_BASE_ADDR + 0x10)
62 #define PIO_WR_DATA_STRB (PIO_BASE_ADDR + 0x14)
63 #define PIO_RD_DATA (PIO_BASE_ADDR + 0x18)
64 #define PIO_START (PIO_BASE_ADDR + 0x1c)
65 #define PIO_ISR (PIO_BASE_ADDR + 0x20)
66 #define PIO_ISRM (PIO_BASE_ADDR + 0x24)
67
68 /* Aardvark Control registers */
69 #define CONTROL_BASE_ADDR 0x4800
70 #define PCIE_CORE_CTRL0_REG (CONTROL_BASE_ADDR + 0x0)
71 #define PCIE_GEN_SEL_MSK 0x3
72 #define PCIE_GEN_SEL_SHIFT 0x0
73 #define SPEED_GEN_1 0
74 #define SPEED_GEN_2 1
75 #define SPEED_GEN_3 2
76 #define IS_RC_MSK 1
77 #define IS_RC_SHIFT 2
78 #define LANE_CNT_MSK 0x18
79 #define LANE_CNT_SHIFT 0x3
80 #define LANE_COUNT_1 (0 << LANE_CNT_SHIFT)
81 #define LANE_COUNT_2 (1 << LANE_CNT_SHIFT)
82 #define LANE_COUNT_4 (2 << LANE_CNT_SHIFT)
83 #define LANE_COUNT_8 (3 << LANE_CNT_SHIFT)
84 #define LINK_TRAINING_EN BIT(6)
85 #define LEGACY_INTA BIT(28)
86 #define LEGACY_INTB BIT(29)
87 #define LEGACY_INTC BIT(30)
88 #define LEGACY_INTD BIT(31)
89 #define PCIE_CORE_CTRL1_REG (CONTROL_BASE_ADDR + 0x4)
90 #define HOT_RESET_GEN BIT(0)
91 #define PCIE_CORE_CTRL2_REG (CONTROL_BASE_ADDR + 0x8)
92 #define PCIE_CORE_CTRL2_RESERVED 0x7
93 #define PCIE_CORE_CTRL2_TD_ENABLE BIT(4)
94 #define PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
95 #define PCIE_CORE_CTRL2_OB_WIN_ENABLE BIT(6)
96 #define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
97 #define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
98 #define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
99 #define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
100 #define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
101 #define PCIE_MSG_PM_PME_MASK BIT(7)
102 #define PCIE_ISR0_MASK_REG (CONTROL_BASE_ADDR + 0x44)
103 #define PCIE_ISR0_MSI_INT_PENDING BIT(24)
104 #define PCIE_ISR0_INTX_ASSERT(val) BIT(16 + (val))
105 #define PCIE_ISR0_INTX_DEASSERT(val) BIT(20 + (val))
106 #define PCIE_ISR0_ALL_MASK GENMASK(26, 0)
107 #define PCIE_ISR1_REG (CONTROL_BASE_ADDR + 0x48)
108 #define PCIE_ISR1_MASK_REG (CONTROL_BASE_ADDR + 0x4C)
109 #define PCIE_ISR1_POWER_STATE_CHANGE BIT(4)
110 #define PCIE_ISR1_FLUSH BIT(5)
111 #define PCIE_ISR1_INTX_ASSERT(val) BIT(8 + (val))
112 #define PCIE_ISR1_ALL_MASK GENMASK(11, 4)
113 #define PCIE_MSI_ADDR_LOW_REG (CONTROL_BASE_ADDR + 0x50)
114 #define PCIE_MSI_ADDR_HIGH_REG (CONTROL_BASE_ADDR + 0x54)
115 #define PCIE_MSI_STATUS_REG (CONTROL_BASE_ADDR + 0x58)
116 #define PCIE_MSI_MASK_REG (CONTROL_BASE_ADDR + 0x5C)
117 #define PCIE_MSI_PAYLOAD_REG (CONTROL_BASE_ADDR + 0x9C)
118
119 /* LMI registers base address and register offsets */
120 #define LMI_BASE_ADDR 0x6000
121 #define CFG_REG (LMI_BASE_ADDR + 0x0)
122 #define LTSSM_SHIFT 24
123 #define LTSSM_MASK 0x3f
124 #define LTSSM_L0 0x10
125 #define RC_BAR_CONFIG 0x300
126
127 /* PCIe core controller registers */
128 #define CTRL_CORE_BASE_ADDR 0x18000
129 #define CTRL_CONFIG_REG (CTRL_CORE_BASE_ADDR + 0x0)
130 #define CTRL_MODE_SHIFT 0x0
131 #define CTRL_MODE_MASK 0x1
132 #define PCIE_CORE_MODE_DIRECT 0x0
133 #define PCIE_CORE_MODE_COMMAND 0x1
134
135 /* PCIe Central Interrupts Registers */
136 #define CENTRAL_INT_BASE_ADDR 0x1b000
137 #define HOST_CTRL_INT_STATUS_REG (CENTRAL_INT_BASE_ADDR + 0x0)
138 #define HOST_CTRL_INT_MASK_REG (CENTRAL_INT_BASE_ADDR + 0x4)
139 #define PCIE_IRQ_CMDQ_INT BIT(0)
140 #define PCIE_IRQ_MSI_STATUS_INT BIT(1)
141 #define PCIE_IRQ_CMD_SENT_DONE BIT(3)
142 #define PCIE_IRQ_DMA_INT BIT(4)
143 #define PCIE_IRQ_IB_DXFERDONE BIT(5)
144 #define PCIE_IRQ_OB_DXFERDONE BIT(6)
145 #define PCIE_IRQ_OB_RXFERDONE BIT(7)
146 #define PCIE_IRQ_COMPQ_INT BIT(12)
147 #define PCIE_IRQ_DIR_RD_DDR_DET BIT(13)
148 #define PCIE_IRQ_DIR_WR_DDR_DET BIT(14)
149 #define PCIE_IRQ_CORE_INT BIT(16)
150 #define PCIE_IRQ_CORE_INT_PIO BIT(17)
151 #define PCIE_IRQ_DPMU_INT BIT(18)
152 #define PCIE_IRQ_PCIE_MIS_INT BIT(19)
153 #define PCIE_IRQ_MSI_INT1_DET BIT(20)
154 #define PCIE_IRQ_MSI_INT2_DET BIT(21)
155 #define PCIE_IRQ_RC_DBELL_DET BIT(22)
156 #define PCIE_IRQ_EP_STATUS BIT(23)
157 #define PCIE_IRQ_ALL_MASK 0xfff0fb
158 #define PCIE_IRQ_ENABLE_INTS_MASK PCIE_IRQ_CORE_INT
159
160 /* Transaction types */
161 #define PCIE_CONFIG_RD_TYPE0 0x8
162 #define PCIE_CONFIG_RD_TYPE1 0x9
163 #define PCIE_CONFIG_WR_TYPE0 0xa
164 #define PCIE_CONFIG_WR_TYPE1 0xb
165
166 #define PCIE_CONF_BUS(bus) (((bus) & 0xff) << 20)
167 #define PCIE_CONF_DEV(dev) (((dev) & 0x1f) << 15)
168 #define PCIE_CONF_FUNC(fun) (((fun) & 0x7) << 12)
169 #define PCIE_CONF_REG(reg) ((reg) & 0xffc)
170 #define PCIE_CONF_ADDR(bus, devfn, where) \
171 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
172 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
173
174 #define PIO_RETRY_CNT 500
175 #define PIO_RETRY_DELAY 2 /* 2 us*/
176
177 #define LINK_WAIT_MAX_RETRIES 10
178 #define LINK_WAIT_USLEEP_MIN 90000
179 #define LINK_WAIT_USLEEP_MAX 100000
180 #define RETRAIN_WAIT_MAX_RETRIES 10
181 #define RETRAIN_WAIT_USLEEP_US 2000
182
183 #define MSI_IRQ_NUM 32
184
185 struct advk_pcie {
186 struct platform_device *pdev;
187 void __iomem *base;
188 struct irq_domain *irq_domain;
189 struct irq_chip irq_chip;
190 struct irq_domain *msi_domain;
191 struct irq_domain *msi_inner_domain;
192 struct irq_chip msi_bottom_irq_chip;
193 struct irq_chip msi_irq_chip;
194 struct msi_domain_info msi_domain_info;
195 DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
196 struct mutex msi_used_lock;
197 u16 msi_msg;
198 int link_gen;
199 struct pci_bridge_emul bridge;
200 struct gpio_desc *reset_gpio;
201 struct phy *phy;
202 };
203
204 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
205 {
206 writel(val, pcie->base + reg);
207 }
208
209 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
210 {
211 return readl(pcie->base + reg);
212 }
213
214 static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg)
215 {
216 return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8);
217 }
218
219 static int advk_pcie_link_up(struct advk_pcie *pcie)
220 {
221 u32 val, ltssm_state;
222
223 val = advk_readl(pcie, CFG_REG);
224 ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
225 return ltssm_state >= LTSSM_L0;
226 }
227
228 static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
229 {
230 int retries;
231
232 /* check if the link is up or not */
233 for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
234 if (advk_pcie_link_up(pcie))
235 return 0;
236
237 usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
238 }
239
240 return -ETIMEDOUT;
241 }
242
243 static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
244 {
245 size_t retries;
246
247 for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
248 if (!advk_pcie_link_up(pcie))
249 break;
250 udelay(RETRAIN_WAIT_USLEEP_US);
251 }
252 }
253
254 static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen)
255 {
256 int ret, neg_gen;
257 u32 reg;
258
259 /* Setup link speed */
260 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
261 reg &= ~PCIE_GEN_SEL_MSK;
262 if (gen == 3)
263 reg |= SPEED_GEN_3;
264 else if (gen == 2)
265 reg |= SPEED_GEN_2;
266 else
267 reg |= SPEED_GEN_1;
268 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
269
270 /*
271 * Enable link training. This is not needed in every call to this
272 * function, just once suffices, but it does not break anything either.
273 */
274 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
275 reg |= LINK_TRAINING_EN;
276 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
277
278 /*
279 * Start link training immediately after enabling it.
280 * This solves problems for some buggy cards.
281 */
282 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
283 reg |= PCI_EXP_LNKCTL_RL;
284 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
285
286 ret = advk_pcie_wait_for_link(pcie);
287 if (ret)
288 return ret;
289
290 reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA);
291 neg_gen = reg & PCI_EXP_LNKSTA_CLS;
292
293 return neg_gen;
294 }
295
296 static void advk_pcie_train_link(struct advk_pcie *pcie)
297 {
298 struct device *dev = &pcie->pdev->dev;
299 int neg_gen = -1, gen;
300
301 /*
302 * Try link training at link gen specified by device tree property
303 * 'max-link-speed'. If this fails, iteratively train at lower gen.
304 */
305 for (gen = pcie->link_gen; gen > 0; --gen) {
306 neg_gen = advk_pcie_train_at_gen(pcie, gen);
307 if (neg_gen > 0)
308 break;
309 }
310
311 if (neg_gen < 0)
312 goto err;
313
314 /*
315 * After successful training if negotiated gen is lower than requested,
316 * train again on negotiated gen. This solves some stability issues for
317 * some buggy gen1 cards.
318 */
319 if (neg_gen < gen) {
320 gen = neg_gen;
321 neg_gen = advk_pcie_train_at_gen(pcie, gen);
322 }
323
324 if (neg_gen == gen) {
325 dev_info(dev, "link up at gen %i\n", gen);
326 return;
327 }
328
329 err:
330 dev_err(dev, "link never came up\n");
331 }
332
333 static void advk_pcie_issue_perst(struct advk_pcie *pcie)
334 {
335 u32 reg;
336
337 if (!pcie->reset_gpio)
338 return;
339
340 /* PERST does not work for some cards when link training is enabled */
341 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
342 reg &= ~LINK_TRAINING_EN;
343 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
344
345 /* 10ms delay is needed for some cards */
346 dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
347 gpiod_set_value_cansleep(pcie->reset_gpio, 1);
348 usleep_range(10000, 11000);
349 gpiod_set_value_cansleep(pcie->reset_gpio, 0);
350 }
351
352 static void advk_pcie_setup_hw(struct advk_pcie *pcie)
353 {
354 u32 reg;
355
356 advk_pcie_issue_perst(pcie);
357
358 /* Enable TX */
359 reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
360 reg |= PCIE_CORE_REF_CLK_TX_ENABLE;
361 advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
362
363 /* Set to Direct mode */
364 reg = advk_readl(pcie, CTRL_CONFIG_REG);
365 reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
366 reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
367 advk_writel(pcie, reg, CTRL_CONFIG_REG);
368
369 /* Set PCI global control register to RC mode */
370 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
371 reg |= (IS_RC_MSK << IS_RC_SHIFT);
372 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
373
374 /* Set Advanced Error Capabilities and Control PF0 register */
375 reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
376 PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
377 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
378 PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
379 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
380
381 /* Set PCIe Device Control register */
382 reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
383 reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
384 reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
385 reg &= ~PCI_EXP_DEVCTL_READRQ;
386 reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */
387 reg |= PCI_EXP_DEVCTL_READRQ_512B;
388 advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
389
390 /* Program PCIe Control 2 to disable strict ordering */
391 reg = PCIE_CORE_CTRL2_RESERVED |
392 PCIE_CORE_CTRL2_TD_ENABLE;
393 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
394
395 /* Set lane X1 */
396 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
397 reg &= ~LANE_CNT_MSK;
398 reg |= LANE_COUNT_1;
399 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
400
401 /* Enable MSI */
402 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
403 reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
404 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
405
406 /* Clear all interrupts */
407 advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
408 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
409 advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
410
411 /* Disable All ISR0/1 Sources */
412 reg = PCIE_ISR0_ALL_MASK;
413 reg &= ~PCIE_ISR0_MSI_INT_PENDING;
414 advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
415
416 advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
417
418 /* Unmask all MSIs */
419 advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
420
421 /* Enable summary interrupt for GIC SPI source */
422 reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
423 advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
424
425 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
426 reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
427 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
428
429 /* Bypass the address window mapping for PIO */
430 reg = advk_readl(pcie, PIO_CTRL);
431 reg |= PIO_CTRL_ADDR_WIN_DISABLE;
432 advk_writel(pcie, reg, PIO_CTRL);
433
434 /*
435 * PERST# signal could have been asserted by pinctrl subsystem before
436 * probe() callback has been called or issued explicitly by reset gpio
437 * function advk_pcie_issue_perst(), making the endpoint going into
438 * fundamental reset. As required by PCI Express spec a delay for at
439 * least 100ms after such a reset before link training is needed.
440 */
441 msleep(PCI_PM_D3COLD_WAIT);
442
443 advk_pcie_train_link(pcie);
444
445 /*
446 * FIXME: The following register update is suspicious. This register is
447 * applicable only when the PCI controller is configured for Endpoint
448 * mode, not as a Root Complex. But apparently when this code is
449 * removed, some cards stop working. This should be investigated and
450 * a comment explaining this should be put here.
451 */
452 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
453 reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
454 PCIE_CORE_CMD_IO_ACCESS_EN |
455 PCIE_CORE_CMD_MEM_IO_REQ_EN;
456 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
457 }
458
459 static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
460 {
461 struct device *dev = &pcie->pdev->dev;
462 u32 reg;
463 unsigned int status;
464 char *strcomp_status, *str_posted;
465
466 reg = advk_readl(pcie, PIO_STAT);
467 status = (reg & PIO_COMPLETION_STATUS_MASK) >>
468 PIO_COMPLETION_STATUS_SHIFT;
469
470 if (!status)
471 return;
472
473 switch (status) {
474 case PIO_COMPLETION_STATUS_UR:
475 strcomp_status = "UR";
476 break;
477 case PIO_COMPLETION_STATUS_CRS:
478 strcomp_status = "CRS";
479 break;
480 case PIO_COMPLETION_STATUS_CA:
481 strcomp_status = "CA";
482 break;
483 default:
484 strcomp_status = "Unknown";
485 break;
486 }
487
488 if (reg & PIO_NON_POSTED_REQ)
489 str_posted = "Non-posted";
490 else
491 str_posted = "Posted";
492
493 dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
494 str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
495 }
496
497 static int advk_pcie_wait_pio(struct advk_pcie *pcie)
498 {
499 struct device *dev = &pcie->pdev->dev;
500 int i;
501
502 for (i = 0; i < PIO_RETRY_CNT; i++) {
503 u32 start, isr;
504
505 start = advk_readl(pcie, PIO_START);
506 isr = advk_readl(pcie, PIO_ISR);
507 if (!start && isr)
508 return 0;
509 udelay(PIO_RETRY_DELAY);
510 }
511
512 dev_err(dev, "config read/write timed out\n");
513 return -ETIMEDOUT;
514 }
515
516
517 static pci_bridge_emul_read_status_t
518 advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
519 int reg, u32 *value)
520 {
521 struct advk_pcie *pcie = bridge->data;
522
523
524 switch (reg) {
525 case PCI_EXP_SLTCTL:
526 *value = PCI_EXP_SLTSTA_PDS << 16;
527 return PCI_BRIDGE_EMUL_HANDLED;
528
529 case PCI_EXP_RTCTL: {
530 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
531 *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
532 return PCI_BRIDGE_EMUL_HANDLED;
533 }
534
535 case PCI_EXP_RTSTA: {
536 u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
537 u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
538 *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16);
539 return PCI_BRIDGE_EMUL_HANDLED;
540 }
541
542 case PCI_EXP_LNKCTL: {
543 /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
544 u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
545 ~(PCI_EXP_LNKSTA_LT << 16);
546 if (!advk_pcie_link_up(pcie))
547 val |= (PCI_EXP_LNKSTA_LT << 16);
548 *value = val;
549 return PCI_BRIDGE_EMUL_HANDLED;
550 }
551
552 case PCI_CAP_LIST_ID:
553 case PCI_EXP_DEVCAP:
554 case PCI_EXP_DEVCTL:
555 case PCI_EXP_LNKCAP:
556 *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
557 return PCI_BRIDGE_EMUL_HANDLED;
558 default:
559 return PCI_BRIDGE_EMUL_NOT_HANDLED;
560 }
561
562 }
563
564 static void
565 advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
566 int reg, u32 old, u32 new, u32 mask)
567 {
568 struct advk_pcie *pcie = bridge->data;
569
570 switch (reg) {
571 case PCI_EXP_DEVCTL:
572 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
573 break;
574
575 case PCI_EXP_LNKCTL:
576 advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
577 if (new & PCI_EXP_LNKCTL_RL)
578 advk_pcie_wait_for_retrain(pcie);
579 break;
580
581 case PCI_EXP_RTCTL: {
582 /* Only mask/unmask PME interrupt */
583 u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
584 ~PCIE_MSG_PM_PME_MASK;
585 if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
586 val |= PCIE_MSG_PM_PME_MASK;
587 advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
588 break;
589 }
590
591 case PCI_EXP_RTSTA:
592 new = (new & PCI_EXP_RTSTA_PME) >> 9;
593 advk_writel(pcie, new, PCIE_ISR0_REG);
594 break;
595
596 default:
597 break;
598 }
599 }
600
601 static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
602 .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
603 .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
604 };
605
606 /*
607 * Initialize the configuration space of the PCI-to-PCI bridge
608 * associated with the given PCIe interface.
609 */
610 static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
611 {
612 struct pci_bridge_emul *bridge = &pcie->bridge;
613
614 bridge->conf.vendor =
615 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
616 bridge->conf.device =
617 cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
618 bridge->conf.class_revision =
619 cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
620
621 /* Support 32 bits I/O addressing */
622 bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
623 bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
624
625 /* Support 64 bits memory pref */
626 bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
627 bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
628
629 /* Support interrupt A for MSI feature */
630 bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
631
632 bridge->has_pcie = true;
633 bridge->data = pcie;
634 bridge->ops = &advk_pci_bridge_emul_ops;
635
636 pci_bridge_emul_init(bridge, 0);
637
638 }
639
640 static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
641 int devfn)
642 {
643 if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0)
644 return false;
645
646 /*
647 * If the link goes down after we check for link-up, nothing bad
648 * happens but the config access times out.
649 */
650 if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))
651 return false;
652
653 return true;
654 }
655
656 static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
657 int where, int size, u32 *val)
658 {
659 struct advk_pcie *pcie = bus->sysdata;
660 u32 reg;
661 int ret;
662
663 if (!advk_pcie_valid_device(pcie, bus, devfn)) {
664 *val = 0xffffffff;
665 return PCIBIOS_DEVICE_NOT_FOUND;
666 }
667
668 if (pci_is_root_bus(bus))
669 return pci_bridge_emul_conf_read(&pcie->bridge, where,
670 size, val);
671
672 /* Start PIO */
673 advk_writel(pcie, 0, PIO_START);
674 advk_writel(pcie, 1, PIO_ISR);
675
676 /* Program the control register */
677 reg = advk_readl(pcie, PIO_CTRL);
678 reg &= ~PIO_CTRL_TYPE_MASK;
679 if (pci_is_root_bus(bus->parent))
680 reg |= PCIE_CONFIG_RD_TYPE0;
681 else
682 reg |= PCIE_CONFIG_RD_TYPE1;
683 advk_writel(pcie, reg, PIO_CTRL);
684
685 /* Program the address registers */
686 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
687 advk_writel(pcie, reg, PIO_ADDR_LS);
688 advk_writel(pcie, 0, PIO_ADDR_MS);
689
690 /* Program the data strobe */
691 advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
692
693 /* Start the transfer */
694 advk_writel(pcie, 1, PIO_START);
695
696 ret = advk_pcie_wait_pio(pcie);
697 if (ret < 0) {
698 *val = 0xffffffff;
699 return PCIBIOS_SET_FAILED;
700 }
701
702 advk_pcie_check_pio_status(pcie);
703
704 /* Get the read result */
705 *val = advk_readl(pcie, PIO_RD_DATA);
706 if (size == 1)
707 *val = (*val >> (8 * (where & 3))) & 0xff;
708 else if (size == 2)
709 *val = (*val >> (8 * (where & 3))) & 0xffff;
710
711 return PCIBIOS_SUCCESSFUL;
712 }
713
714 static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
715 int where, int size, u32 val)
716 {
717 struct advk_pcie *pcie = bus->sysdata;
718 u32 reg;
719 u32 data_strobe = 0x0;
720 int offset;
721 int ret;
722
723 if (!advk_pcie_valid_device(pcie, bus, devfn))
724 return PCIBIOS_DEVICE_NOT_FOUND;
725
726 if (pci_is_root_bus(bus))
727 return pci_bridge_emul_conf_write(&pcie->bridge, where,
728 size, val);
729
730 if (where % size)
731 return PCIBIOS_SET_FAILED;
732
733 /* Start PIO */
734 advk_writel(pcie, 0, PIO_START);
735 advk_writel(pcie, 1, PIO_ISR);
736
737 /* Program the control register */
738 reg = advk_readl(pcie, PIO_CTRL);
739 reg &= ~PIO_CTRL_TYPE_MASK;
740 if (pci_is_root_bus(bus->parent))
741 reg |= PCIE_CONFIG_WR_TYPE0;
742 else
743 reg |= PCIE_CONFIG_WR_TYPE1;
744 advk_writel(pcie, reg, PIO_CTRL);
745
746 /* Program the address registers */
747 reg = PCIE_CONF_ADDR(bus->number, devfn, where);
748 advk_writel(pcie, reg, PIO_ADDR_LS);
749 advk_writel(pcie, 0, PIO_ADDR_MS);
750
751 /* Calculate the write strobe */
752 offset = where & 0x3;
753 reg = val << (8 * offset);
754 data_strobe = GENMASK(size - 1, 0) << offset;
755
756 /* Program the data register */
757 advk_writel(pcie, reg, PIO_WR_DATA);
758
759 /* Program the data strobe */
760 advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
761
762 /* Start the transfer */
763 advk_writel(pcie, 1, PIO_START);
764
765 ret = advk_pcie_wait_pio(pcie);
766 if (ret < 0)
767 return PCIBIOS_SET_FAILED;
768
769 advk_pcie_check_pio_status(pcie);
770
771 return PCIBIOS_SUCCESSFUL;
772 }
773
774 static struct pci_ops advk_pcie_ops = {
775 .read = advk_pcie_rd_conf,
776 .write = advk_pcie_wr_conf,
777 };
778
779 static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
780 struct msi_msg *msg)
781 {
782 struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
783 phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
784
785 msg->address_lo = lower_32_bits(msi_msg);
786 msg->address_hi = upper_32_bits(msi_msg);
787 msg->data = data->irq;
788 }
789
790 static int advk_msi_set_affinity(struct irq_data *irq_data,
791 const struct cpumask *mask, bool force)
792 {
793 return -EINVAL;
794 }
795
796 static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
797 unsigned int virq,
798 unsigned int nr_irqs, void *args)
799 {
800 struct advk_pcie *pcie = domain->host_data;
801 int hwirq, i;
802
803 mutex_lock(&pcie->msi_used_lock);
804 hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
805 0, nr_irqs, 0);
806 if (hwirq >= MSI_IRQ_NUM) {
807 mutex_unlock(&pcie->msi_used_lock);
808 return -ENOSPC;
809 }
810
811 bitmap_set(pcie->msi_used, hwirq, nr_irqs);
812 mutex_unlock(&pcie->msi_used_lock);
813
814 for (i = 0; i < nr_irqs; i++)
815 irq_domain_set_info(domain, virq + i, hwirq + i,
816 &pcie->msi_bottom_irq_chip,
817 domain->host_data, handle_simple_irq,
818 NULL, NULL);
819
820 return hwirq;
821 }
822
823 static void advk_msi_irq_domain_free(struct irq_domain *domain,
824 unsigned int virq, unsigned int nr_irqs)
825 {
826 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
827 struct advk_pcie *pcie = domain->host_data;
828
829 mutex_lock(&pcie->msi_used_lock);
830 bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
831 mutex_unlock(&pcie->msi_used_lock);
832 }
833
834 static const struct irq_domain_ops advk_msi_domain_ops = {
835 .alloc = advk_msi_irq_domain_alloc,
836 .free = advk_msi_irq_domain_free,
837 };
838
839 static void advk_pcie_irq_mask(struct irq_data *d)
840 {
841 struct advk_pcie *pcie = d->domain->host_data;
842 irq_hw_number_t hwirq = irqd_to_hwirq(d);
843 u32 mask;
844
845 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
846 mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
847 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
848 }
849
850 static void advk_pcie_irq_unmask(struct irq_data *d)
851 {
852 struct advk_pcie *pcie = d->domain->host_data;
853 irq_hw_number_t hwirq = irqd_to_hwirq(d);
854 u32 mask;
855
856 mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
857 mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
858 advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
859 }
860
861 static int advk_pcie_irq_map(struct irq_domain *h,
862 unsigned int virq, irq_hw_number_t hwirq)
863 {
864 struct advk_pcie *pcie = h->host_data;
865
866 advk_pcie_irq_mask(irq_get_irq_data(virq));
867 irq_set_status_flags(virq, IRQ_LEVEL);
868 irq_set_chip_and_handler(virq, &pcie->irq_chip,
869 handle_level_irq);
870 irq_set_chip_data(virq, pcie);
871
872 return 0;
873 }
874
875 static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
876 .map = advk_pcie_irq_map,
877 .xlate = irq_domain_xlate_onecell,
878 };
879
880 static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
881 {
882 struct device *dev = &pcie->pdev->dev;
883 struct device_node *node = dev->of_node;
884 struct irq_chip *bottom_ic, *msi_ic;
885 struct msi_domain_info *msi_di;
886 phys_addr_t msi_msg_phys;
887
888 mutex_init(&pcie->msi_used_lock);
889
890 bottom_ic = &pcie->msi_bottom_irq_chip;
891
892 bottom_ic->name = "MSI";
893 bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
894 bottom_ic->irq_set_affinity = advk_msi_set_affinity;
895
896 msi_ic = &pcie->msi_irq_chip;
897 msi_ic->name = "advk-MSI";
898
899 msi_di = &pcie->msi_domain_info;
900 msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
901 MSI_FLAG_MULTI_PCI_MSI;
902 msi_di->chip = msi_ic;
903
904 msi_msg_phys = virt_to_phys(&pcie->msi_msg);
905
906 advk_writel(pcie, lower_32_bits(msi_msg_phys),
907 PCIE_MSI_ADDR_LOW_REG);
908 advk_writel(pcie, upper_32_bits(msi_msg_phys),
909 PCIE_MSI_ADDR_HIGH_REG);
910
911 pcie->msi_inner_domain =
912 irq_domain_add_linear(NULL, MSI_IRQ_NUM,
913 &advk_msi_domain_ops, pcie);
914 if (!pcie->msi_inner_domain)
915 return -ENOMEM;
916
917 pcie->msi_domain =
918 pci_msi_create_irq_domain(of_node_to_fwnode(node),
919 msi_di, pcie->msi_inner_domain);
920 if (!pcie->msi_domain) {
921 irq_domain_remove(pcie->msi_inner_domain);
922 return -ENOMEM;
923 }
924
925 return 0;
926 }
927
928 static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
929 {
930 irq_domain_remove(pcie->msi_domain);
931 irq_domain_remove(pcie->msi_inner_domain);
932 }
933
934 static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
935 {
936 struct device *dev = &pcie->pdev->dev;
937 struct device_node *node = dev->of_node;
938 struct device_node *pcie_intc_node;
939 struct irq_chip *irq_chip;
940 int ret = 0;
941
942 pcie_intc_node = of_get_next_child(node, NULL);
943 if (!pcie_intc_node) {
944 dev_err(dev, "No PCIe Intc node found\n");
945 return -ENODEV;
946 }
947
948 irq_chip = &pcie->irq_chip;
949
950 irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
951 dev_name(dev));
952 if (!irq_chip->name) {
953 ret = -ENOMEM;
954 goto out_put_node;
955 }
956
957 irq_chip->irq_mask = advk_pcie_irq_mask;
958 irq_chip->irq_mask_ack = advk_pcie_irq_mask;
959 irq_chip->irq_unmask = advk_pcie_irq_unmask;
960
961 pcie->irq_domain =
962 irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
963 &advk_pcie_irq_domain_ops, pcie);
964 if (!pcie->irq_domain) {
965 dev_err(dev, "Failed to get a INTx IRQ domain\n");
966 ret = -ENOMEM;
967 goto out_put_node;
968 }
969
970 out_put_node:
971 of_node_put(pcie_intc_node);
972 return ret;
973 }
974
975 static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
976 {
977 irq_domain_remove(pcie->irq_domain);
978 }
979
980 static void advk_pcie_handle_msi(struct advk_pcie *pcie)
981 {
982 u32 msi_val, msi_mask, msi_status, msi_idx;
983 u16 msi_data;
984
985 msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
986 msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
987 msi_status = msi_val & ~msi_mask;
988
989 for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
990 if (!(BIT(msi_idx) & msi_status))
991 continue;
992
993 advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
994 msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
995 generic_handle_irq(msi_data);
996 }
997
998 advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
999 PCIE_ISR0_REG);
1000 }
1001
1002 static void advk_pcie_handle_int(struct advk_pcie *pcie)
1003 {
1004 u32 isr0_val, isr0_mask, isr0_status;
1005 u32 isr1_val, isr1_mask, isr1_status;
1006 int i, virq;
1007
1008 isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
1009 isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1010 isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
1011
1012 isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
1013 isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1014 isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
1015
1016 if (!isr0_status && !isr1_status) {
1017 advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
1018 advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
1019 return;
1020 }
1021
1022 /* Process MSI interrupts */
1023 if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
1024 advk_pcie_handle_msi(pcie);
1025
1026 /* Process legacy interrupts */
1027 for (i = 0; i < PCI_NUM_INTX; i++) {
1028 if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
1029 continue;
1030
1031 advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1032 PCIE_ISR1_REG);
1033
1034 virq = irq_find_mapping(pcie->irq_domain, i);
1035 generic_handle_irq(virq);
1036 }
1037 }
1038
1039 static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
1040 {
1041 struct advk_pcie *pcie = arg;
1042 u32 status;
1043
1044 status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
1045 if (!(status & PCIE_IRQ_CORE_INT))
1046 return IRQ_NONE;
1047
1048 advk_pcie_handle_int(pcie);
1049
1050 /* Clear interrupt */
1051 advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
1052
1053 return IRQ_HANDLED;
1054 }
1055
1056 static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
1057 {
1058 phy_power_off(pcie->phy);
1059 phy_exit(pcie->phy);
1060 }
1061
1062 static int advk_pcie_enable_phy(struct advk_pcie *pcie)
1063 {
1064 int ret;
1065
1066 if (!pcie->phy)
1067 return 0;
1068
1069 ret = phy_init(pcie->phy);
1070 if (ret)
1071 return ret;
1072
1073 ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
1074 if (ret) {
1075 phy_exit(pcie->phy);
1076 return ret;
1077 }
1078
1079 ret = phy_power_on(pcie->phy);
1080 if (ret) {
1081 phy_exit(pcie->phy);
1082 return ret;
1083 }
1084
1085 return 0;
1086 }
1087
1088 static int advk_pcie_setup_phy(struct advk_pcie *pcie)
1089 {
1090 struct device *dev = &pcie->pdev->dev;
1091 struct device_node *node = dev->of_node;
1092 int ret = 0;
1093
1094 pcie->phy = devm_of_phy_get(dev, node, NULL);
1095 if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER))
1096 return PTR_ERR(pcie->phy);
1097
1098 /* Old bindings miss the PHY handle */
1099 if (IS_ERR(pcie->phy)) {
1100 dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
1101 pcie->phy = NULL;
1102 return 0;
1103 }
1104
1105 ret = advk_pcie_enable_phy(pcie);
1106 if (ret)
1107 dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
1108
1109 return ret;
1110 }
1111
1112 static int advk_pcie_probe(struct platform_device *pdev)
1113 {
1114 struct device *dev = &pdev->dev;
1115 struct advk_pcie *pcie;
1116 struct pci_host_bridge *bridge;
1117 int ret, irq;
1118
1119 bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
1120 if (!bridge)
1121 return -ENOMEM;
1122
1123 pcie = pci_host_bridge_priv(bridge);
1124 pcie->pdev = pdev;
1125
1126 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1127 if (IS_ERR(pcie->base))
1128 return PTR_ERR(pcie->base);
1129
1130 irq = platform_get_irq(pdev, 0);
1131 if (irq < 0)
1132 return irq;
1133
1134 ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
1135 IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
1136 pcie);
1137 if (ret) {
1138 dev_err(dev, "Failed to register interrupt\n");
1139 return ret;
1140 }
1141
1142 pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
1143 "reset-gpios", 0,
1144 GPIOD_OUT_LOW,
1145 "pcie1-reset");
1146 ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
1147 if (ret) {
1148 if (ret == -ENOENT) {
1149 pcie->reset_gpio = NULL;
1150 } else {
1151 if (ret != -EPROBE_DEFER)
1152 dev_err(dev, "Failed to get reset-gpio: %i\n",
1153 ret);
1154 return ret;
1155 }
1156 }
1157
1158 ret = of_pci_get_max_link_speed(dev->of_node);
1159 if (ret <= 0 || ret > 3)
1160 pcie->link_gen = 3;
1161 else
1162 pcie->link_gen = ret;
1163
1164 ret = advk_pcie_setup_phy(pcie);
1165 if (ret)
1166 return ret;
1167
1168 advk_pcie_setup_hw(pcie);
1169
1170 advk_sw_pci_bridge_init(pcie);
1171
1172 ret = advk_pcie_init_irq_domain(pcie);
1173 if (ret) {
1174 dev_err(dev, "Failed to initialize irq\n");
1175 return ret;
1176 }
1177
1178 ret = advk_pcie_init_msi_irq_domain(pcie);
1179 if (ret) {
1180 dev_err(dev, "Failed to initialize irq\n");
1181 advk_pcie_remove_irq_domain(pcie);
1182 return ret;
1183 }
1184
1185 bridge->sysdata = pcie;
1186 bridge->ops = &advk_pcie_ops;
1187
1188 ret = pci_host_probe(bridge);
1189 if (ret < 0) {
1190 advk_pcie_remove_msi_irq_domain(pcie);
1191 advk_pcie_remove_irq_domain(pcie);
1192 return ret;
1193 }
1194
1195 return 0;
1196 }
1197
1198 static const struct of_device_id advk_pcie_of_match_table[] = {
1199 { .compatible = "marvell,armada-3700-pcie", },
1200 {},
1201 };
1202
1203 static struct platform_driver advk_pcie_driver = {
1204 .driver = {
1205 .name = "advk-pcie",
1206 .of_match_table = advk_pcie_of_match_table,
1207 /* Driver unloading/unbinding currently not supported */
1208 .suppress_bind_attrs = true,
1209 },
1210 .probe = advk_pcie_probe,
1211 };
1212 builtin_platform_driver(advk_pcie_driver);
Linux with added FPC-III support