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Merge tag 'm68knommu-for-v5.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux/fpc-iii.git] / drivers / pci / controller / pcie-rockchip-ep.c
blob7631dc3961c1281bf1ca5b9374e332fbd101d1e9
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Rockchip AXI PCIe endpoint controller driver
4 *
5 * Copyright (c) 2018 Rockchip, Inc.
6 *
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Simon Xue <xxm@rock-chips.com>
9 */
10
11 #include <linux/configfs.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/of.h>
15 #include <linux/pci-epc.h>
16 #include <linux/platform_device.h>
17 #include <linux/pci-epf.h>
18 #include <linux/sizes.h>
19
20 #include "pcie-rockchip.h"
21
22 /**
23 * struct rockchip_pcie_ep - private data for PCIe endpoint controller driver
24 * @rockchip: Rockchip PCIe controller
25 * @epc: PCI EPC device
26 * @max_regions: maximum number of regions supported by hardware
27 * @ob_region_map: bitmask of mapped outbound regions
28 * @ob_addr: base addresses in the AXI bus where the outbound regions start
29 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
30 * dedicated outbound regions is mapped.
31 * @irq_cpu_addr: base address in the CPU space where a write access triggers
32 * the sending of a memory write (MSI) / normal message (legacy
33 * IRQ) TLP through the PCIe bus.
34 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
35 * dedicated outbound region.
36 * @irq_pci_fn: the latest PCI function that has updated the mapping of
37 * the MSI/legacy IRQ dedicated outbound region.
38 * @irq_pending: bitmask of asserted legacy IRQs.
39 */
40 struct rockchip_pcie_ep {
41 struct rockchip_pcie rockchip;
42 struct pci_epc *epc;
43 u32 max_regions;
44 unsigned long ob_region_map;
45 phys_addr_t *ob_addr;
46 phys_addr_t irq_phys_addr;
47 void __iomem *irq_cpu_addr;
48 u64 irq_pci_addr;
49 u8 irq_pci_fn;
50 u8 irq_pending;
51 };
52
53 static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
54 u32 region)
55 {
56 rockchip_pcie_write(rockchip, 0,
57 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(region));
58 rockchip_pcie_write(rockchip, 0,
59 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(region));
60 rockchip_pcie_write(rockchip, 0,
61 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
62 rockchip_pcie_write(rockchip, 0,
63 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
64 rockchip_pcie_write(rockchip, 0,
65 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region));
66 rockchip_pcie_write(rockchip, 0,
67 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region));
68 }
69
70 static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
71 u32 r, u32 type, u64 cpu_addr,
72 u64 pci_addr, size_t size)
73 {
74 u64 sz = 1ULL << fls64(size - 1);
75 int num_pass_bits = ilog2(sz);
76 u32 addr0, addr1, desc0, desc1;
77 bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG);
78
79 /* The minimal region size is 1MB */
80 if (num_pass_bits < 8)
81 num_pass_bits = 8;
82
83 cpu_addr -= rockchip->mem_res->start;
84 addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) &
85 PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
86 (lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
87 addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr);
88 desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type;
89 desc1 = 0;
90
91 if (is_nor_msg) {
92 rockchip_pcie_write(rockchip, 0,
93 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
94 rockchip_pcie_write(rockchip, 0,
95 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
96 rockchip_pcie_write(rockchip, desc0,
97 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
98 rockchip_pcie_write(rockchip, desc1,
99 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
100 } else {
101 /* PCI bus address region */
102 rockchip_pcie_write(rockchip, addr0,
103 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
104 rockchip_pcie_write(rockchip, addr1,
105 ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
106 rockchip_pcie_write(rockchip, desc0,
107 ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
108 rockchip_pcie_write(rockchip, desc1,
109 ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
110
111 addr0 =
112 ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
113 (lower_32_bits(cpu_addr) &
114 PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
115 addr1 = upper_32_bits(cpu_addr);
116 }
117
118 /* CPU bus address region */
119 rockchip_pcie_write(rockchip, addr0,
120 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r));
121 rockchip_pcie_write(rockchip, addr1,
122 ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r));
123 }
124
125 static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
126 struct pci_epf_header *hdr)
127 {
128 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
129 struct rockchip_pcie *rockchip = &ep->rockchip;
130
131 /* All functions share the same vendor ID with function 0 */
132 if (fn == 0) {
133 u32 vid_regs = (hdr->vendorid & GENMASK(15, 0)) |
134 (hdr->subsys_vendor_id & GENMASK(31, 16)) << 16;
135
136 rockchip_pcie_write(rockchip, vid_regs,
137 PCIE_CORE_CONFIG_VENDOR);
138 }
139
140 rockchip_pcie_write(rockchip, hdr->deviceid << 16,
141 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID);
142
143 rockchip_pcie_write(rockchip,
144 hdr->revid |
145 hdr->progif_code << 8 |
146 hdr->subclass_code << 16 |
147 hdr->baseclass_code << 24,
148 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_REVISION_ID);
149 rockchip_pcie_write(rockchip, hdr->cache_line_size,
150 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
151 PCI_CACHE_LINE_SIZE);
152 rockchip_pcie_write(rockchip, hdr->subsys_id << 16,
153 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
154 PCI_SUBSYSTEM_VENDOR_ID);
155 rockchip_pcie_write(rockchip, hdr->interrupt_pin << 8,
156 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
157 PCI_INTERRUPT_LINE);
158
159 return 0;
160 }
161
162 static int rockchip_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
163 struct pci_epf_bar *epf_bar)
164 {
165 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
166 struct rockchip_pcie *rockchip = &ep->rockchip;
167 dma_addr_t bar_phys = epf_bar->phys_addr;
168 enum pci_barno bar = epf_bar->barno;
169 int flags = epf_bar->flags;
170 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
171 u64 sz;
172
173 /* BAR size is 2^(aperture + 7) */
174 sz = max_t(size_t, epf_bar->size, MIN_EP_APERTURE);
175
176 /*
177 * roundup_pow_of_two() returns an unsigned long, which is not suited
178 * for 64bit values.
179 */
180 sz = 1ULL << fls64(sz - 1);
181 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
182
183 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
184 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_IO_32BITS;
185 } else {
186 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
187 bool is_64bits = sz > SZ_2G;
188
189 if (is_64bits && (bar & 1))
190 return -EINVAL;
191
192 if (is_64bits && is_prefetch)
193 ctrl =
194 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
195 else if (is_prefetch)
196 ctrl =
197 ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
198 else if (is_64bits)
199 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_64BITS;
200 else
201 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_MEM_32BITS;
202 }
203
204 if (bar < BAR_4) {
205 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
206 b = bar;
207 } else {
208 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
209 b = bar - BAR_4;
210 }
211
212 addr0 = lower_32_bits(bar_phys);
213 addr1 = upper_32_bits(bar_phys);
214
215 cfg = rockchip_pcie_read(rockchip, reg);
216 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
217 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
218 cfg |= (ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
219 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
220
221 rockchip_pcie_write(rockchip, cfg, reg);
222 rockchip_pcie_write(rockchip, addr0,
223 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
224 rockchip_pcie_write(rockchip, addr1,
225 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
226
227 return 0;
228 }
229
230 static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
231 struct pci_epf_bar *epf_bar)
232 {
233 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
234 struct rockchip_pcie *rockchip = &ep->rockchip;
235 u32 reg, cfg, b, ctrl;
236 enum pci_barno bar = epf_bar->barno;
237
238 if (bar < BAR_4) {
239 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn);
240 b = bar;
241 } else {
242 reg = ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG1(fn);
243 b = bar - BAR_4;
244 }
245
246 ctrl = ROCKCHIP_PCIE_CORE_BAR_CFG_CTRL_DISABLED;
247 cfg = rockchip_pcie_read(rockchip, reg);
248 cfg &= ~(ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
249 ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
250 cfg |= ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
251
252 rockchip_pcie_write(rockchip, cfg, reg);
253 rockchip_pcie_write(rockchip, 0x0,
254 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar));
255 rockchip_pcie_write(rockchip, 0x0,
256 ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
257 }
258
259 static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn,
260 phys_addr_t addr, u64 pci_addr,
261 size_t size)
262 {
263 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
264 struct rockchip_pcie *pcie = &ep->rockchip;
265 u32 r;
266
267 r = find_first_zero_bit(&ep->ob_region_map,
268 sizeof(ep->ob_region_map) * BITS_PER_LONG);
269 /*
270 * Region 0 is reserved for configuration space and shouldn't
271 * be used elsewhere per TRM, so leave it out.
272 */
273 if (r >= ep->max_regions - 1) {
274 dev_err(&epc->dev, "no free outbound region\n");
275 return -EINVAL;
276 }
277
278 rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr,
279 pci_addr, size);
280
281 set_bit(r, &ep->ob_region_map);
282 ep->ob_addr[r] = addr;
283
284 return 0;
285 }
286
287 static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
288 phys_addr_t addr)
289 {
290 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
291 struct rockchip_pcie *rockchip = &ep->rockchip;
292 u32 r;
293
294 for (r = 0; r < ep->max_regions - 1; r++)
295 if (ep->ob_addr[r] == addr)
296 break;
297
298 /*
299 * Region 0 is reserved for configuration space and shouldn't
300 * be used elsewhere per TRM, so leave it out.
301 */
302 if (r == ep->max_regions - 1)
303 return;
304
305 rockchip_pcie_clear_ep_ob_atu(rockchip, r);
306
307 ep->ob_addr[r] = 0;
308 clear_bit(r, &ep->ob_region_map);
309 }
310
311 static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn,
312 u8 multi_msg_cap)
313 {
314 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
315 struct rockchip_pcie *rockchip = &ep->rockchip;
316 u16 flags;
317
318 flags = rockchip_pcie_read(rockchip,
319 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
320 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
321 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
322 flags |=
323 ((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
324 PCI_MSI_FLAGS_64BIT;
325 flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
326 rockchip_pcie_write(rockchip, flags,
327 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
328 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
329 return 0;
330 }
331
332 static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
333 {
334 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
335 struct rockchip_pcie *rockchip = &ep->rockchip;
336 u16 flags;
337
338 flags = rockchip_pcie_read(rockchip,
339 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
340 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
341 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
342 return -EINVAL;
343
344 return ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
345 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
346 }
347
348 static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
349 u8 intx, bool is_asserted)
350 {
351 struct rockchip_pcie *rockchip = &ep->rockchip;
352 u32 r = ep->max_regions - 1;
353 u32 offset;
354 u32 status;
355 u8 msg_code;
356
357 if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
358 ep->irq_pci_fn != fn)) {
359 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
360 AXI_WRAPPER_NOR_MSG,
361 ep->irq_phys_addr, 0, 0);
362 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
363 ep->irq_pci_fn = fn;
364 }
365
366 intx &= 3;
367 if (is_asserted) {
368 ep->irq_pending |= BIT(intx);
369 msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx;
370 } else {
371 ep->irq_pending &= ~BIT(intx);
372 msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
373 }
374
375 status = rockchip_pcie_read(rockchip,
376 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
377 ROCKCHIP_PCIE_EP_CMD_STATUS);
378 status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
379
380 if ((status != 0) ^ (ep->irq_pending != 0)) {
381 status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
382 rockchip_pcie_write(rockchip, status,
383 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
384 ROCKCHIP_PCIE_EP_CMD_STATUS);
385 }
386
387 offset =
388 ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
389 ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
390 writel(0, ep->irq_cpu_addr + offset);
391 }
392
393 static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
394 u8 intx)
395 {
396 u16 cmd;
397
398 cmd = rockchip_pcie_read(&ep->rockchip,
399 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
400 ROCKCHIP_PCIE_EP_CMD_STATUS);
401
402 if (cmd & PCI_COMMAND_INTX_DISABLE)
403 return -EINVAL;
404
405 /*
406 * Should add some delay between toggling INTx per TRM vaguely saying
407 * it depends on some cycles of the AHB bus clock to function it. So
408 * add sufficient 1ms here.
409 */
410 rockchip_pcie_ep_assert_intx(ep, fn, intx, true);
411 mdelay(1);
412 rockchip_pcie_ep_assert_intx(ep, fn, intx, false);
413 return 0;
414 }
415
416 static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
417 u8 interrupt_num)
418 {
419 struct rockchip_pcie *rockchip = &ep->rockchip;
420 u16 flags, mme, data, data_mask;
421 u8 msi_count;
422 u64 pci_addr, pci_addr_mask = 0xff;
423
424 /* Check MSI enable bit */
425 flags = rockchip_pcie_read(&ep->rockchip,
426 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
427 ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
428 if (!(flags & ROCKCHIP_PCIE_EP_MSI_CTRL_ME))
429 return -EINVAL;
430
431 /* Get MSI numbers from MME */
432 mme = ((flags & ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK) >>
433 ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET);
434 msi_count = 1 << mme;
435 if (!interrupt_num || interrupt_num > msi_count)
436 return -EINVAL;
437
438 /* Set MSI private data */
439 data_mask = msi_count - 1;
440 data = rockchip_pcie_read(rockchip,
441 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
442 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
443 PCI_MSI_DATA_64);
444 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
445
446 /* Get MSI PCI address */
447 pci_addr = rockchip_pcie_read(rockchip,
448 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
449 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
450 PCI_MSI_ADDRESS_HI);
451 pci_addr <<= 32;
452 pci_addr |= rockchip_pcie_read(rockchip,
453 ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
454 ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
455 PCI_MSI_ADDRESS_LO);
456 pci_addr &= GENMASK_ULL(63, 2);
457
458 /* Set the outbound region if needed. */
459 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
460 ep->irq_pci_fn != fn)) {
461 rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1,
462 AXI_WRAPPER_MEM_WRITE,
463 ep->irq_phys_addr,
464 pci_addr & ~pci_addr_mask,
465 pci_addr_mask + 1);
466 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
467 ep->irq_pci_fn = fn;
468 }
469
470 writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
471 return 0;
472 }
473
474 static int rockchip_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
475 enum pci_epc_irq_type type,
476 u16 interrupt_num)
477 {
478 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
479
480 switch (type) {
481 case PCI_EPC_IRQ_LEGACY:
482 return rockchip_pcie_ep_send_legacy_irq(ep, fn, 0);
483 case PCI_EPC_IRQ_MSI:
484 return rockchip_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
485 default:
486 return -EINVAL;
487 }
488 }
489
490 static int rockchip_pcie_ep_start(struct pci_epc *epc)
491 {
492 struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
493 struct rockchip_pcie *rockchip = &ep->rockchip;
494 struct pci_epf *epf;
495 u32 cfg;
496
497 cfg = BIT(0);
498 list_for_each_entry(epf, &epc->pci_epf, list)
499 cfg |= BIT(epf->func_no);
500
501 rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
502
503 return 0;
504 }
505
506 static const struct pci_epc_features rockchip_pcie_epc_features = {
507 .linkup_notifier = false,
508 .msi_capable = true,
509 .msix_capable = false,
510 };
511
512 static const struct pci_epc_features*
513 rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
514 {
515 return &rockchip_pcie_epc_features;
516 }
517
518 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
519 .write_header = rockchip_pcie_ep_write_header,
520 .set_bar = rockchip_pcie_ep_set_bar,
521 .clear_bar = rockchip_pcie_ep_clear_bar,
522 .map_addr = rockchip_pcie_ep_map_addr,
523 .unmap_addr = rockchip_pcie_ep_unmap_addr,
524 .set_msi = rockchip_pcie_ep_set_msi,
525 .get_msi = rockchip_pcie_ep_get_msi,
526 .raise_irq = rockchip_pcie_ep_raise_irq,
527 .start = rockchip_pcie_ep_start,
528 .get_features = rockchip_pcie_ep_get_features,
529 };
530
531 static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
532 struct rockchip_pcie_ep *ep)
533 {
534 struct device *dev = rockchip->dev;
535 int err;
536
537 err = rockchip_pcie_parse_dt(rockchip);
538 if (err)
539 return err;
540
541 err = rockchip_pcie_get_phys(rockchip);
542 if (err)
543 return err;
544
545 err = of_property_read_u32(dev->of_node,
546 "rockchip,max-outbound-regions",
547 &ep->max_regions);
548 if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
549 ep->max_regions = MAX_REGION_LIMIT;
550
551 err = of_property_read_u8(dev->of_node, "max-functions",
552 &ep->epc->max_functions);
553 if (err < 0)
554 ep->epc->max_functions = 1;
555
556 return 0;
557 }
558
559 static const struct of_device_id rockchip_pcie_ep_of_match[] = {
560 { .compatible = "rockchip,rk3399-pcie-ep"},
561 {},
562 };
563
564 static int rockchip_pcie_ep_probe(struct platform_device *pdev)
565 {
566 struct device *dev = &pdev->dev;
567 struct rockchip_pcie_ep *ep;
568 struct rockchip_pcie *rockchip;
569 struct pci_epc *epc;
570 size_t max_regions;
571 int err;
572
573 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
574 if (!ep)
575 return -ENOMEM;
576
577 rockchip = &ep->rockchip;
578 rockchip->is_rc = false;
579 rockchip->dev = dev;
580
581 epc = devm_pci_epc_create(dev, &rockchip_pcie_epc_ops);
582 if (IS_ERR(epc)) {
583 dev_err(dev, "failed to create epc device\n");
584 return PTR_ERR(epc);
585 }
586
587 ep->epc = epc;
588 epc_set_drvdata(epc, ep);
589
590 err = rockchip_pcie_parse_ep_dt(rockchip, ep);
591 if (err)
592 return err;
593
594 err = rockchip_pcie_enable_clocks(rockchip);
595 if (err)
596 return err;
597
598 err = rockchip_pcie_init_port(rockchip);
599 if (err)
600 goto err_disable_clocks;
601
602 /* Establish the link automatically */
603 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
604 PCIE_CLIENT_CONFIG);
605
606 max_regions = ep->max_regions;
607 ep->ob_addr = devm_kcalloc(dev, max_regions, sizeof(*ep->ob_addr),
608 GFP_KERNEL);
609
610 if (!ep->ob_addr) {
611 err = -ENOMEM;
612 goto err_uninit_port;
613 }
614
615 /* Only enable function 0 by default */
616 rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
617
618 err = pci_epc_mem_init(epc, rockchip->mem_res->start,
619 resource_size(rockchip->mem_res), PAGE_SIZE);
620 if (err < 0) {
621 dev_err(dev, "failed to initialize the memory space\n");
622 goto err_uninit_port;
623 }
624
625 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
626 SZ_128K);
627 if (!ep->irq_cpu_addr) {
628 dev_err(dev, "failed to reserve memory space for MSI\n");
629 err = -ENOMEM;
630 goto err_epc_mem_exit;
631 }
632
633 ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
634
635 return 0;
636 err_epc_mem_exit:
637 pci_epc_mem_exit(epc);
638 err_uninit_port:
639 rockchip_pcie_deinit_phys(rockchip);
640 err_disable_clocks:
641 rockchip_pcie_disable_clocks(rockchip);
642 return err;
643 }
644
645 static struct platform_driver rockchip_pcie_ep_driver = {
646 .driver = {
647 .name = "rockchip-pcie-ep",
648 .of_match_table = rockchip_pcie_ep_of_match,
649 },
650 .probe = rockchip_pcie_ep_probe,
651 };
652
653 builtin_platform_driver(rockchip_pcie_ep_driver);
Linux with added FPC-III support