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x86/amd-iommu: Improve handling of full command buffer
[linux/fpc-iii.git] / arch / x86 / kernel / amd_iommu.c
blob75c7f8c3fe12ee0fa7d482c4ba8c648e8884b9a4
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <linux/delay.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32 #include <asm/amd_iommu_proto.h>
33 #include <asm/amd_iommu_types.h>
34 #include <asm/amd_iommu.h>
35
36 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37
38 #define LOOP_TIMEOUT 100000
39
40 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41
42 /* A list of preallocated protection domains */
43 static LIST_HEAD(iommu_pd_list);
44 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45
46 /*
47 * Domain for untranslated devices - only allocated
48 * if iommu=pt passed on kernel cmd line.
49 */
50 static struct protection_domain *pt_domain;
51
52 static struct iommu_ops amd_iommu_ops;
53
54 /*
55 * general struct to manage commands send to an IOMMU
56 */
57 struct iommu_cmd {
58 u32 data[4];
59 };
60
61 static void update_domain(struct protection_domain *domain);
62
63 /****************************************************************************
64 *
65 * Helper functions
66 *
67 ****************************************************************************/
68
69 static inline u16 get_device_id(struct device *dev)
70 {
71 struct pci_dev *pdev = to_pci_dev(dev);
72
73 return calc_devid(pdev->bus->number, pdev->devfn);
74 }
75
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
77 {
78 return dev->archdata.iommu;
79 }
80
81 /*
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
84 */
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
86 {
87 struct dma_ops_domain *entry, *ret = NULL;
88 unsigned long flags;
89 u16 alias = amd_iommu_alias_table[devid];
90
91 if (list_empty(&iommu_pd_list))
92 return NULL;
93
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
95
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
99 ret = entry;
100 break;
101 }
102 }
103
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
105
106 return ret;
107 }
108
109 /*
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
112 */
113 static bool check_device(struct device *dev)
114 {
115 u16 devid;
116
117 if (!dev || !dev->dma_mask)
118 return false;
119
120 /* No device or no PCI device */
121 if (dev->bus != &pci_bus_type)
122 return false;
123
124 devid = get_device_id(dev);
125
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
128 return false;
129
130 if (amd_iommu_rlookup_table[devid] == NULL)
131 return false;
132
133 return true;
134 }
135
136 static int iommu_init_device(struct device *dev)
137 {
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
140 u16 devid, alias;
141
142 if (dev->archdata.iommu)
143 return 0;
144
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
146 if (!dev_data)
147 return -ENOMEM;
148
149 dev_data->dev = dev;
150
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
154 if (pdev)
155 dev_data->alias = &pdev->dev;
156
157 atomic_set(&dev_data->bind, 0);
158
159 dev->archdata.iommu = dev_data;
160
161
162 return 0;
163 }
164
165 static void iommu_uninit_device(struct device *dev)
166 {
167 kfree(dev->archdata.iommu);
168 }
169
170 void __init amd_iommu_uninit_devices(void)
171 {
172 struct pci_dev *pdev = NULL;
173
174 for_each_pci_dev(pdev) {
175
176 if (!check_device(&pdev->dev))
177 continue;
178
179 iommu_uninit_device(&pdev->dev);
180 }
181 }
182
183 int __init amd_iommu_init_devices(void)
184 {
185 struct pci_dev *pdev = NULL;
186 int ret = 0;
187
188 for_each_pci_dev(pdev) {
189
190 if (!check_device(&pdev->dev))
191 continue;
192
193 ret = iommu_init_device(&pdev->dev);
194 if (ret)
195 goto out_free;
196 }
197
198 return 0;
199
200 out_free:
201
202 amd_iommu_uninit_devices();
203
204 return ret;
205 }
206 #ifdef CONFIG_AMD_IOMMU_STATS
207
208 /*
209 * Initialization code for statistics collection
210 */
211
212 DECLARE_STATS_COUNTER(compl_wait);
213 DECLARE_STATS_COUNTER(cnt_map_single);
214 DECLARE_STATS_COUNTER(cnt_unmap_single);
215 DECLARE_STATS_COUNTER(cnt_map_sg);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
218 DECLARE_STATS_COUNTER(cnt_free_coherent);
219 DECLARE_STATS_COUNTER(cross_page);
220 DECLARE_STATS_COUNTER(domain_flush_single);
221 DECLARE_STATS_COUNTER(domain_flush_all);
222 DECLARE_STATS_COUNTER(alloced_io_mem);
223 DECLARE_STATS_COUNTER(total_map_requests);
224
225 static struct dentry *stats_dir;
226 static struct dentry *de_fflush;
227
228 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
229 {
230 if (stats_dir == NULL)
231 return;
232
233 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
234 &cnt->value);
235 }
236
237 static void amd_iommu_stats_init(void)
238 {
239 stats_dir = debugfs_create_dir("amd-iommu", NULL);
240 if (stats_dir == NULL)
241 return;
242
243 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
244 (u32 *)&amd_iommu_unmap_flush);
245
246 amd_iommu_stats_add(&compl_wait);
247 amd_iommu_stats_add(&cnt_map_single);
248 amd_iommu_stats_add(&cnt_unmap_single);
249 amd_iommu_stats_add(&cnt_map_sg);
250 amd_iommu_stats_add(&cnt_unmap_sg);
251 amd_iommu_stats_add(&cnt_alloc_coherent);
252 amd_iommu_stats_add(&cnt_free_coherent);
253 amd_iommu_stats_add(&cross_page);
254 amd_iommu_stats_add(&domain_flush_single);
255 amd_iommu_stats_add(&domain_flush_all);
256 amd_iommu_stats_add(&alloced_io_mem);
257 amd_iommu_stats_add(&total_map_requests);
258 }
259
260 #endif
261
262 /****************************************************************************
263 *
264 * Interrupt handling functions
265 *
266 ****************************************************************************/
267
268 static void dump_dte_entry(u16 devid)
269 {
270 int i;
271
272 for (i = 0; i < 8; ++i)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
274 amd_iommu_dev_table[devid].data[i]);
275 }
276
277 static void dump_command(unsigned long phys_addr)
278 {
279 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
280 int i;
281
282 for (i = 0; i < 4; ++i)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
284 }
285
286 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
287 {
288 u32 *event = __evt;
289 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
290 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
291 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
292 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
293 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
294
295 printk(KERN_ERR "AMD-Vi: Event logged [");
296
297 switch (type) {
298 case EVENT_TYPE_ILL_DEV:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
302 address, flags);
303 dump_dte_entry(devid);
304 break;
305 case EVENT_TYPE_IO_FAULT:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
309 domid, address, flags);
310 break;
311 case EVENT_TYPE_DEV_TAB_ERR:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
315 address, flags);
316 break;
317 case EVENT_TYPE_PAGE_TAB_ERR:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
321 domid, address, flags);
322 break;
323 case EVENT_TYPE_ILL_CMD:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
325 dump_command(address);
326 break;
327 case EVENT_TYPE_CMD_HARD_ERR:
328 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
329 "flags=0x%04x]\n", address, flags);
330 break;
331 case EVENT_TYPE_IOTLB_INV_TO:
332 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
333 "address=0x%016llx]\n",
334 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
335 address);
336 break;
337 case EVENT_TYPE_INV_DEV_REQ:
338 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
339 "address=0x%016llx flags=0x%04x]\n",
340 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
341 address, flags);
342 break;
343 default:
344 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
345 }
346 }
347
348 static void iommu_poll_events(struct amd_iommu *iommu)
349 {
350 u32 head, tail;
351 unsigned long flags;
352
353 spin_lock_irqsave(&iommu->lock, flags);
354
355 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
356 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
357
358 while (head != tail) {
359 iommu_print_event(iommu, iommu->evt_buf + head);
360 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
361 }
362
363 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
364
365 spin_unlock_irqrestore(&iommu->lock, flags);
366 }
367
368 irqreturn_t amd_iommu_int_handler(int irq, void *data)
369 {
370 struct amd_iommu *iommu;
371
372 for_each_iommu(iommu)
373 iommu_poll_events(iommu);
374
375 return IRQ_HANDLED;
376 }
377
378 /****************************************************************************
379 *
380 * IOMMU command queuing functions
381 *
382 ****************************************************************************/
383
384 static int wait_on_sem(volatile u64 *sem)
385 {
386 int i = 0;
387
388 while (*sem == 0 && i < LOOP_TIMEOUT) {
389 udelay(1);
390 i += 1;
391 }
392
393 if (i == LOOP_TIMEOUT) {
394 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
395 return -EIO;
396 }
397
398 return 0;
399 }
400
401 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
402 struct iommu_cmd *cmd,
403 u32 tail)
404 {
405 u8 *target;
406
407 target = iommu->cmd_buf + tail;
408 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
409
410 /* Copy command to buffer */
411 memcpy(target, cmd, sizeof(*cmd));
412
413 /* Tell the IOMMU about it */
414 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
415 }
416
417 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
418 {
419 WARN_ON(address & 0x7ULL);
420
421 memset(cmd, 0, sizeof(*cmd));
422 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
423 cmd->data[1] = upper_32_bits(__pa(address));
424 cmd->data[2] = 1;
425 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
426 }
427
428 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
429 {
430 memset(cmd, 0, sizeof(*cmd));
431 cmd->data[0] = devid;
432 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
433 }
434
435 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
436 size_t size, u16 domid, int pde)
437 {
438 u64 pages;
439 int s;
440
441 pages = iommu_num_pages(address, size, PAGE_SIZE);
442 s = 0;
443
444 if (pages > 1) {
445 /*
446 * If we have to flush more than one page, flush all
447 * TLB entries for this domain
448 */
449 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
450 s = 1;
451 }
452
453 address &= PAGE_MASK;
454
455 memset(cmd, 0, sizeof(*cmd));
456 cmd->data[1] |= domid;
457 cmd->data[2] = lower_32_bits(address);
458 cmd->data[3] = upper_32_bits(address);
459 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
460 if (s) /* size bit - we flush more than one 4kb page */
461 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
462 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
463 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
464 }
465
466 /*
467 * Writes the command to the IOMMUs command buffer and informs the
468 * hardware about the new command.
469 */
470 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
471 {
472 u32 left, tail, head, next_tail;
473 unsigned long flags;
474
475 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
476
477 again:
478 spin_lock_irqsave(&iommu->lock, flags);
479
480 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
481 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
482 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
483 left = (head - next_tail) % iommu->cmd_buf_size;
484
485 if (left <= 2) {
486 struct iommu_cmd sync_cmd;
487 volatile u64 sem = 0;
488 int ret;
489
490 build_completion_wait(&sync_cmd, (u64)&sem);
491 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
492
493 spin_unlock_irqrestore(&iommu->lock, flags);
494
495 if ((ret = wait_on_sem(&sem)) != 0)
496 return ret;
497
498 goto again;
499 }
500
501 copy_cmd_to_buffer(iommu, cmd, tail);
502
503 /* We need to sync now to make sure all commands are processed */
504 iommu->need_sync = true;
505
506 spin_unlock_irqrestore(&iommu->lock, flags);
507
508 return 0;
509 }
510
511 /*
512 * This function queues a completion wait command into the command
513 * buffer of an IOMMU
514 */
515 static int iommu_completion_wait(struct amd_iommu *iommu)
516 {
517 struct iommu_cmd cmd;
518 volatile u64 sem = 0;
519 int ret;
520
521 if (!iommu->need_sync)
522 return 0;
523
524 build_completion_wait(&cmd, (u64)&sem);
525
526 ret = iommu_queue_command(iommu, &cmd);
527 if (ret)
528 return ret;
529
530 return wait_on_sem(&sem);
531 }
532
533 /*
534 * Command send function for invalidating a device table entry
535 */
536 static int iommu_flush_device(struct device *dev)
537 {
538 struct amd_iommu *iommu;
539 struct iommu_cmd cmd;
540 u16 devid;
541
542 devid = get_device_id(dev);
543 iommu = amd_iommu_rlookup_table[devid];
544
545 build_inv_dte(&cmd, devid);
546
547 return iommu_queue_command(iommu, &cmd);
548 }
549
550 /*
551 * TLB invalidation function which is called from the mapping functions.
552 * It invalidates a single PTE if the range to flush is within a single
553 * page. Otherwise it flushes the whole TLB of the IOMMU.
554 */
555 static void __domain_flush_pages(struct protection_domain *domain,
556 u64 address, size_t size, int pde)
557 {
558 struct iommu_cmd cmd;
559 int ret = 0, i;
560
561 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
562
563 for (i = 0; i < amd_iommus_present; ++i) {
564 if (!domain->dev_iommu[i])
565 continue;
566
567 /*
568 * Devices of this domain are behind this IOMMU
569 * We need a TLB flush
570 */
571 ret |= iommu_queue_command(amd_iommus[i], &cmd);
572 }
573
574 WARN_ON(ret);
575 }
576
577 static void domain_flush_pages(struct protection_domain *domain,
578 u64 address, size_t size)
579 {
580 __domain_flush_pages(domain, address, size, 0);
581 }
582
583 /* Flush the whole IO/TLB for a given protection domain */
584 static void domain_flush_tlb(struct protection_domain *domain)
585 {
586 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
587 }
588
589 /* Flush the whole IO/TLB for a given protection domain - including PDE */
590 static void domain_flush_tlb_pde(struct protection_domain *domain)
591 {
592 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
593 }
594
595 static void domain_flush_complete(struct protection_domain *domain)
596 {
597 int i;
598
599 for (i = 0; i < amd_iommus_present; ++i) {
600 if (!domain->dev_iommu[i])
601 continue;
602
603 /*
604 * Devices of this domain are behind this IOMMU
605 * We need to wait for completion of all commands.
606 */
607 iommu_completion_wait(amd_iommus[i]);
608 }
609 }
610
611
612 /*
613 * This function flushes the DTEs for all devices in domain
614 */
615 static void domain_flush_devices(struct protection_domain *domain)
616 {
617 struct iommu_dev_data *dev_data;
618 unsigned long flags;
619
620 spin_lock_irqsave(&domain->lock, flags);
621
622 list_for_each_entry(dev_data, &domain->dev_list, list)
623 iommu_flush_device(dev_data->dev);
624
625 spin_unlock_irqrestore(&domain->lock, flags);
626 }
627
628 static void iommu_flush_all_domain_devices(void)
629 {
630 struct protection_domain *domain;
631 unsigned long flags;
632
633 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
634
635 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
636 domain_flush_devices(domain);
637 domain_flush_complete(domain);
638 }
639
640 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
641 }
642
643 void amd_iommu_flush_all_devices(void)
644 {
645 iommu_flush_all_domain_devices();
646 }
647
648 /*
649 * This function uses heavy locking and may disable irqs for some time. But
650 * this is no issue because it is only called during resume.
651 */
652 void amd_iommu_flush_all_domains(void)
653 {
654 struct protection_domain *domain;
655 unsigned long flags;
656
657 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
658
659 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
660 spin_lock(&domain->lock);
661 domain_flush_tlb_pde(domain);
662 domain_flush_complete(domain);
663 spin_unlock(&domain->lock);
664 }
665
666 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
667 }
668
669 /****************************************************************************
670 *
671 * The functions below are used the create the page table mappings for
672 * unity mapped regions.
673 *
674 ****************************************************************************/
675
676 /*
677 * This function is used to add another level to an IO page table. Adding
678 * another level increases the size of the address space by 9 bits to a size up
679 * to 64 bits.
680 */
681 static bool increase_address_space(struct protection_domain *domain,
682 gfp_t gfp)
683 {
684 u64 *pte;
685
686 if (domain->mode == PAGE_MODE_6_LEVEL)
687 /* address space already 64 bit large */
688 return false;
689
690 pte = (void *)get_zeroed_page(gfp);
691 if (!pte)
692 return false;
693
694 *pte = PM_LEVEL_PDE(domain->mode,
695 virt_to_phys(domain->pt_root));
696 domain->pt_root = pte;
697 domain->mode += 1;
698 domain->updated = true;
699
700 return true;
701 }
702
703 static u64 *alloc_pte(struct protection_domain *domain,
704 unsigned long address,
705 unsigned long page_size,
706 u64 **pte_page,
707 gfp_t gfp)
708 {
709 int level, end_lvl;
710 u64 *pte, *page;
711
712 BUG_ON(!is_power_of_2(page_size));
713
714 while (address > PM_LEVEL_SIZE(domain->mode))
715 increase_address_space(domain, gfp);
716
717 level = domain->mode - 1;
718 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
719 address = PAGE_SIZE_ALIGN(address, page_size);
720 end_lvl = PAGE_SIZE_LEVEL(page_size);
721
722 while (level > end_lvl) {
723 if (!IOMMU_PTE_PRESENT(*pte)) {
724 page = (u64 *)get_zeroed_page(gfp);
725 if (!page)
726 return NULL;
727 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
728 }
729
730 /* No level skipping support yet */
731 if (PM_PTE_LEVEL(*pte) != level)
732 return NULL;
733
734 level -= 1;
735
736 pte = IOMMU_PTE_PAGE(*pte);
737
738 if (pte_page && level == end_lvl)
739 *pte_page = pte;
740
741 pte = &pte[PM_LEVEL_INDEX(level, address)];
742 }
743
744 return pte;
745 }
746
747 /*
748 * This function checks if there is a PTE for a given dma address. If
749 * there is one, it returns the pointer to it.
750 */
751 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
752 {
753 int level;
754 u64 *pte;
755
756 if (address > PM_LEVEL_SIZE(domain->mode))
757 return NULL;
758
759 level = domain->mode - 1;
760 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
761
762 while (level > 0) {
763
764 /* Not Present */
765 if (!IOMMU_PTE_PRESENT(*pte))
766 return NULL;
767
768 /* Large PTE */
769 if (PM_PTE_LEVEL(*pte) == 0x07) {
770 unsigned long pte_mask, __pte;
771
772 /*
773 * If we have a series of large PTEs, make
774 * sure to return a pointer to the first one.
775 */
776 pte_mask = PTE_PAGE_SIZE(*pte);
777 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
778 __pte = ((unsigned long)pte) & pte_mask;
779
780 return (u64 *)__pte;
781 }
782
783 /* No level skipping support yet */
784 if (PM_PTE_LEVEL(*pte) != level)
785 return NULL;
786
787 level -= 1;
788
789 /* Walk to the next level */
790 pte = IOMMU_PTE_PAGE(*pte);
791 pte = &pte[PM_LEVEL_INDEX(level, address)];
792 }
793
794 return pte;
795 }
796
797 /*
798 * Generic mapping functions. It maps a physical address into a DMA
799 * address space. It allocates the page table pages if necessary.
800 * In the future it can be extended to a generic mapping function
801 * supporting all features of AMD IOMMU page tables like level skipping
802 * and full 64 bit address spaces.
803 */
804 static int iommu_map_page(struct protection_domain *dom,
805 unsigned long bus_addr,
806 unsigned long phys_addr,
807 int prot,
808 unsigned long page_size)
809 {
810 u64 __pte, *pte;
811 int i, count;
812
813 if (!(prot & IOMMU_PROT_MASK))
814 return -EINVAL;
815
816 bus_addr = PAGE_ALIGN(bus_addr);
817 phys_addr = PAGE_ALIGN(phys_addr);
818 count = PAGE_SIZE_PTE_COUNT(page_size);
819 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
820
821 for (i = 0; i < count; ++i)
822 if (IOMMU_PTE_PRESENT(pte[i]))
823 return -EBUSY;
824
825 if (page_size > PAGE_SIZE) {
826 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
827 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
828 } else
829 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
830
831 if (prot & IOMMU_PROT_IR)
832 __pte |= IOMMU_PTE_IR;
833 if (prot & IOMMU_PROT_IW)
834 __pte |= IOMMU_PTE_IW;
835
836 for (i = 0; i < count; ++i)
837 pte[i] = __pte;
838
839 update_domain(dom);
840
841 return 0;
842 }
843
844 static unsigned long iommu_unmap_page(struct protection_domain *dom,
845 unsigned long bus_addr,
846 unsigned long page_size)
847 {
848 unsigned long long unmap_size, unmapped;
849 u64 *pte;
850
851 BUG_ON(!is_power_of_2(page_size));
852
853 unmapped = 0;
854
855 while (unmapped < page_size) {
856
857 pte = fetch_pte(dom, bus_addr);
858
859 if (!pte) {
860 /*
861 * No PTE for this address
862 * move forward in 4kb steps
863 */
864 unmap_size = PAGE_SIZE;
865 } else if (PM_PTE_LEVEL(*pte) == 0) {
866 /* 4kb PTE found for this address */
867 unmap_size = PAGE_SIZE;
868 *pte = 0ULL;
869 } else {
870 int count, i;
871
872 /* Large PTE found which maps this address */
873 unmap_size = PTE_PAGE_SIZE(*pte);
874 count = PAGE_SIZE_PTE_COUNT(unmap_size);
875 for (i = 0; i < count; i++)
876 pte[i] = 0ULL;
877 }
878
879 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
880 unmapped += unmap_size;
881 }
882
883 BUG_ON(!is_power_of_2(unmapped));
884
885 return unmapped;
886 }
887
888 /*
889 * This function checks if a specific unity mapping entry is needed for
890 * this specific IOMMU.
891 */
892 static int iommu_for_unity_map(struct amd_iommu *iommu,
893 struct unity_map_entry *entry)
894 {
895 u16 bdf, i;
896
897 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
898 bdf = amd_iommu_alias_table[i];
899 if (amd_iommu_rlookup_table[bdf] == iommu)
900 return 1;
901 }
902
903 return 0;
904 }
905
906 /*
907 * This function actually applies the mapping to the page table of the
908 * dma_ops domain.
909 */
910 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
911 struct unity_map_entry *e)
912 {
913 u64 addr;
914 int ret;
915
916 for (addr = e->address_start; addr < e->address_end;
917 addr += PAGE_SIZE) {
918 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
919 PAGE_SIZE);
920 if (ret)
921 return ret;
922 /*
923 * if unity mapping is in aperture range mark the page
924 * as allocated in the aperture
925 */
926 if (addr < dma_dom->aperture_size)
927 __set_bit(addr >> PAGE_SHIFT,
928 dma_dom->aperture[0]->bitmap);
929 }
930
931 return 0;
932 }
933
934 /*
935 * Init the unity mappings for a specific IOMMU in the system
936 *
937 * Basically iterates over all unity mapping entries and applies them to
938 * the default domain DMA of that IOMMU if necessary.
939 */
940 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
941 {
942 struct unity_map_entry *entry;
943 int ret;
944
945 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
946 if (!iommu_for_unity_map(iommu, entry))
947 continue;
948 ret = dma_ops_unity_map(iommu->default_dom, entry);
949 if (ret)
950 return ret;
951 }
952
953 return 0;
954 }
955
956 /*
957 * Inits the unity mappings required for a specific device
958 */
959 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
960 u16 devid)
961 {
962 struct unity_map_entry *e;
963 int ret;
964
965 list_for_each_entry(e, &amd_iommu_unity_map, list) {
966 if (!(devid >= e->devid_start && devid <= e->devid_end))
967 continue;
968 ret = dma_ops_unity_map(dma_dom, e);
969 if (ret)
970 return ret;
971 }
972
973 return 0;
974 }
975
976 /****************************************************************************
977 *
978 * The next functions belong to the address allocator for the dma_ops
979 * interface functions. They work like the allocators in the other IOMMU
980 * drivers. Its basically a bitmap which marks the allocated pages in
981 * the aperture. Maybe it could be enhanced in the future to a more
982 * efficient allocator.
983 *
984 ****************************************************************************/
985
986 /*
987 * The address allocator core functions.
988 *
989 * called with domain->lock held
990 */
991
992 /*
993 * Used to reserve address ranges in the aperture (e.g. for exclusion
994 * ranges.
995 */
996 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
997 unsigned long start_page,
998 unsigned int pages)
999 {
1000 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1001
1002 if (start_page + pages > last_page)
1003 pages = last_page - start_page;
1004
1005 for (i = start_page; i < start_page + pages; ++i) {
1006 int index = i / APERTURE_RANGE_PAGES;
1007 int page = i % APERTURE_RANGE_PAGES;
1008 __set_bit(page, dom->aperture[index]->bitmap);
1009 }
1010 }
1011
1012 /*
1013 * This function is used to add a new aperture range to an existing
1014 * aperture in case of dma_ops domain allocation or address allocation
1015 * failure.
1016 */
1017 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1018 bool populate, gfp_t gfp)
1019 {
1020 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1021 struct amd_iommu *iommu;
1022 unsigned long i;
1023
1024 #ifdef CONFIG_IOMMU_STRESS
1025 populate = false;
1026 #endif
1027
1028 if (index >= APERTURE_MAX_RANGES)
1029 return -ENOMEM;
1030
1031 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1032 if (!dma_dom->aperture[index])
1033 return -ENOMEM;
1034
1035 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1036 if (!dma_dom->aperture[index]->bitmap)
1037 goto out_free;
1038
1039 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1040
1041 if (populate) {
1042 unsigned long address = dma_dom->aperture_size;
1043 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1044 u64 *pte, *pte_page;
1045
1046 for (i = 0; i < num_ptes; ++i) {
1047 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1048 &pte_page, gfp);
1049 if (!pte)
1050 goto out_free;
1051
1052 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1053
1054 address += APERTURE_RANGE_SIZE / 64;
1055 }
1056 }
1057
1058 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1059
1060 /* Initialize the exclusion range if necessary */
1061 for_each_iommu(iommu) {
1062 if (iommu->exclusion_start &&
1063 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1064 && iommu->exclusion_start < dma_dom->aperture_size) {
1065 unsigned long startpage;
1066 int pages = iommu_num_pages(iommu->exclusion_start,
1067 iommu->exclusion_length,
1068 PAGE_SIZE);
1069 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1070 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1071 }
1072 }
1073
1074 /*
1075 * Check for areas already mapped as present in the new aperture
1076 * range and mark those pages as reserved in the allocator. Such
1077 * mappings may already exist as a result of requested unity
1078 * mappings for devices.
1079 */
1080 for (i = dma_dom->aperture[index]->offset;
1081 i < dma_dom->aperture_size;
1082 i += PAGE_SIZE) {
1083 u64 *pte = fetch_pte(&dma_dom->domain, i);
1084 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1085 continue;
1086
1087 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1088 }
1089
1090 update_domain(&dma_dom->domain);
1091
1092 return 0;
1093
1094 out_free:
1095 update_domain(&dma_dom->domain);
1096
1097 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1098
1099 kfree(dma_dom->aperture[index]);
1100 dma_dom->aperture[index] = NULL;
1101
1102 return -ENOMEM;
1103 }
1104
1105 static unsigned long dma_ops_area_alloc(struct device *dev,
1106 struct dma_ops_domain *dom,
1107 unsigned int pages,
1108 unsigned long align_mask,
1109 u64 dma_mask,
1110 unsigned long start)
1111 {
1112 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1113 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1114 int i = start >> APERTURE_RANGE_SHIFT;
1115 unsigned long boundary_size;
1116 unsigned long address = -1;
1117 unsigned long limit;
1118
1119 next_bit >>= PAGE_SHIFT;
1120
1121 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1122 PAGE_SIZE) >> PAGE_SHIFT;
1123
1124 for (;i < max_index; ++i) {
1125 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1126
1127 if (dom->aperture[i]->offset >= dma_mask)
1128 break;
1129
1130 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1131 dma_mask >> PAGE_SHIFT);
1132
1133 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1134 limit, next_bit, pages, 0,
1135 boundary_size, align_mask);
1136 if (address != -1) {
1137 address = dom->aperture[i]->offset +
1138 (address << PAGE_SHIFT);
1139 dom->next_address = address + (pages << PAGE_SHIFT);
1140 break;
1141 }
1142
1143 next_bit = 0;
1144 }
1145
1146 return address;
1147 }
1148
1149 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1150 struct dma_ops_domain *dom,
1151 unsigned int pages,
1152 unsigned long align_mask,
1153 u64 dma_mask)
1154 {
1155 unsigned long address;
1156
1157 #ifdef CONFIG_IOMMU_STRESS
1158 dom->next_address = 0;
1159 dom->need_flush = true;
1160 #endif
1161
1162 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1163 dma_mask, dom->next_address);
1164
1165 if (address == -1) {
1166 dom->next_address = 0;
1167 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1168 dma_mask, 0);
1169 dom->need_flush = true;
1170 }
1171
1172 if (unlikely(address == -1))
1173 address = DMA_ERROR_CODE;
1174
1175 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1176
1177 return address;
1178 }
1179
1180 /*
1181 * The address free function.
1182 *
1183 * called with domain->lock held
1184 */
1185 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1186 unsigned long address,
1187 unsigned int pages)
1188 {
1189 unsigned i = address >> APERTURE_RANGE_SHIFT;
1190 struct aperture_range *range = dom->aperture[i];
1191
1192 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1193
1194 #ifdef CONFIG_IOMMU_STRESS
1195 if (i < 4)
1196 return;
1197 #endif
1198
1199 if (address >= dom->next_address)
1200 dom->need_flush = true;
1201
1202 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1203
1204 bitmap_clear(range->bitmap, address, pages);
1205
1206 }
1207
1208 /****************************************************************************
1209 *
1210 * The next functions belong to the domain allocation. A domain is
1211 * allocated for every IOMMU as the default domain. If device isolation
1212 * is enabled, every device get its own domain. The most important thing
1213 * about domains is the page table mapping the DMA address space they
1214 * contain.
1215 *
1216 ****************************************************************************/
1217
1218 /*
1219 * This function adds a protection domain to the global protection domain list
1220 */
1221 static void add_domain_to_list(struct protection_domain *domain)
1222 {
1223 unsigned long flags;
1224
1225 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1226 list_add(&domain->list, &amd_iommu_pd_list);
1227 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1228 }
1229
1230 /*
1231 * This function removes a protection domain to the global
1232 * protection domain list
1233 */
1234 static void del_domain_from_list(struct protection_domain *domain)
1235 {
1236 unsigned long flags;
1237
1238 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1239 list_del(&domain->list);
1240 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1241 }
1242
1243 static u16 domain_id_alloc(void)
1244 {
1245 unsigned long flags;
1246 int id;
1247
1248 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1249 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1250 BUG_ON(id == 0);
1251 if (id > 0 && id < MAX_DOMAIN_ID)
1252 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1253 else
1254 id = 0;
1255 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1256
1257 return id;
1258 }
1259
1260 static void domain_id_free(int id)
1261 {
1262 unsigned long flags;
1263
1264 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1265 if (id > 0 && id < MAX_DOMAIN_ID)
1266 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1267 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1268 }
1269
1270 static void free_pagetable(struct protection_domain *domain)
1271 {
1272 int i, j;
1273 u64 *p1, *p2, *p3;
1274
1275 p1 = domain->pt_root;
1276
1277 if (!p1)
1278 return;
1279
1280 for (i = 0; i < 512; ++i) {
1281 if (!IOMMU_PTE_PRESENT(p1[i]))
1282 continue;
1283
1284 p2 = IOMMU_PTE_PAGE(p1[i]);
1285 for (j = 0; j < 512; ++j) {
1286 if (!IOMMU_PTE_PRESENT(p2[j]))
1287 continue;
1288 p3 = IOMMU_PTE_PAGE(p2[j]);
1289 free_page((unsigned long)p3);
1290 }
1291
1292 free_page((unsigned long)p2);
1293 }
1294
1295 free_page((unsigned long)p1);
1296
1297 domain->pt_root = NULL;
1298 }
1299
1300 /*
1301 * Free a domain, only used if something went wrong in the
1302 * allocation path and we need to free an already allocated page table
1303 */
1304 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1305 {
1306 int i;
1307
1308 if (!dom)
1309 return;
1310
1311 del_domain_from_list(&dom->domain);
1312
1313 free_pagetable(&dom->domain);
1314
1315 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1316 if (!dom->aperture[i])
1317 continue;
1318 free_page((unsigned long)dom->aperture[i]->bitmap);
1319 kfree(dom->aperture[i]);
1320 }
1321
1322 kfree(dom);
1323 }
1324
1325 /*
1326 * Allocates a new protection domain usable for the dma_ops functions.
1327 * It also initializes the page table and the address allocator data
1328 * structures required for the dma_ops interface
1329 */
1330 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1331 {
1332 struct dma_ops_domain *dma_dom;
1333
1334 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1335 if (!dma_dom)
1336 return NULL;
1337
1338 spin_lock_init(&dma_dom->domain.lock);
1339
1340 dma_dom->domain.id = domain_id_alloc();
1341 if (dma_dom->domain.id == 0)
1342 goto free_dma_dom;
1343 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1344 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1345 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1346 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1347 dma_dom->domain.priv = dma_dom;
1348 if (!dma_dom->domain.pt_root)
1349 goto free_dma_dom;
1350
1351 dma_dom->need_flush = false;
1352 dma_dom->target_dev = 0xffff;
1353
1354 add_domain_to_list(&dma_dom->domain);
1355
1356 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1357 goto free_dma_dom;
1358
1359 /*
1360 * mark the first page as allocated so we never return 0 as
1361 * a valid dma-address. So we can use 0 as error value
1362 */
1363 dma_dom->aperture[0]->bitmap[0] = 1;
1364 dma_dom->next_address = 0;
1365
1366
1367 return dma_dom;
1368
1369 free_dma_dom:
1370 dma_ops_domain_free(dma_dom);
1371
1372 return NULL;
1373 }
1374
1375 /*
1376 * little helper function to check whether a given protection domain is a
1377 * dma_ops domain
1378 */
1379 static bool dma_ops_domain(struct protection_domain *domain)
1380 {
1381 return domain->flags & PD_DMA_OPS_MASK;
1382 }
1383
1384 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1385 {
1386 u64 pte_root = virt_to_phys(domain->pt_root);
1387
1388 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1389 << DEV_ENTRY_MODE_SHIFT;
1390 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1391
1392 amd_iommu_dev_table[devid].data[2] = domain->id;
1393 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1394 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1395 }
1396
1397 static void clear_dte_entry(u16 devid)
1398 {
1399 /* remove entry from the device table seen by the hardware */
1400 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1401 amd_iommu_dev_table[devid].data[1] = 0;
1402 amd_iommu_dev_table[devid].data[2] = 0;
1403
1404 amd_iommu_apply_erratum_63(devid);
1405 }
1406
1407 static void do_attach(struct device *dev, struct protection_domain *domain)
1408 {
1409 struct iommu_dev_data *dev_data;
1410 struct amd_iommu *iommu;
1411 u16 devid;
1412
1413 devid = get_device_id(dev);
1414 iommu = amd_iommu_rlookup_table[devid];
1415 dev_data = get_dev_data(dev);
1416
1417 /* Update data structures */
1418 dev_data->domain = domain;
1419 list_add(&dev_data->list, &domain->dev_list);
1420 set_dte_entry(devid, domain);
1421
1422 /* Do reference counting */
1423 domain->dev_iommu[iommu->index] += 1;
1424 domain->dev_cnt += 1;
1425
1426 /* Flush the DTE entry */
1427 iommu_flush_device(dev);
1428 }
1429
1430 static void do_detach(struct device *dev)
1431 {
1432 struct iommu_dev_data *dev_data;
1433 struct amd_iommu *iommu;
1434 u16 devid;
1435
1436 devid = get_device_id(dev);
1437 iommu = amd_iommu_rlookup_table[devid];
1438 dev_data = get_dev_data(dev);
1439
1440 /* decrease reference counters */
1441 dev_data->domain->dev_iommu[iommu->index] -= 1;
1442 dev_data->domain->dev_cnt -= 1;
1443
1444 /* Update data structures */
1445 dev_data->domain = NULL;
1446 list_del(&dev_data->list);
1447 clear_dte_entry(devid);
1448
1449 /* Flush the DTE entry */
1450 iommu_flush_device(dev);
1451 }
1452
1453 /*
1454 * If a device is not yet associated with a domain, this function does
1455 * assigns it visible for the hardware
1456 */
1457 static int __attach_device(struct device *dev,
1458 struct protection_domain *domain)
1459 {
1460 struct iommu_dev_data *dev_data, *alias_data;
1461 int ret;
1462
1463 dev_data = get_dev_data(dev);
1464 alias_data = get_dev_data(dev_data->alias);
1465
1466 if (!alias_data)
1467 return -EINVAL;
1468
1469 /* lock domain */
1470 spin_lock(&domain->lock);
1471
1472 /* Some sanity checks */
1473 ret = -EBUSY;
1474 if (alias_data->domain != NULL &&
1475 alias_data->domain != domain)
1476 goto out_unlock;
1477
1478 if (dev_data->domain != NULL &&
1479 dev_data->domain != domain)
1480 goto out_unlock;
1481
1482 /* Do real assignment */
1483 if (dev_data->alias != dev) {
1484 alias_data = get_dev_data(dev_data->alias);
1485 if (alias_data->domain == NULL)
1486 do_attach(dev_data->alias, domain);
1487
1488 atomic_inc(&alias_data->bind);
1489 }
1490
1491 if (dev_data->domain == NULL)
1492 do_attach(dev, domain);
1493
1494 atomic_inc(&dev_data->bind);
1495
1496 ret = 0;
1497
1498 out_unlock:
1499
1500 /* ready */
1501 spin_unlock(&domain->lock);
1502
1503 return ret;
1504 }
1505
1506 /*
1507 * If a device is not yet associated with a domain, this function does
1508 * assigns it visible for the hardware
1509 */
1510 static int attach_device(struct device *dev,
1511 struct protection_domain *domain)
1512 {
1513 unsigned long flags;
1514 int ret;
1515
1516 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1517 ret = __attach_device(dev, domain);
1518 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1519
1520 /*
1521 * We might boot into a crash-kernel here. The crashed kernel
1522 * left the caches in the IOMMU dirty. So we have to flush
1523 * here to evict all dirty stuff.
1524 */
1525 domain_flush_tlb_pde(domain);
1526
1527 return ret;
1528 }
1529
1530 /*
1531 * Removes a device from a protection domain (unlocked)
1532 */
1533 static void __detach_device(struct device *dev)
1534 {
1535 struct iommu_dev_data *dev_data = get_dev_data(dev);
1536 struct iommu_dev_data *alias_data;
1537 struct protection_domain *domain;
1538 unsigned long flags;
1539
1540 BUG_ON(!dev_data->domain);
1541
1542 domain = dev_data->domain;
1543
1544 spin_lock_irqsave(&domain->lock, flags);
1545
1546 if (dev_data->alias != dev) {
1547 alias_data = get_dev_data(dev_data->alias);
1548 if (atomic_dec_and_test(&alias_data->bind))
1549 do_detach(dev_data->alias);
1550 }
1551
1552 if (atomic_dec_and_test(&dev_data->bind))
1553 do_detach(dev);
1554
1555 spin_unlock_irqrestore(&domain->lock, flags);
1556
1557 /*
1558 * If we run in passthrough mode the device must be assigned to the
1559 * passthrough domain if it is detached from any other domain.
1560 * Make sure we can deassign from the pt_domain itself.
1561 */
1562 if (iommu_pass_through &&
1563 (dev_data->domain == NULL && domain != pt_domain))
1564 __attach_device(dev, pt_domain);
1565 }
1566
1567 /*
1568 * Removes a device from a protection domain (with devtable_lock held)
1569 */
1570 static void detach_device(struct device *dev)
1571 {
1572 unsigned long flags;
1573
1574 /* lock device table */
1575 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1576 __detach_device(dev);
1577 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1578 }
1579
1580 /*
1581 * Find out the protection domain structure for a given PCI device. This
1582 * will give us the pointer to the page table root for example.
1583 */
1584 static struct protection_domain *domain_for_device(struct device *dev)
1585 {
1586 struct protection_domain *dom;
1587 struct iommu_dev_data *dev_data, *alias_data;
1588 unsigned long flags;
1589 u16 devid, alias;
1590
1591 devid = get_device_id(dev);
1592 alias = amd_iommu_alias_table[devid];
1593 dev_data = get_dev_data(dev);
1594 alias_data = get_dev_data(dev_data->alias);
1595 if (!alias_data)
1596 return NULL;
1597
1598 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1599 dom = dev_data->domain;
1600 if (dom == NULL &&
1601 alias_data->domain != NULL) {
1602 __attach_device(dev, alias_data->domain);
1603 dom = alias_data->domain;
1604 }
1605
1606 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1607
1608 return dom;
1609 }
1610
1611 static int device_change_notifier(struct notifier_block *nb,
1612 unsigned long action, void *data)
1613 {
1614 struct device *dev = data;
1615 u16 devid;
1616 struct protection_domain *domain;
1617 struct dma_ops_domain *dma_domain;
1618 struct amd_iommu *iommu;
1619 unsigned long flags;
1620
1621 if (!check_device(dev))
1622 return 0;
1623
1624 devid = get_device_id(dev);
1625 iommu = amd_iommu_rlookup_table[devid];
1626
1627 switch (action) {
1628 case BUS_NOTIFY_UNBOUND_DRIVER:
1629
1630 domain = domain_for_device(dev);
1631
1632 if (!domain)
1633 goto out;
1634 if (iommu_pass_through)
1635 break;
1636 detach_device(dev);
1637 break;
1638 case BUS_NOTIFY_ADD_DEVICE:
1639
1640 iommu_init_device(dev);
1641
1642 domain = domain_for_device(dev);
1643
1644 /* allocate a protection domain if a device is added */
1645 dma_domain = find_protection_domain(devid);
1646 if (dma_domain)
1647 goto out;
1648 dma_domain = dma_ops_domain_alloc();
1649 if (!dma_domain)
1650 goto out;
1651 dma_domain->target_dev = devid;
1652
1653 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1654 list_add_tail(&dma_domain->list, &iommu_pd_list);
1655 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1656
1657 break;
1658 case BUS_NOTIFY_DEL_DEVICE:
1659
1660 iommu_uninit_device(dev);
1661
1662 default:
1663 goto out;
1664 }
1665
1666 iommu_flush_device(dev);
1667 iommu_completion_wait(iommu);
1668
1669 out:
1670 return 0;
1671 }
1672
1673 static struct notifier_block device_nb = {
1674 .notifier_call = device_change_notifier,
1675 };
1676
1677 void amd_iommu_init_notifier(void)
1678 {
1679 bus_register_notifier(&pci_bus_type, &device_nb);
1680 }
1681
1682 /*****************************************************************************
1683 *
1684 * The next functions belong to the dma_ops mapping/unmapping code.
1685 *
1686 *****************************************************************************/
1687
1688 /*
1689 * In the dma_ops path we only have the struct device. This function
1690 * finds the corresponding IOMMU, the protection domain and the
1691 * requestor id for a given device.
1692 * If the device is not yet associated with a domain this is also done
1693 * in this function.
1694 */
1695 static struct protection_domain *get_domain(struct device *dev)
1696 {
1697 struct protection_domain *domain;
1698 struct dma_ops_domain *dma_dom;
1699 u16 devid = get_device_id(dev);
1700
1701 if (!check_device(dev))
1702 return ERR_PTR(-EINVAL);
1703
1704 domain = domain_for_device(dev);
1705 if (domain != NULL && !dma_ops_domain(domain))
1706 return ERR_PTR(-EBUSY);
1707
1708 if (domain != NULL)
1709 return domain;
1710
1711 /* Device not bount yet - bind it */
1712 dma_dom = find_protection_domain(devid);
1713 if (!dma_dom)
1714 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1715 attach_device(dev, &dma_dom->domain);
1716 DUMP_printk("Using protection domain %d for device %s\n",
1717 dma_dom->domain.id, dev_name(dev));
1718
1719 return &dma_dom->domain;
1720 }
1721
1722 static void update_device_table(struct protection_domain *domain)
1723 {
1724 struct iommu_dev_data *dev_data;
1725
1726 list_for_each_entry(dev_data, &domain->dev_list, list) {
1727 u16 devid = get_device_id(dev_data->dev);
1728 set_dte_entry(devid, domain);
1729 }
1730 }
1731
1732 static void update_domain(struct protection_domain *domain)
1733 {
1734 if (!domain->updated)
1735 return;
1736
1737 update_device_table(domain);
1738
1739 domain_flush_devices(domain);
1740 domain_flush_tlb_pde(domain);
1741
1742 domain->updated = false;
1743 }
1744
1745 /*
1746 * This function fetches the PTE for a given address in the aperture
1747 */
1748 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1749 unsigned long address)
1750 {
1751 struct aperture_range *aperture;
1752 u64 *pte, *pte_page;
1753
1754 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1755 if (!aperture)
1756 return NULL;
1757
1758 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1759 if (!pte) {
1760 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1761 GFP_ATOMIC);
1762 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1763 } else
1764 pte += PM_LEVEL_INDEX(0, address);
1765
1766 update_domain(&dom->domain);
1767
1768 return pte;
1769 }
1770
1771 /*
1772 * This is the generic map function. It maps one 4kb page at paddr to
1773 * the given address in the DMA address space for the domain.
1774 */
1775 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1776 unsigned long address,
1777 phys_addr_t paddr,
1778 int direction)
1779 {
1780 u64 *pte, __pte;
1781
1782 WARN_ON(address > dom->aperture_size);
1783
1784 paddr &= PAGE_MASK;
1785
1786 pte = dma_ops_get_pte(dom, address);
1787 if (!pte)
1788 return DMA_ERROR_CODE;
1789
1790 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1791
1792 if (direction == DMA_TO_DEVICE)
1793 __pte |= IOMMU_PTE_IR;
1794 else if (direction == DMA_FROM_DEVICE)
1795 __pte |= IOMMU_PTE_IW;
1796 else if (direction == DMA_BIDIRECTIONAL)
1797 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1798
1799 WARN_ON(*pte);
1800
1801 *pte = __pte;
1802
1803 return (dma_addr_t)address;
1804 }
1805
1806 /*
1807 * The generic unmapping function for on page in the DMA address space.
1808 */
1809 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1810 unsigned long address)
1811 {
1812 struct aperture_range *aperture;
1813 u64 *pte;
1814
1815 if (address >= dom->aperture_size)
1816 return;
1817
1818 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1819 if (!aperture)
1820 return;
1821
1822 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1823 if (!pte)
1824 return;
1825
1826 pte += PM_LEVEL_INDEX(0, address);
1827
1828 WARN_ON(!*pte);
1829
1830 *pte = 0ULL;
1831 }
1832
1833 /*
1834 * This function contains common code for mapping of a physically
1835 * contiguous memory region into DMA address space. It is used by all
1836 * mapping functions provided with this IOMMU driver.
1837 * Must be called with the domain lock held.
1838 */
1839 static dma_addr_t __map_single(struct device *dev,
1840 struct dma_ops_domain *dma_dom,
1841 phys_addr_t paddr,
1842 size_t size,
1843 int dir,
1844 bool align,
1845 u64 dma_mask)
1846 {
1847 dma_addr_t offset = paddr & ~PAGE_MASK;
1848 dma_addr_t address, start, ret;
1849 unsigned int pages;
1850 unsigned long align_mask = 0;
1851 int i;
1852
1853 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1854 paddr &= PAGE_MASK;
1855
1856 INC_STATS_COUNTER(total_map_requests);
1857
1858 if (pages > 1)
1859 INC_STATS_COUNTER(cross_page);
1860
1861 if (align)
1862 align_mask = (1UL << get_order(size)) - 1;
1863
1864 retry:
1865 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1866 dma_mask);
1867 if (unlikely(address == DMA_ERROR_CODE)) {
1868 /*
1869 * setting next_address here will let the address
1870 * allocator only scan the new allocated range in the
1871 * first run. This is a small optimization.
1872 */
1873 dma_dom->next_address = dma_dom->aperture_size;
1874
1875 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1876 goto out;
1877
1878 /*
1879 * aperture was successfully enlarged by 128 MB, try
1880 * allocation again
1881 */
1882 goto retry;
1883 }
1884
1885 start = address;
1886 for (i = 0; i < pages; ++i) {
1887 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1888 if (ret == DMA_ERROR_CODE)
1889 goto out_unmap;
1890
1891 paddr += PAGE_SIZE;
1892 start += PAGE_SIZE;
1893 }
1894 address += offset;
1895
1896 ADD_STATS_COUNTER(alloced_io_mem, size);
1897
1898 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1899 domain_flush_tlb(&dma_dom->domain);
1900 dma_dom->need_flush = false;
1901 } else if (unlikely(amd_iommu_np_cache))
1902 domain_flush_pages(&dma_dom->domain, address, size);
1903
1904 out:
1905 return address;
1906
1907 out_unmap:
1908
1909 for (--i; i >= 0; --i) {
1910 start -= PAGE_SIZE;
1911 dma_ops_domain_unmap(dma_dom, start);
1912 }
1913
1914 dma_ops_free_addresses(dma_dom, address, pages);
1915
1916 return DMA_ERROR_CODE;
1917 }
1918
1919 /*
1920 * Does the reverse of the __map_single function. Must be called with
1921 * the domain lock held too
1922 */
1923 static void __unmap_single(struct dma_ops_domain *dma_dom,
1924 dma_addr_t dma_addr,
1925 size_t size,
1926 int dir)
1927 {
1928 dma_addr_t flush_addr;
1929 dma_addr_t i, start;
1930 unsigned int pages;
1931
1932 if ((dma_addr == DMA_ERROR_CODE) ||
1933 (dma_addr + size > dma_dom->aperture_size))
1934 return;
1935
1936 flush_addr = dma_addr;
1937 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1938 dma_addr &= PAGE_MASK;
1939 start = dma_addr;
1940
1941 for (i = 0; i < pages; ++i) {
1942 dma_ops_domain_unmap(dma_dom, start);
1943 start += PAGE_SIZE;
1944 }
1945
1946 SUB_STATS_COUNTER(alloced_io_mem, size);
1947
1948 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1949
1950 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1951 domain_flush_pages(&dma_dom->domain, flush_addr, size);
1952 dma_dom->need_flush = false;
1953 }
1954 }
1955
1956 /*
1957 * The exported map_single function for dma_ops.
1958 */
1959 static dma_addr_t map_page(struct device *dev, struct page *page,
1960 unsigned long offset, size_t size,
1961 enum dma_data_direction dir,
1962 struct dma_attrs *attrs)
1963 {
1964 unsigned long flags;
1965 struct protection_domain *domain;
1966 dma_addr_t addr;
1967 u64 dma_mask;
1968 phys_addr_t paddr = page_to_phys(page) + offset;
1969
1970 INC_STATS_COUNTER(cnt_map_single);
1971
1972 domain = get_domain(dev);
1973 if (PTR_ERR(domain) == -EINVAL)
1974 return (dma_addr_t)paddr;
1975 else if (IS_ERR(domain))
1976 return DMA_ERROR_CODE;
1977
1978 dma_mask = *dev->dma_mask;
1979
1980 spin_lock_irqsave(&domain->lock, flags);
1981
1982 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1983 dma_mask);
1984 if (addr == DMA_ERROR_CODE)
1985 goto out;
1986
1987 domain_flush_complete(domain);
1988
1989 out:
1990 spin_unlock_irqrestore(&domain->lock, flags);
1991
1992 return addr;
1993 }
1994
1995 /*
1996 * The exported unmap_single function for dma_ops.
1997 */
1998 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1999 enum dma_data_direction dir, struct dma_attrs *attrs)
2000 {
2001 unsigned long flags;
2002 struct protection_domain *domain;
2003
2004 INC_STATS_COUNTER(cnt_unmap_single);
2005
2006 domain = get_domain(dev);
2007 if (IS_ERR(domain))
2008 return;
2009
2010 spin_lock_irqsave(&domain->lock, flags);
2011
2012 __unmap_single(domain->priv, dma_addr, size, dir);
2013
2014 domain_flush_complete(domain);
2015
2016 spin_unlock_irqrestore(&domain->lock, flags);
2017 }
2018
2019 /*
2020 * This is a special map_sg function which is used if we should map a
2021 * device which is not handled by an AMD IOMMU in the system.
2022 */
2023 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2024 int nelems, int dir)
2025 {
2026 struct scatterlist *s;
2027 int i;
2028
2029 for_each_sg(sglist, s, nelems, i) {
2030 s->dma_address = (dma_addr_t)sg_phys(s);
2031 s->dma_length = s->length;
2032 }
2033
2034 return nelems;
2035 }
2036
2037 /*
2038 * The exported map_sg function for dma_ops (handles scatter-gather
2039 * lists).
2040 */
2041 static int map_sg(struct device *dev, struct scatterlist *sglist,
2042 int nelems, enum dma_data_direction dir,
2043 struct dma_attrs *attrs)
2044 {
2045 unsigned long flags;
2046 struct protection_domain *domain;
2047 int i;
2048 struct scatterlist *s;
2049 phys_addr_t paddr;
2050 int mapped_elems = 0;
2051 u64 dma_mask;
2052
2053 INC_STATS_COUNTER(cnt_map_sg);
2054
2055 domain = get_domain(dev);
2056 if (PTR_ERR(domain) == -EINVAL)
2057 return map_sg_no_iommu(dev, sglist, nelems, dir);
2058 else if (IS_ERR(domain))
2059 return 0;
2060
2061 dma_mask = *dev->dma_mask;
2062
2063 spin_lock_irqsave(&domain->lock, flags);
2064
2065 for_each_sg(sglist, s, nelems, i) {
2066 paddr = sg_phys(s);
2067
2068 s->dma_address = __map_single(dev, domain->priv,
2069 paddr, s->length, dir, false,
2070 dma_mask);
2071
2072 if (s->dma_address) {
2073 s->dma_length = s->length;
2074 mapped_elems++;
2075 } else
2076 goto unmap;
2077 }
2078
2079 domain_flush_complete(domain);
2080
2081 out:
2082 spin_unlock_irqrestore(&domain->lock, flags);
2083
2084 return mapped_elems;
2085 unmap:
2086 for_each_sg(sglist, s, mapped_elems, i) {
2087 if (s->dma_address)
2088 __unmap_single(domain->priv, s->dma_address,
2089 s->dma_length, dir);
2090 s->dma_address = s->dma_length = 0;
2091 }
2092
2093 mapped_elems = 0;
2094
2095 goto out;
2096 }
2097
2098 /*
2099 * The exported map_sg function for dma_ops (handles scatter-gather
2100 * lists).
2101 */
2102 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2103 int nelems, enum dma_data_direction dir,
2104 struct dma_attrs *attrs)
2105 {
2106 unsigned long flags;
2107 struct protection_domain *domain;
2108 struct scatterlist *s;
2109 int i;
2110
2111 INC_STATS_COUNTER(cnt_unmap_sg);
2112
2113 domain = get_domain(dev);
2114 if (IS_ERR(domain))
2115 return;
2116
2117 spin_lock_irqsave(&domain->lock, flags);
2118
2119 for_each_sg(sglist, s, nelems, i) {
2120 __unmap_single(domain->priv, s->dma_address,
2121 s->dma_length, dir);
2122 s->dma_address = s->dma_length = 0;
2123 }
2124
2125 domain_flush_complete(domain);
2126
2127 spin_unlock_irqrestore(&domain->lock, flags);
2128 }
2129
2130 /*
2131 * The exported alloc_coherent function for dma_ops.
2132 */
2133 static void *alloc_coherent(struct device *dev, size_t size,
2134 dma_addr_t *dma_addr, gfp_t flag)
2135 {
2136 unsigned long flags;
2137 void *virt_addr;
2138 struct protection_domain *domain;
2139 phys_addr_t paddr;
2140 u64 dma_mask = dev->coherent_dma_mask;
2141
2142 INC_STATS_COUNTER(cnt_alloc_coherent);
2143
2144 domain = get_domain(dev);
2145 if (PTR_ERR(domain) == -EINVAL) {
2146 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2147 *dma_addr = __pa(virt_addr);
2148 return virt_addr;
2149 } else if (IS_ERR(domain))
2150 return NULL;
2151
2152 dma_mask = dev->coherent_dma_mask;
2153 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2154 flag |= __GFP_ZERO;
2155
2156 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2157 if (!virt_addr)
2158 return NULL;
2159
2160 paddr = virt_to_phys(virt_addr);
2161
2162 if (!dma_mask)
2163 dma_mask = *dev->dma_mask;
2164
2165 spin_lock_irqsave(&domain->lock, flags);
2166
2167 *dma_addr = __map_single(dev, domain->priv, paddr,
2168 size, DMA_BIDIRECTIONAL, true, dma_mask);
2169
2170 if (*dma_addr == DMA_ERROR_CODE) {
2171 spin_unlock_irqrestore(&domain->lock, flags);
2172 goto out_free;
2173 }
2174
2175 domain_flush_complete(domain);
2176
2177 spin_unlock_irqrestore(&domain->lock, flags);
2178
2179 return virt_addr;
2180
2181 out_free:
2182
2183 free_pages((unsigned long)virt_addr, get_order(size));
2184
2185 return NULL;
2186 }
2187
2188 /*
2189 * The exported free_coherent function for dma_ops.
2190 */
2191 static void free_coherent(struct device *dev, size_t size,
2192 void *virt_addr, dma_addr_t dma_addr)
2193 {
2194 unsigned long flags;
2195 struct protection_domain *domain;
2196
2197 INC_STATS_COUNTER(cnt_free_coherent);
2198
2199 domain = get_domain(dev);
2200 if (IS_ERR(domain))
2201 goto free_mem;
2202
2203 spin_lock_irqsave(&domain->lock, flags);
2204
2205 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2206
2207 domain_flush_complete(domain);
2208
2209 spin_unlock_irqrestore(&domain->lock, flags);
2210
2211 free_mem:
2212 free_pages((unsigned long)virt_addr, get_order(size));
2213 }
2214
2215 /*
2216 * This function is called by the DMA layer to find out if we can handle a
2217 * particular device. It is part of the dma_ops.
2218 */
2219 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2220 {
2221 return check_device(dev);
2222 }
2223
2224 /*
2225 * The function for pre-allocating protection domains.
2226 *
2227 * If the driver core informs the DMA layer if a driver grabs a device
2228 * we don't need to preallocate the protection domains anymore.
2229 * For now we have to.
2230 */
2231 static void prealloc_protection_domains(void)
2232 {
2233 struct pci_dev *dev = NULL;
2234 struct dma_ops_domain *dma_dom;
2235 u16 devid;
2236
2237 for_each_pci_dev(dev) {
2238
2239 /* Do we handle this device? */
2240 if (!check_device(&dev->dev))
2241 continue;
2242
2243 /* Is there already any domain for it? */
2244 if (domain_for_device(&dev->dev))
2245 continue;
2246
2247 devid = get_device_id(&dev->dev);
2248
2249 dma_dom = dma_ops_domain_alloc();
2250 if (!dma_dom)
2251 continue;
2252 init_unity_mappings_for_device(dma_dom, devid);
2253 dma_dom->target_dev = devid;
2254
2255 attach_device(&dev->dev, &dma_dom->domain);
2256
2257 list_add_tail(&dma_dom->list, &iommu_pd_list);
2258 }
2259 }
2260
2261 static struct dma_map_ops amd_iommu_dma_ops = {
2262 .alloc_coherent = alloc_coherent,
2263 .free_coherent = free_coherent,
2264 .map_page = map_page,
2265 .unmap_page = unmap_page,
2266 .map_sg = map_sg,
2267 .unmap_sg = unmap_sg,
2268 .dma_supported = amd_iommu_dma_supported,
2269 };
2270
2271 /*
2272 * The function which clues the AMD IOMMU driver into dma_ops.
2273 */
2274
2275 void __init amd_iommu_init_api(void)
2276 {
2277 register_iommu(&amd_iommu_ops);
2278 }
2279
2280 int __init amd_iommu_init_dma_ops(void)
2281 {
2282 struct amd_iommu *iommu;
2283 int ret;
2284
2285 /*
2286 * first allocate a default protection domain for every IOMMU we
2287 * found in the system. Devices not assigned to any other
2288 * protection domain will be assigned to the default one.
2289 */
2290 for_each_iommu(iommu) {
2291 iommu->default_dom = dma_ops_domain_alloc();
2292 if (iommu->default_dom == NULL)
2293 return -ENOMEM;
2294 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2295 ret = iommu_init_unity_mappings(iommu);
2296 if (ret)
2297 goto free_domains;
2298 }
2299
2300 /*
2301 * Pre-allocate the protection domains for each device.
2302 */
2303 prealloc_protection_domains();
2304
2305 iommu_detected = 1;
2306 swiotlb = 0;
2307
2308 /* Make the driver finally visible to the drivers */
2309 dma_ops = &amd_iommu_dma_ops;
2310
2311 amd_iommu_stats_init();
2312
2313 return 0;
2314
2315 free_domains:
2316
2317 for_each_iommu(iommu) {
2318 if (iommu->default_dom)
2319 dma_ops_domain_free(iommu->default_dom);
2320 }
2321
2322 return ret;
2323 }
2324
2325 /*****************************************************************************
2326 *
2327 * The following functions belong to the exported interface of AMD IOMMU
2328 *
2329 * This interface allows access to lower level functions of the IOMMU
2330 * like protection domain handling and assignement of devices to domains
2331 * which is not possible with the dma_ops interface.
2332 *
2333 *****************************************************************************/
2334
2335 static void cleanup_domain(struct protection_domain *domain)
2336 {
2337 struct iommu_dev_data *dev_data, *next;
2338 unsigned long flags;
2339
2340 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2341
2342 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2343 struct device *dev = dev_data->dev;
2344
2345 __detach_device(dev);
2346 atomic_set(&dev_data->bind, 0);
2347 }
2348
2349 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2350 }
2351
2352 static void protection_domain_free(struct protection_domain *domain)
2353 {
2354 if (!domain)
2355 return;
2356
2357 del_domain_from_list(domain);
2358
2359 if (domain->id)
2360 domain_id_free(domain->id);
2361
2362 kfree(domain);
2363 }
2364
2365 static struct protection_domain *protection_domain_alloc(void)
2366 {
2367 struct protection_domain *domain;
2368
2369 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2370 if (!domain)
2371 return NULL;
2372
2373 spin_lock_init(&domain->lock);
2374 mutex_init(&domain->api_lock);
2375 domain->id = domain_id_alloc();
2376 if (!domain->id)
2377 goto out_err;
2378 INIT_LIST_HEAD(&domain->dev_list);
2379
2380 add_domain_to_list(domain);
2381
2382 return domain;
2383
2384 out_err:
2385 kfree(domain);
2386
2387 return NULL;
2388 }
2389
2390 static int amd_iommu_domain_init(struct iommu_domain *dom)
2391 {
2392 struct protection_domain *domain;
2393
2394 domain = protection_domain_alloc();
2395 if (!domain)
2396 goto out_free;
2397
2398 domain->mode = PAGE_MODE_3_LEVEL;
2399 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2400 if (!domain->pt_root)
2401 goto out_free;
2402
2403 dom->priv = domain;
2404
2405 return 0;
2406
2407 out_free:
2408 protection_domain_free(domain);
2409
2410 return -ENOMEM;
2411 }
2412
2413 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2414 {
2415 struct protection_domain *domain = dom->priv;
2416
2417 if (!domain)
2418 return;
2419
2420 if (domain->dev_cnt > 0)
2421 cleanup_domain(domain);
2422
2423 BUG_ON(domain->dev_cnt != 0);
2424
2425 free_pagetable(domain);
2426
2427 protection_domain_free(domain);
2428
2429 dom->priv = NULL;
2430 }
2431
2432 static void amd_iommu_detach_device(struct iommu_domain *dom,
2433 struct device *dev)
2434 {
2435 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2436 struct amd_iommu *iommu;
2437 u16 devid;
2438
2439 if (!check_device(dev))
2440 return;
2441
2442 devid = get_device_id(dev);
2443
2444 if (dev_data->domain != NULL)
2445 detach_device(dev);
2446
2447 iommu = amd_iommu_rlookup_table[devid];
2448 if (!iommu)
2449 return;
2450
2451 iommu_flush_device(dev);
2452 iommu_completion_wait(iommu);
2453 }
2454
2455 static int amd_iommu_attach_device(struct iommu_domain *dom,
2456 struct device *dev)
2457 {
2458 struct protection_domain *domain = dom->priv;
2459 struct iommu_dev_data *dev_data;
2460 struct amd_iommu *iommu;
2461 int ret;
2462 u16 devid;
2463
2464 if (!check_device(dev))
2465 return -EINVAL;
2466
2467 dev_data = dev->archdata.iommu;
2468
2469 devid = get_device_id(dev);
2470
2471 iommu = amd_iommu_rlookup_table[devid];
2472 if (!iommu)
2473 return -EINVAL;
2474
2475 if (dev_data->domain)
2476 detach_device(dev);
2477
2478 ret = attach_device(dev, domain);
2479
2480 iommu_completion_wait(iommu);
2481
2482 return ret;
2483 }
2484
2485 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2486 phys_addr_t paddr, int gfp_order, int iommu_prot)
2487 {
2488 unsigned long page_size = 0x1000UL << gfp_order;
2489 struct protection_domain *domain = dom->priv;
2490 int prot = 0;
2491 int ret;
2492
2493 if (iommu_prot & IOMMU_READ)
2494 prot |= IOMMU_PROT_IR;
2495 if (iommu_prot & IOMMU_WRITE)
2496 prot |= IOMMU_PROT_IW;
2497
2498 mutex_lock(&domain->api_lock);
2499 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2500 mutex_unlock(&domain->api_lock);
2501
2502 return ret;
2503 }
2504
2505 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2506 int gfp_order)
2507 {
2508 struct protection_domain *domain = dom->priv;
2509 unsigned long page_size, unmap_size;
2510
2511 page_size = 0x1000UL << gfp_order;
2512
2513 mutex_lock(&domain->api_lock);
2514 unmap_size = iommu_unmap_page(domain, iova, page_size);
2515 mutex_unlock(&domain->api_lock);
2516
2517 domain_flush_tlb_pde(domain);
2518
2519 return get_order(unmap_size);
2520 }
2521
2522 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2523 unsigned long iova)
2524 {
2525 struct protection_domain *domain = dom->priv;
2526 unsigned long offset_mask;
2527 phys_addr_t paddr;
2528 u64 *pte, __pte;
2529
2530 pte = fetch_pte(domain, iova);
2531
2532 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2533 return 0;
2534
2535 if (PM_PTE_LEVEL(*pte) == 0)
2536 offset_mask = PAGE_SIZE - 1;
2537 else
2538 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2539
2540 __pte = *pte & PM_ADDR_MASK;
2541 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2542
2543 return paddr;
2544 }
2545
2546 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2547 unsigned long cap)
2548 {
2549 switch (cap) {
2550 case IOMMU_CAP_CACHE_COHERENCY:
2551 return 1;
2552 }
2553
2554 return 0;
2555 }
2556
2557 static struct iommu_ops amd_iommu_ops = {
2558 .domain_init = amd_iommu_domain_init,
2559 .domain_destroy = amd_iommu_domain_destroy,
2560 .attach_dev = amd_iommu_attach_device,
2561 .detach_dev = amd_iommu_detach_device,
2562 .map = amd_iommu_map,
2563 .unmap = amd_iommu_unmap,
2564 .iova_to_phys = amd_iommu_iova_to_phys,
2565 .domain_has_cap = amd_iommu_domain_has_cap,
2566 };
2567
2568 /*****************************************************************************
2569 *
2570 * The next functions do a basic initialization of IOMMU for pass through
2571 * mode
2572 *
2573 * In passthrough mode the IOMMU is initialized and enabled but not used for
2574 * DMA-API translation.
2575 *
2576 *****************************************************************************/
2577
2578 int __init amd_iommu_init_passthrough(void)
2579 {
2580 struct amd_iommu *iommu;
2581 struct pci_dev *dev = NULL;
2582 u16 devid;
2583
2584 /* allocate passthrough domain */
2585 pt_domain = protection_domain_alloc();
2586 if (!pt_domain)
2587 return -ENOMEM;
2588
2589 pt_domain->mode |= PAGE_MODE_NONE;
2590
2591 for_each_pci_dev(dev) {
2592 if (!check_device(&dev->dev))
2593 continue;
2594
2595 devid = get_device_id(&dev->dev);
2596
2597 iommu = amd_iommu_rlookup_table[devid];
2598 if (!iommu)
2599 continue;
2600
2601 attach_device(&dev->dev, pt_domain);
2602 }
2603
2604 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
2605
2606 return 0;
2607 }
Linux with added FPC-III support