drivers/net/wireless/ath/ath10k/core.h

   1 /*
   2  * Copyright (c) 2005-2011 Atheros Communications Inc.
   3  * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
   4  *
   5  * Permission to use, copy, modify, and/or distribute this software for any
   6  * purpose with or without fee is hereby granted, provided that the above
   7  * copyright notice and this permission notice appear in all copies.
   8  *
   9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16  */
  17
  18 #ifndef _CORE_H_
  19 #define _CORE_H_
  20
  21 #include <linux/completion.h>
  22 #include <linux/if_ether.h>
  23 #include <linux/types.h>
  24 #include <linux/pci.h>
  25 #include <linux/uuid.h>
  26 #include <linux/time.h>
  27
  28 #include "htt.h"
  29 #include "htc.h"
  30 #include "hw.h"
  31 #include "targaddrs.h"
  32 #include "wmi.h"
  33 #include "../ath.h"
  34 #include "../regd.h"
  35 #include "../dfs_pattern_detector.h"
  36 #include "spectral.h"
  37 #include "thermal.h"
  38 #include "wow.h"
  39 #include "swap.h"
  40
  41 #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
  42 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
  43 #define WO(_f)      ((_f##_OFFSET) >> 2)
  44
  45 #define ATH10K_SCAN_ID 0
  46 #define WMI_READY_TIMEOUT (5 * HZ)
  47 #define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
  48 #define ATH10K_CONNECTION_LOSS_HZ (3*HZ)
  49 #define ATH10K_NUM_CHANS 39
  50
  51 /* Antenna noise floor */
  52 #define ATH10K_DEFAULT_NOISE_FLOOR -95
  53
  54 #define ATH10K_MAX_NUM_MGMT_PENDING 128
  55
  56 /* number of failed packets (20 packets with 16 sw reties each) */
  57 #define ATH10K_KICKOUT_THRESHOLD (20 * 16)
  58
  59 /*
  60  * Use insanely high numbers to make sure that the firmware implementation
  61  * won't start, we have the same functionality already in hostapd. Unit
  62  * is seconds.
  63  */
  64 #define ATH10K_KEEPALIVE_MIN_IDLE 3747
  65 #define ATH10K_KEEPALIVE_MAX_IDLE 3895
  66 #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900
  67
  68 struct ath10k;
  69
  70 enum ath10k_bus {
  71         ATH10K_BUS_PCI,
  72 };
  73
  74 static inline const char *ath10k_bus_str(enum ath10k_bus bus)
  75 {
  76         switch (bus) {
  77         case ATH10K_BUS_PCI:
  78                 return "pci";
  79         }
  80
  81         return "unknown";
  82 }
  83
  84 struct ath10k_skb_cb {
  85         dma_addr_t paddr;
  86         u8 eid;
  87         u8 vdev_id;
  88         enum ath10k_hw_txrx_mode txmode;
  89         bool is_protected;
  90
  91         struct {
  92                 u8 tid;
  93                 u16 freq;
  94                 bool is_offchan;
  95                 bool nohwcrypt;
  96                 struct ath10k_htt_txbuf *txbuf;
  97                 u32 txbuf_paddr;
  98         } __packed htt;
  99
 100         struct {
 101                 bool dtim_zero;
 102                 bool deliver_cab;
 103         } bcn;
 104 } __packed;
 105
 106 struct ath10k_skb_rxcb {
 107         dma_addr_t paddr;
 108         struct hlist_node hlist;
 109 };
 110
 111 static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
 112 {
 113         BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
 114                      IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
 115         return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
 116 }
 117
 118 static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb)
 119 {
 120         BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb));
 121         return (struct ath10k_skb_rxcb *)skb->cb;
 122 }
 123
 124 #define ATH10K_RXCB_SKB(rxcb) \
 125                 container_of((void *)rxcb, struct sk_buff, cb)
 126
 127 static inline u32 host_interest_item_address(u32 item_offset)
 128 {
 129         return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
 130 }
 131
 132 struct ath10k_bmi {
 133         bool done_sent;
 134 };
 135
 136 struct ath10k_mem_chunk {
 137         void *vaddr;
 138         dma_addr_t paddr;
 139         u32 len;
 140         u32 req_id;
 141 };
 142
 143 struct ath10k_wmi {
 144         enum ath10k_fw_wmi_op_version op_version;
 145         enum ath10k_htc_ep_id eid;
 146         struct completion service_ready;
 147         struct completion unified_ready;
 148         wait_queue_head_t tx_credits_wq;
 149         DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX);
 150         struct wmi_cmd_map *cmd;
 151         struct wmi_vdev_param_map *vdev_param;
 152         struct wmi_pdev_param_map *pdev_param;
 153         const struct wmi_ops *ops;
 154
 155         u32 num_mem_chunks;
 156         u32 rx_decap_mode;
 157         struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS];
 158 };
 159
 160 struct ath10k_fw_stats_peer {
 161         struct list_head list;
 162
 163         u8 peer_macaddr[ETH_ALEN];
 164         u32 peer_rssi;
 165         u32 peer_tx_rate;
 166         u32 peer_rx_rate; /* 10x only */
 167 };
 168
 169 struct ath10k_fw_stats_vdev {
 170         struct list_head list;
 171
 172         u32 vdev_id;
 173         u32 beacon_snr;
 174         u32 data_snr;
 175         u32 num_tx_frames[4];
 176         u32 num_rx_frames;
 177         u32 num_tx_frames_retries[4];
 178         u32 num_tx_frames_failures[4];
 179         u32 num_rts_fail;
 180         u32 num_rts_success;
 181         u32 num_rx_err;
 182         u32 num_rx_discard;
 183         u32 num_tx_not_acked;
 184         u32 tx_rate_history[10];
 185         u32 beacon_rssi_history[10];
 186 };
 187
 188 struct ath10k_fw_stats_pdev {
 189         struct list_head list;
 190
 191         /* PDEV stats */
 192         s32 ch_noise_floor;
 193         u32 tx_frame_count;
 194         u32 rx_frame_count;
 195         u32 rx_clear_count;
 196         u32 cycle_count;
 197         u32 phy_err_count;
 198         u32 chan_tx_power;
 199         u32 ack_rx_bad;
 200         u32 rts_bad;
 201         u32 rts_good;
 202         u32 fcs_bad;
 203         u32 no_beacons;
 204         u32 mib_int_count;
 205
 206         /* PDEV TX stats */
 207         s32 comp_queued;
 208         s32 comp_delivered;
 209         s32 msdu_enqued;
 210         s32 mpdu_enqued;
 211         s32 wmm_drop;
 212         s32 local_enqued;
 213         s32 local_freed;
 214         s32 hw_queued;
 215         s32 hw_reaped;
 216         s32 underrun;
 217         u32 hw_paused;
 218         s32 tx_abort;
 219         s32 mpdus_requed;
 220         u32 tx_ko;
 221         u32 data_rc;
 222         u32 self_triggers;
 223         u32 sw_retry_failure;
 224         u32 illgl_rate_phy_err;
 225         u32 pdev_cont_xretry;
 226         u32 pdev_tx_timeout;
 227         u32 pdev_resets;
 228         u32 phy_underrun;
 229         u32 txop_ovf;
 230         u32 seq_posted;
 231         u32 seq_failed_queueing;
 232         u32 seq_completed;
 233         u32 seq_restarted;
 234         u32 mu_seq_posted;
 235         u32 mpdus_sw_flush;
 236         u32 mpdus_hw_filter;
 237         u32 mpdus_truncated;
 238         u32 mpdus_ack_failed;
 239         u32 mpdus_expired;
 240
 241         /* PDEV RX stats */
 242         s32 mid_ppdu_route_change;
 243         s32 status_rcvd;
 244         s32 r0_frags;
 245         s32 r1_frags;
 246         s32 r2_frags;
 247         s32 r3_frags;
 248         s32 htt_msdus;
 249         s32 htt_mpdus;
 250         s32 loc_msdus;
 251         s32 loc_mpdus;
 252         s32 oversize_amsdu;
 253         s32 phy_errs;
 254         s32 phy_err_drop;
 255         s32 mpdu_errs;
 256         s32 rx_ovfl_errs;
 257 };
 258
 259 struct ath10k_fw_stats {
 260         struct list_head pdevs;
 261         struct list_head vdevs;
 262         struct list_head peers;
 263 };
 264
 265 #define ATH10K_TPC_TABLE_TYPE_FLAG      1
 266 #define ATH10K_TPC_PREAM_TABLE_END      0xFFFF
 267
 268 struct ath10k_tpc_table {
 269         u32 pream_idx[WMI_TPC_RATE_MAX];
 270         u8 rate_code[WMI_TPC_RATE_MAX];
 271         char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE];
 272 };
 273
 274 struct ath10k_tpc_stats {
 275         u32 reg_domain;
 276         u32 chan_freq;
 277         u32 phy_mode;
 278         u32 twice_antenna_reduction;
 279         u32 twice_max_rd_power;
 280         s32 twice_antenna_gain;
 281         u32 power_limit;
 282         u32 num_tx_chain;
 283         u32 ctl;
 284         u32 rate_max;
 285         u8 flag[WMI_TPC_FLAG];
 286         struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG];
 287 };
 288
 289 struct ath10k_dfs_stats {
 290         u32 phy_errors;
 291         u32 pulses_total;
 292         u32 pulses_detected;
 293         u32 pulses_discarded;
 294         u32 radar_detected;
 295 };
 296
 297 #define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
 298
 299 struct ath10k_peer {
 300         struct list_head list;
 301         int vdev_id;
 302         u8 addr[ETH_ALEN];
 303         DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
 304
 305         /* protected by ar->data_lock */
 306         struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
 307 };
 308
 309 struct ath10k_sta {
 310         struct ath10k_vif *arvif;
 311
 312         /* the following are protected by ar->data_lock */
 313         u32 changed; /* IEEE80211_RC_* */
 314         u32 bw;
 315         u32 nss;
 316         u32 smps;
 317
 318         struct work_struct update_wk;
 319
 320 #ifdef CONFIG_MAC80211_DEBUGFS
 321         /* protected by conf_mutex */
 322         bool aggr_mode;
 323 #endif
 324 };
 325
 326 #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
 327
 328 enum ath10k_beacon_state {
 329         ATH10K_BEACON_SCHEDULED = 0,
 330         ATH10K_BEACON_SENDING,
 331         ATH10K_BEACON_SENT,
 332 };
 333
 334 struct ath10k_vif {
 335         struct list_head list;
 336
 337         u32 vdev_id;
 338         enum wmi_vdev_type vdev_type;
 339         enum wmi_vdev_subtype vdev_subtype;
 340         u32 beacon_interval;
 341         u32 dtim_period;
 342         struct sk_buff *beacon;
 343         /* protected by data_lock */
 344         enum ath10k_beacon_state beacon_state;
 345         void *beacon_buf;
 346         dma_addr_t beacon_paddr;
 347         unsigned long tx_paused; /* arbitrary values defined by target */
 348
 349         struct ath10k *ar;
 350         struct ieee80211_vif *vif;
 351
 352         bool is_started;
 353         bool is_up;
 354         bool spectral_enabled;
 355         bool ps;
 356         u32 aid;
 357         u8 bssid[ETH_ALEN];
 358
 359         struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
 360         s8 def_wep_key_idx;
 361
 362         u16 tx_seq_no;
 363
 364         union {
 365                 struct {
 366                         u32 uapsd;
 367                 } sta;
 368                 struct {
 369                         /* 512 stations */
 370                         u8 tim_bitmap[64];
 371                         u8 tim_len;
 372                         u32 ssid_len;
 373                         u8 ssid[IEEE80211_MAX_SSID_LEN];
 374                         bool hidden_ssid;
 375                         /* P2P_IE with NoA attribute for P2P_GO case */
 376                         u32 noa_len;
 377                         u8 *noa_data;
 378                 } ap;
 379         } u;
 380
 381         bool use_cts_prot;
 382         bool nohwcrypt;
 383         int num_legacy_stations;
 384         int txpower;
 385         struct wmi_wmm_params_all_arg wmm_params;
 386         struct work_struct ap_csa_work;
 387         struct delayed_work connection_loss_work;
 388         struct cfg80211_bitrate_mask bitrate_mask;
 389 };
 390
 391 struct ath10k_vif_iter {
 392         u32 vdev_id;
 393         struct ath10k_vif *arvif;
 394 };
 395
 396 /* used for crash-dump storage, protected by data-lock */
 397 struct ath10k_fw_crash_data {
 398         bool crashed_since_read;
 399
 400         uuid_le uuid;
 401         struct timespec timestamp;
 402         __le32 registers[REG_DUMP_COUNT_QCA988X];
 403 };
 404
 405 struct ath10k_debug {
 406         struct dentry *debugfs_phy;
 407
 408         struct ath10k_fw_stats fw_stats;
 409         struct completion fw_stats_complete;
 410         bool fw_stats_done;
 411
 412         unsigned long htt_stats_mask;
 413         struct delayed_work htt_stats_dwork;
 414         struct ath10k_dfs_stats dfs_stats;
 415         struct ath_dfs_pool_stats dfs_pool_stats;
 416
 417         /* used for tpc-dump storage, protected by data-lock */
 418         struct ath10k_tpc_stats *tpc_stats;
 419
 420         struct completion tpc_complete;
 421
 422         /* protected by conf_mutex */
 423         u32 fw_dbglog_mask;
 424         u32 fw_dbglog_level;
 425         u32 pktlog_filter;
 426         u32 reg_addr;
 427         u32 nf_cal_period;
 428
 429         struct ath10k_fw_crash_data *fw_crash_data;
 430 };
 431
 432 enum ath10k_state {
 433         ATH10K_STATE_OFF = 0,
 434         ATH10K_STATE_ON,
 435
 436         /* When doing firmware recovery the device is first powered down.
 437          * mac80211 is supposed to call in to start() hook later on. It is
 438          * however possible that driver unloading and firmware crash overlap.
 439          * mac80211 can wait on conf_mutex in stop() while the device is
 440          * stopped in ath10k_core_restart() work holding conf_mutex. The state
 441          * RESTARTED means that the device is up and mac80211 has started hw
 442          * reconfiguration. Once mac80211 is done with the reconfiguration we
 443          * set the state to STATE_ON in reconfig_complete(). */
 444         ATH10K_STATE_RESTARTING,
 445         ATH10K_STATE_RESTARTED,
 446
 447         /* The device has crashed while restarting hw. This state is like ON
 448          * but commands are blocked in HTC and -ECOMM response is given. This
 449          * prevents completion timeouts and makes the driver more responsive to
 450          * userspace commands. This is also prevents recursive recovery. */
 451         ATH10K_STATE_WEDGED,
 452
 453         /* factory tests */
 454         ATH10K_STATE_UTF,
 455 };
 456
 457 enum ath10k_firmware_mode {
 458         /* the default mode, standard 802.11 functionality */
 459         ATH10K_FIRMWARE_MODE_NORMAL,
 460
 461         /* factory tests etc */
 462         ATH10K_FIRMWARE_MODE_UTF,
 463 };
 464
 465 enum ath10k_fw_features {
 466         /* wmi_mgmt_rx_hdr contains extra RSSI information */
 467         ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
 468
 469         /* Firmware from 10X branch. Deprecated, don't use in new code. */
 470         ATH10K_FW_FEATURE_WMI_10X = 1,
 471
 472         /* firmware support tx frame management over WMI, otherwise it's HTT */
 473         ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2,
 474
 475         /* Firmware does not support P2P */
 476         ATH10K_FW_FEATURE_NO_P2P = 3,
 477
 478         /* Firmware 10.2 feature bit. The ATH10K_FW_FEATURE_WMI_10X feature
 479          * bit is required to be set as well. Deprecated, don't use in new
 480          * code.
 481          */
 482         ATH10K_FW_FEATURE_WMI_10_2 = 4,
 483
 484         /* Some firmware revisions lack proper multi-interface client powersave
 485          * implementation. Enabling PS could result in connection drops,
 486          * traffic stalls, etc.
 487          */
 488         ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5,
 489
 490         /* Some firmware revisions have an incomplete WoWLAN implementation
 491          * despite WMI service bit being advertised. This feature flag is used
 492          * to distinguish whether WoWLAN is really supported or not.
 493          */
 494         ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6,
 495
 496         /* Don't trust error code from otp.bin */
 497         ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7,
 498
 499         /* Some firmware revisions pad 4th hw address to 4 byte boundary making
 500          * it 8 bytes long in Native Wifi Rx decap.
 501          */
 502         ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8,
 503
 504         /* Firmware supports bypassing PLL setting on init. */
 505         ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9,
 506
 507         /* Raw mode support. If supported, FW supports receiving and trasmitting
 508          * frames in raw mode.
 509          */
 510         ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10,
 511
 512         /* Firmware Supports Adaptive CCA*/
 513         ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11,
 514
 515         /* keep last */
 516         ATH10K_FW_FEATURE_COUNT,
 517 };
 518
 519 enum ath10k_dev_flags {
 520         /* Indicates that ath10k device is during CAC phase of DFS */
 521         ATH10K_CAC_RUNNING,
 522         ATH10K_FLAG_CORE_REGISTERED,
 523
 524         /* Device has crashed and needs to restart. This indicates any pending
 525          * waiters should immediately cancel instead of waiting for a time out.
 526          */
 527         ATH10K_FLAG_CRASH_FLUSH,
 528
 529         /* Use Raw mode instead of native WiFi Tx/Rx encap mode.
 530          * Raw mode supports both hardware and software crypto. Native WiFi only
 531          * supports hardware crypto.
 532          */
 533         ATH10K_FLAG_RAW_MODE,
 534
 535         /* Disable HW crypto engine */
 536         ATH10K_FLAG_HW_CRYPTO_DISABLED,
 537 };
 538
 539 enum ath10k_cal_mode {
 540         ATH10K_CAL_MODE_FILE,
 541         ATH10K_CAL_MODE_OTP,
 542         ATH10K_CAL_MODE_DT,
 543 };
 544
 545 enum ath10k_crypt_mode {
 546         /* Only use hardware crypto engine */
 547         ATH10K_CRYPT_MODE_HW,
 548         /* Only use software crypto engine */
 549         ATH10K_CRYPT_MODE_SW,
 550 };
 551
 552 static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode)
 553 {
 554         switch (mode) {
 555         case ATH10K_CAL_MODE_FILE:
 556                 return "file";
 557         case ATH10K_CAL_MODE_OTP:
 558                 return "otp";
 559         case ATH10K_CAL_MODE_DT:
 560                 return "dt";
 561         }
 562
 563         return "unknown";
 564 }
 565
 566 enum ath10k_scan_state {
 567         ATH10K_SCAN_IDLE,
 568         ATH10K_SCAN_STARTING,
 569         ATH10K_SCAN_RUNNING,
 570         ATH10K_SCAN_ABORTING,
 571 };
 572
 573 static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state)
 574 {
 575         switch (state) {
 576         case ATH10K_SCAN_IDLE:
 577                 return "idle";
 578         case ATH10K_SCAN_STARTING:
 579                 return "starting";
 580         case ATH10K_SCAN_RUNNING:
 581                 return "running";
 582         case ATH10K_SCAN_ABORTING:
 583                 return "aborting";
 584         }
 585
 586         return "unknown";
 587 }
 588
 589 enum ath10k_tx_pause_reason {
 590         ATH10K_TX_PAUSE_Q_FULL,
 591         ATH10K_TX_PAUSE_MAX,
 592 };
 593
 594 struct ath10k {
 595         struct ath_common ath_common;
 596         struct ieee80211_hw *hw;
 597         struct device *dev;
 598         u8 mac_addr[ETH_ALEN];
 599
 600         enum ath10k_hw_rev hw_rev;
 601         u16 dev_id;
 602         u32 chip_id;
 603         u32 target_version;
 604         u8 fw_version_major;
 605         u32 fw_version_minor;
 606         u16 fw_version_release;
 607         u16 fw_version_build;
 608         u32 fw_stats_req_mask;
 609         u32 phy_capability;
 610         u32 hw_min_tx_power;
 611         u32 hw_max_tx_power;
 612         u32 ht_cap_info;
 613         u32 vht_cap_info;
 614         u32 num_rf_chains;
 615         u32 max_spatial_stream;
 616         /* protected by conf_mutex */
 617         bool ani_enabled;
 618
 619         DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
 620
 621         bool p2p;
 622
 623         struct {
 624                 enum ath10k_bus bus;
 625                 const struct ath10k_hif_ops *ops;
 626         } hif;
 627
 628         struct completion target_suspend;
 629
 630         const struct ath10k_hw_regs *regs;
 631         const struct ath10k_hw_values *hw_values;
 632         struct ath10k_bmi bmi;
 633         struct ath10k_wmi wmi;
 634         struct ath10k_htc htc;
 635         struct ath10k_htt htt;
 636
 637         struct ath10k_hw_params {
 638                 u32 id;
 639                 u16 dev_id;
 640                 const char *name;
 641                 u32 patch_load_addr;
 642                 int uart_pin;
 643                 u32 otp_exe_param;
 644
 645                 /* This is true if given HW chip has a quirky Cycle Counter
 646                  * wraparound which resets to 0x7fffffff instead of 0. All
 647                  * other CC related counters (e.g. Rx Clear Count) are divided
 648                  * by 2 so they never wraparound themselves.
 649                  */
 650                 bool has_shifted_cc_wraparound;
 651
 652                 /* Some of chip expects fragment descriptor to be continuous
 653                  * memory for any TX operation. Set continuous_frag_desc flag
 654                  * for the hardware which have such requirement.
 655                  */
 656                 bool continuous_frag_desc;
 657
 658                 u32 channel_counters_freq_hz;
 659
 660                 /* Mgmt tx descriptors threshold for limiting probe response
 661                  * frames.
 662                  */
 663                 u32 max_probe_resp_desc_thres;
 664
 665                 struct ath10k_hw_params_fw {
 666                         const char *dir;
 667                         const char *fw;
 668                         const char *otp;
 669                         const char *board;
 670                         size_t board_size;
 671                         size_t board_ext_size;
 672                 } fw;
 673
 674                 /* Number of bytes used for alignment in rx_hdr_status */
 675                 int decap_align_bytes;
 676
 677         } hw_params;
 678
 679         const struct firmware *board;
 680         const void *board_data;
 681         size_t board_len;
 682
 683         const struct firmware *otp;
 684         const void *otp_data;
 685         size_t otp_len;
 686
 687         const struct firmware *firmware;
 688         const void *firmware_data;
 689         size_t firmware_len;
 690
 691         const struct firmware *cal_file;
 692
 693         struct {
 694                 const void *firmware_codeswap_data;
 695                 size_t firmware_codeswap_len;
 696                 struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info;
 697         } swap;
 698
 699         struct {
 700                 u32 vendor;
 701                 u32 device;
 702                 u32 subsystem_vendor;
 703                 u32 subsystem_device;
 704
 705                 bool bmi_ids_valid;
 706                 u8 bmi_board_id;
 707                 u8 bmi_chip_id;
 708         } id;
 709
 710         int fw_api;
 711         int bd_api;
 712         enum ath10k_cal_mode cal_mode;
 713
 714         struct {
 715                 struct completion started;
 716                 struct completion completed;
 717                 struct completion on_channel;
 718                 struct delayed_work timeout;
 719                 enum ath10k_scan_state state;
 720                 bool is_roc;
 721                 int vdev_id;
 722                 int roc_freq;
 723                 bool roc_notify;
 724         } scan;
 725
 726         struct {
 727                 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 728         } mac;
 729
 730         /* should never be NULL; needed for regular htt rx */
 731         struct ieee80211_channel *rx_channel;
 732
 733         /* valid during scan; needed for mgmt rx during scan */
 734         struct ieee80211_channel *scan_channel;
 735
 736         /* current operating channel definition */
 737         struct cfg80211_chan_def chandef;
 738
 739         unsigned long long free_vdev_map;
 740         struct ath10k_vif *monitor_arvif;
 741         bool monitor;
 742         int monitor_vdev_id;
 743         bool monitor_started;
 744         unsigned int filter_flags;
 745         unsigned long dev_flags;
 746         bool dfs_block_radar_events;
 747
 748         /* protected by conf_mutex */
 749         bool radar_enabled;
 750         int num_started_vdevs;
 751
 752         /* Protected by conf-mutex */
 753         u8 cfg_tx_chainmask;
 754         u8 cfg_rx_chainmask;
 755
 756         struct completion install_key_done;
 757
 758         struct completion vdev_setup_done;
 759
 760         struct workqueue_struct *workqueue;
 761         /* Auxiliary workqueue */
 762         struct workqueue_struct *workqueue_aux;
 763
 764         /* prevents concurrent FW reconfiguration */
 765         struct mutex conf_mutex;
 766
 767         /* protects shared structure data */
 768         spinlock_t data_lock;
 769
 770         struct list_head arvifs;
 771         struct list_head peers;
 772         wait_queue_head_t peer_mapping_wq;
 773
 774         /* protected by conf_mutex */
 775         int num_peers;
 776         int num_stations;
 777
 778         int max_num_peers;
 779         int max_num_stations;
 780         int max_num_vdevs;
 781         int max_num_tdls_vdevs;
 782         int num_active_peers;
 783         int num_tids;
 784
 785         struct work_struct svc_rdy_work;
 786         struct sk_buff *svc_rdy_skb;
 787
 788         struct work_struct offchan_tx_work;
 789         struct sk_buff_head offchan_tx_queue;
 790         struct completion offchan_tx_completed;
 791         struct sk_buff *offchan_tx_skb;
 792
 793         struct work_struct wmi_mgmt_tx_work;
 794         struct sk_buff_head wmi_mgmt_tx_queue;
 795
 796         enum ath10k_state state;
 797
 798         struct work_struct register_work;
 799         struct work_struct restart_work;
 800
 801         /* cycle count is reported twice for each visited channel during scan.
 802          * access protected by data_lock */
 803         u32 survey_last_rx_clear_count;
 804         u32 survey_last_cycle_count;
 805         struct survey_info survey[ATH10K_NUM_CHANS];
 806
 807         /* Channel info events are expected to come in pairs without and with
 808          * COMPLETE flag set respectively for each channel visit during scan.
 809          *
 810          * However there are deviations from this rule. This flag is used to
 811          * avoid reporting garbage data.
 812          */
 813         bool ch_info_can_report_survey;
 814
 815         struct dfs_pattern_detector *dfs_detector;
 816
 817         unsigned long tx_paused; /* see ATH10K_TX_PAUSE_ */
 818
 819 #ifdef CONFIG_ATH10K_DEBUGFS
 820         struct ath10k_debug debug;
 821 #endif
 822
 823         struct {
 824                 /* relay(fs) channel for spectral scan */
 825                 struct rchan *rfs_chan_spec_scan;
 826
 827                 /* spectral_mode and spec_config are protected by conf_mutex */
 828                 enum ath10k_spectral_mode mode;
 829                 struct ath10k_spec_scan config;
 830         } spectral;
 831
 832         struct {
 833                 /* protected by conf_mutex */
 834                 const struct firmware *utf;
 835                 char utf_version[32];
 836                 const void *utf_firmware_data;
 837                 size_t utf_firmware_len;
 838                 DECLARE_BITMAP(orig_fw_features, ATH10K_FW_FEATURE_COUNT);
 839                 enum ath10k_fw_wmi_op_version orig_wmi_op_version;
 840                 enum ath10k_fw_wmi_op_version op_version;
 841                 /* protected by data_lock */
 842                 bool utf_monitor;
 843         } testmode;
 844
 845         struct {
 846                 /* protected by data_lock */
 847                 u32 fw_crash_counter;
 848                 u32 fw_warm_reset_counter;
 849                 u32 fw_cold_reset_counter;
 850         } stats;
 851
 852         struct ath10k_thermal thermal;
 853         struct ath10k_wow wow;
 854
 855         /* must be last */
 856         u8 drv_priv[0] __aligned(sizeof(void *));
 857 };
 858
 859 struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
 860                                   enum ath10k_bus bus,
 861                                   enum ath10k_hw_rev hw_rev,
 862                                   const struct ath10k_hif_ops *hif_ops);
 863 void ath10k_core_destroy(struct ath10k *ar);
 864 void ath10k_core_get_fw_features_str(struct ath10k *ar,
 865                                      char *buf,
 866                                      size_t max_len);
 867
 868 int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode);
 869 int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt);
 870 void ath10k_core_stop(struct ath10k *ar);
 871 int ath10k_core_register(struct ath10k *ar, u32 chip_id);
 872 void ath10k_core_unregister(struct ath10k *ar);
 873
 874 #endif /* _CORE_H_ */