drivers/net/wireless/ath/ath9k/debug.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef DEBUG_H
  18 #define DEBUG_H
  19
  20 #include "hw.h"
  21 #include "dfs_debug.h"
  22
  23 struct ath_txq;
  24 struct ath_buf;
  25 struct fft_sample_tlv;
  26
  27 #ifdef CONFIG_ATH9K_DEBUGFS
  28 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  29 #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
  30 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
  31 #define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
  32 #define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++;
  33 #else
  34 #define TX_STAT_INC(q, c) do { } while (0)
  35 #define RX_STAT_INC(c)
  36 #define RESET_STAT_INC(sc, type) do { } while (0)
  37 #define ANT_STAT_INC(i, c) do { } while (0)
  38 #define ANT_LNA_INC(i, c) do { } while (0)
  39 #endif
  40
  41 enum ath_reset_type {
  42         RESET_TYPE_BB_HANG,
  43         RESET_TYPE_BB_WATCHDOG,
  44         RESET_TYPE_FATAL_INT,
  45         RESET_TYPE_TX_ERROR,
  46         RESET_TYPE_TX_GTT,
  47         RESET_TYPE_TX_HANG,
  48         RESET_TYPE_PLL_HANG,
  49         RESET_TYPE_MAC_HANG,
  50         RESET_TYPE_BEACON_STUCK,
  51         RESET_TYPE_MCI,
  52         RESET_TYPE_CALIBRATION,
  53         RESET_TX_DMA_ERROR,
  54         RESET_RX_DMA_ERROR,
  55         __RESET_TYPE_MAX
  56 };
  57
  58 #ifdef CONFIG_ATH9K_DEBUGFS
  59
  60 /**
  61  * struct ath_interrupt_stats - Contains statistics about interrupts
  62  * @total: Total no. of interrupts generated so far
  63  * @rxok: RX with no errors
  64  * @rxlp: RX with low priority RX
  65  * @rxhp: RX with high priority, uapsd only
  66  * @rxeol: RX with no more RXDESC available
  67  * @rxorn: RX FIFO overrun
  68  * @txok: TX completed at the requested rate
  69  * @txurn: TX FIFO underrun
  70  * @mib: MIB regs reaching its threshold
  71  * @rxphyerr: RX with phy errors
  72  * @rx_keycache_miss: RX with key cache misses
  73  * @swba: Software Beacon Alert
  74  * @bmiss: Beacon Miss
  75  * @bnr: Beacon Not Ready
  76  * @cst: Carrier Sense TImeout
  77  * @gtt: Global TX Timeout
  78  * @tim: RX beacon TIM occurrence
  79  * @cabend: RX End of CAB traffic
  80  * @dtimsync: DTIM sync lossage
  81  * @dtim: RX Beacon with DTIM
  82  * @bb_watchdog: Baseband watchdog
  83  * @tsfoor: TSF out of range, indicates that the corrected TSF received
  84  * from a beacon differs from the PCU's internal TSF by more than a
  85  * (programmable) threshold
  86  * @local_timeout: Internal bus timeout.
  87  * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
  88  * @gen_timer: Generic hardware timer interrupt
  89  */
  90 struct ath_interrupt_stats {
  91         u32 total;
  92         u32 rxok;
  93         u32 rxlp;
  94         u32 rxhp;
  95         u32 rxeol;
  96         u32 rxorn;
  97         u32 txok;
  98         u32 txeol;
  99         u32 txurn;
 100         u32 mib;
 101         u32 rxphyerr;
 102         u32 rx_keycache_miss;
 103         u32 swba;
 104         u32 bmiss;
 105         u32 bnr;
 106         u32 cst;
 107         u32 gtt;
 108         u32 tim;
 109         u32 cabend;
 110         u32 dtimsync;
 111         u32 dtim;
 112         u32 bb_watchdog;
 113         u32 tsfoor;
 114         u32 mci;
 115         u32 gen_timer;
 116
 117         /* Sync-cause stats */
 118         u32 sync_cause_all;
 119         u32 sync_rtc_irq;
 120         u32 sync_mac_irq;
 121         u32 eeprom_illegal_access;
 122         u32 apb_timeout;
 123         u32 pci_mode_conflict;
 124         u32 host1_fatal;
 125         u32 host1_perr;
 126         u32 trcv_fifo_perr;
 127         u32 radm_cpl_ep;
 128         u32 radm_cpl_dllp_abort;
 129         u32 radm_cpl_tlp_abort;
 130         u32 radm_cpl_ecrc_err;
 131         u32 radm_cpl_timeout;
 132         u32 local_timeout;
 133         u32 pm_access;
 134         u32 mac_awake;
 135         u32 mac_asleep;
 136         u32 mac_sleep_access;
 137 };
 138
 139
 140 /**
 141  * struct ath_tx_stats - Statistics about TX
 142  * @tx_pkts_all:  No. of total frames transmitted, including ones that
 143         may have had errors.
 144  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
 145         may have had errors.
 146  * @queued: Total MPDUs (non-aggr) queued
 147  * @completed: Total MPDUs (non-aggr) completed
 148  * @a_aggr: Total no. of aggregates queued
 149  * @a_queued_hw: Total AMPDUs queued to hardware
 150  * @a_queued_sw: Total AMPDUs queued to software queues
 151  * @a_completed: Total AMPDUs completed
 152  * @a_retries: No. of AMPDUs retried (SW)
 153  * @a_xretries: No. of AMPDUs dropped due to xretries
 154  * @txerr_filtered: No. of frames with TXERR_FILT flag set.
 155  * @fifo_underrun: FIFO underrun occurrences
 156         Valid only for:
 157                 - non-aggregate condition.
 158                 - first packet of aggregate.
 159  * @xtxop: No. of frames filtered because of TXOP limit
 160  * @timer_exp: Transmit timer expiry
 161  * @desc_cfg_err: Descriptor configuration errors
 162  * @data_urn: TX data underrun errors
 163  * @delim_urn: TX delimiter underrun errors
 164  * @puttxbuf: Number of times hardware was given txbuf to write.
 165  * @txstart:  Number of times hardware was told to start tx.
 166  * @txprocdesc:  Number of times tx descriptor was processed
 167  * @txfailed:  Out-of-memory or other errors in xmit path.
 168  */
 169 struct ath_tx_stats {
 170         u32 tx_pkts_all;
 171         u32 tx_bytes_all;
 172         u32 queued;
 173         u32 completed;
 174         u32 xretries;
 175         u32 a_aggr;
 176         u32 a_queued_hw;
 177         u32 a_queued_sw;
 178         u32 a_completed;
 179         u32 a_retries;
 180         u32 a_xretries;
 181         u32 txerr_filtered;
 182         u32 fifo_underrun;
 183         u32 xtxop;
 184         u32 timer_exp;
 185         u32 desc_cfg_err;
 186         u32 data_underrun;
 187         u32 delim_underrun;
 188         u32 puttxbuf;
 189         u32 txstart;
 190         u32 txprocdesc;
 191         u32 txfailed;
 192 };
 193
 194 /*
 195  * Various utility macros to print TX/Queue counters.
 196  */
 197 #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
 198 #define TXSTATS sc->debug.stats.txstats
 199 #define PR(str, elem)                                                   \
 200         do {                                                            \
 201                 seq_printf(file, "%s%13u%11u%10u%10u\n", str,           \
 202                            TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
 203                            TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
 204                            TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
 205                            TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
 206         } while(0)
 207
 208 struct ath_rx_rate_stats {
 209         struct {
 210                 u32 ht20_cnt;
 211                 u32 ht40_cnt;
 212                 u32 sgi_cnt;
 213                 u32 lgi_cnt;
 214         } ht_stats[24];
 215
 216         struct {
 217                 u32 ofdm_cnt;
 218         } ofdm_stats[8];
 219
 220         struct {
 221                 u32 cck_lp_cnt;
 222                 u32 cck_sp_cnt;
 223         } cck_stats[4];
 224 };
 225
 226 #define ANT_MAIN 0
 227 #define ANT_ALT  1
 228
 229 struct ath_antenna_stats {
 230         u32 recv_cnt;
 231         u32 rssi_avg;
 232         u32 lna_recv_cnt[4];
 233         u32 lna_attempt_cnt[4];
 234 };
 235
 236 struct ath_stats {
 237         struct ath_interrupt_stats istats;
 238         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
 239         struct ath_rx_stats rxstats;
 240         struct ath_dfs_stats dfs_stats;
 241         struct ath_antenna_stats ant_stats[2];
 242         u32 reset[__RESET_TYPE_MAX];
 243 };
 244
 245 struct ath9k_debug {
 246         struct dentry *debugfs_phy;
 247         u32 regidx;
 248         struct ath_stats stats;
 249 };
 250
 251 int ath9k_init_debug(struct ath_hw *ah);
 252 void ath9k_deinit_debug(struct ath_softc *sc);
 253
 254 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
 255 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
 256                        struct ath_tx_status *ts, struct ath_txq *txq,
 257                        unsigned int flags);
 258 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
 259 int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
 260                             struct ieee80211_vif *vif, int sset);
 261 void ath9k_get_et_stats(struct ieee80211_hw *hw,
 262                         struct ieee80211_vif *vif,
 263                         struct ethtool_stats *stats, u64 *data);
 264 void ath9k_get_et_strings(struct ieee80211_hw *hw,
 265                           struct ieee80211_vif *vif,
 266                           u32 sset, u8 *data);
 267 void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
 268                            struct ieee80211_vif *vif,
 269                            struct ieee80211_sta *sta,
 270                            struct dentry *dir);
 271 void ath9k_debug_stat_ant(struct ath_softc *sc,
 272                           struct ath_hw_antcomb_conf *div_ant_conf,
 273                           int main_rssi_avg, int alt_rssi_avg);
 274 void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
 275
 276 #else
 277
 278 static inline int ath9k_init_debug(struct ath_hw *ah)
 279 {
 280         return 0;
 281 }
 282
 283 static inline void ath9k_deinit_debug(struct ath_softc *sc)
 284 {
 285 }
 286 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
 287                                             enum ath9k_int status)
 288 {
 289 }
 290 static inline void ath_debug_stat_tx(struct ath_softc *sc,
 291                                      struct ath_buf *bf,
 292                                      struct ath_tx_status *ts,
 293                                      struct ath_txq *txq,
 294                                      unsigned int flags)
 295 {
 296 }
 297 static inline void ath_debug_stat_rx(struct ath_softc *sc,
 298                                      struct ath_rx_status *rs)
 299 {
 300 }
 301 static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
 302                                         struct ath_hw_antcomb_conf *div_ant_conf,
 303                                         int main_rssi_avg, int alt_rssi_avg)
 304 {
 305
 306 }
 307
 308 static inline void
 309 ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
 310 {
 311 }
 312
 313 #endif /* CONFIG_ATH9K_DEBUGFS */
 314
 315 #ifdef CONFIG_ATH9K_STATION_STATISTICS
 316 void ath_debug_rate_stats(struct ath_softc *sc,
 317                           struct ath_rx_status *rs,
 318                           struct sk_buff *skb);
 319 #else
 320 static inline void ath_debug_rate_stats(struct ath_softc *sc,
 321                                         struct ath_rx_status *rs,
 322                                         struct sk_buff *skb)
 323 {
 324 }
 325 #endif /* CONFIG_ATH9K_STATION_STATISTICS */
 326
 327 #endif /* DEBUG_H */