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Linux 4.4.145
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / hw.h
blob831a54415a2512fe890832dcd6ec688d160b1a7c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23 #include <linux/firmware.h>
24
25 #include "mac.h"
26 #include "ani.h"
27 #include "eeprom.h"
28 #include "calib.h"
29 #include "reg.h"
30 #include "reg_mci.h"
31 #include "phy.h"
32 #include "btcoex.h"
33 #include "dynack.h"
34
35 #include "../regd.h"
36
37 #define ATHEROS_VENDOR_ID 0x168c
38
39 #define AR5416_DEVID_PCI 0x0023
40 #define AR5416_DEVID_PCIE 0x0024
41 #define AR9160_DEVID_PCI 0x0027
42 #define AR9280_DEVID_PCI 0x0029
43 #define AR9280_DEVID_PCIE 0x002a
44 #define AR9285_DEVID_PCIE 0x002b
45 #define AR2427_DEVID_PCIE 0x002c
46 #define AR9287_DEVID_PCI 0x002d
47 #define AR9287_DEVID_PCIE 0x002e
48 #define AR9300_DEVID_PCIE 0x0030
49 #define AR9300_DEVID_AR9340 0x0031
50 #define AR9300_DEVID_AR9485_PCIE 0x0032
51 #define AR9300_DEVID_AR9580 0x0033
52 #define AR9300_DEVID_AR9462 0x0034
53 #define AR9300_DEVID_AR9330 0x0035
54 #define AR9300_DEVID_QCA955X 0x0038
55 #define AR9485_DEVID_AR1111 0x0037
56 #define AR9300_DEVID_AR9565 0x0036
57 #define AR9300_DEVID_AR953X 0x003d
58 #define AR9300_DEVID_QCA956X 0x003f
59
60 #define AR5416_AR9100_DEVID 0x000b
61
62 #define AR_SUBVENDOR_ID_NOG 0x0e11
63 #define AR_SUBVENDOR_ID_NEW_A 0x7065
64 #define AR5416_MAGIC 0x19641014
65
66 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
67 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
68 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
69
70 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
71
72 #define ATH_DEFAULT_NOISE_FLOOR -95
73
74 #define ATH9K_RSSI_BAD -128
75
76 #define ATH9K_NUM_CHANNELS 38
77
78 /* Register read/write primitives */
79 #define REG_WRITE(_ah, _reg, _val) \
80 (_ah)->reg_ops.write((_ah), (_val), (_reg))
81
82 #define REG_READ(_ah, _reg) \
83 (_ah)->reg_ops.read((_ah), (_reg))
84
85 #define REG_READ_MULTI(_ah, _addr, _val, _cnt) \
86 (_ah)->reg_ops.multi_read((_ah), (_addr), (_val), (_cnt))
87
88 #define REG_RMW(_ah, _reg, _set, _clr) \
89 (_ah)->reg_ops.rmw((_ah), (_reg), (_set), (_clr))
90
91 #define ENABLE_REGWRITE_BUFFER(_ah) \
92 do { \
93 if ((_ah)->reg_ops.enable_write_buffer) \
94 (_ah)->reg_ops.enable_write_buffer((_ah)); \
95 } while (0)
96
97 #define REGWRITE_BUFFER_FLUSH(_ah) \
98 do { \
99 if ((_ah)->reg_ops.write_flush) \
100 (_ah)->reg_ops.write_flush((_ah)); \
101 } while (0)
102
103 #define ENABLE_REG_RMW_BUFFER(_ah) \
104 do { \
105 if ((_ah)->reg_ops.enable_rmw_buffer) \
106 (_ah)->reg_ops.enable_rmw_buffer((_ah)); \
107 } while (0)
108
109 #define REG_RMW_BUFFER_FLUSH(_ah) \
110 do { \
111 if ((_ah)->reg_ops.rmw_flush) \
112 (_ah)->reg_ops.rmw_flush((_ah)); \
113 } while (0)
114
115 #define PR_EEP(_s, _val) \
116 do { \
117 len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
118 _s, (_val)); \
119 } while (0)
120
121 #define SM(_v, _f) (((_v) << _f##_S) & _f)
122 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
123 #define REG_RMW_FIELD(_a, _r, _f, _v) \
124 REG_RMW(_a, _r, (((_v) << _f##_S) & _f), (_f))
125 #define REG_READ_FIELD(_a, _r, _f) \
126 (((REG_READ(_a, _r) & _f) >> _f##_S))
127 #define REG_SET_BIT(_a, _r, _f) \
128 REG_RMW(_a, _r, (_f), 0)
129 #define REG_CLR_BIT(_a, _r, _f) \
130 REG_RMW(_a, _r, 0, (_f))
131
132 #define DO_DELAY(x) do { \
133 if (((++(x) % 64) == 0) && \
134 (ath9k_hw_common(ah)->bus_ops->ath_bus_type \
135 != ATH_USB)) \
136 udelay(1); \
137 } while (0)
138
139 #define REG_WRITE_ARRAY(iniarray, column, regWr) \
140 ath9k_hw_write_array(ah, iniarray, column, &(regWr))
141 #define REG_READ_ARRAY(ah, array, size) \
142 ath9k_hw_read_array(ah, array, size)
143
144 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
145 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
146 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
147 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
148 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
149 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
150 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
151 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_DATA 0x16
152 #define AR_GPIO_OUTPUT_MUX_AS_MCI_WLAN_CLK 0x17
153 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_DATA 0x18
154 #define AR_GPIO_OUTPUT_MUX_AS_MCI_BT_CLK 0x19
155 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_TX 0x14
156 #define AR_GPIO_OUTPUT_MUX_AS_WL_IN_RX 0x13
157 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_TX 9
158 #define AR_GPIO_OUTPUT_MUX_AS_BT_IN_RX 8
159 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_STROBE 0x1d
160 #define AR_GPIO_OUTPUT_MUX_AS_RUCKUS_DATA 0x1e
161
162 #define AR_GPIOD_MASK 0x00001FFF
163 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
164
165 #define BASE_ACTIVATE_DELAY 100
166 #define RTC_PLL_SETTLE_DELAY (AR_SREV_9340(ah) ? 1000 : 100)
167 #define COEF_SCALE_S 24
168 #define HT40_CHANNEL_CENTER_SHIFT 10
169
170 #define ATH9K_ANTENNA0_CHAINMASK 0x1
171 #define ATH9K_ANTENNA1_CHAINMASK 0x2
172
173 #define ATH9K_NUM_DMA_DEBUG_REGS 8
174 #define ATH9K_NUM_QUEUES 10
175
176 #define MAX_RATE_POWER 63
177 #define AH_WAIT_TIMEOUT 100000 /* (us) */
178 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
179 #define AH_TIME_QUANTUM 10
180 #define AR_KEYTABLE_SIZE 128
181 #define POWER_UP_TIME 10000
182 #define SPUR_RSSI_THRESH 40
183 #define UPPER_5G_SUB_BAND_START 5700
184 #define MID_5G_SUB_BAND_START 5400
185
186 #define CAB_TIMEOUT_VAL 10
187 #define BEACON_TIMEOUT_VAL 10
188 #define MIN_BEACON_TIMEOUT_VAL 1
189 #define SLEEP_SLOP TU_TO_USEC(3)
190
191 #define INIT_CONFIG_STATUS 0x00000000
192 #define INIT_RSSI_THR 0x00000700
193 #define INIT_BCON_CNTRL_REG 0x00000000
194
195 #define TU_TO_USEC(_tu) ((_tu) << 10)
196
197 #define ATH9K_HW_RX_HP_QDEPTH 16
198 #define ATH9K_HW_RX_LP_QDEPTH 128
199
200 #define PAPRD_GAIN_TABLE_ENTRIES 32
201 #define PAPRD_TABLE_SZ 24
202 #define PAPRD_IDEAL_AGC2_PWR_RANGE 0xe0
203
204 /*
205 * Wake on Wireless
206 */
207
208 /* Keep Alive Frame */
209 #define KAL_FRAME_LEN 28
210 #define KAL_FRAME_TYPE 0x2 /* data frame */
211 #define KAL_FRAME_SUB_TYPE 0x4 /* null data frame */
212 #define KAL_DURATION_ID 0x3d
213 #define KAL_NUM_DATA_WORDS 6
214 #define KAL_NUM_DESC_WORDS 12
215 #define KAL_ANTENNA_MODE 1
216 #define KAL_TO_DS 1
217 #define KAL_DELAY 4 /* delay of 4ms between 2 KAL frames */
218 #define KAL_TIMEOUT 900
219
220 #define MAX_PATTERN_SIZE 256
221 #define MAX_PATTERN_MASK_SIZE 32
222 #define MAX_NUM_PATTERN 16
223 #define MAX_NUM_PATTERN_LEGACY 8
224 #define MAX_NUM_USER_PATTERN 6 /* deducting the disassociate and
225 deauthenticate packets */
226
227 /*
228 * WoW trigger mapping to hardware code
229 */
230
231 #define AH_WOW_USER_PATTERN_EN BIT(0)
232 #define AH_WOW_MAGIC_PATTERN_EN BIT(1)
233 #define AH_WOW_LINK_CHANGE BIT(2)
234 #define AH_WOW_BEACON_MISS BIT(3)
235
236 enum ath_hw_txq_subtype {
237 ATH_TXQ_AC_BK = 0,
238 ATH_TXQ_AC_BE = 1,
239 ATH_TXQ_AC_VI = 2,
240 ATH_TXQ_AC_VO = 3,
241 };
242
243 enum ath_ini_subsys {
244 ATH_INI_PRE = 0,
245 ATH_INI_CORE,
246 ATH_INI_POST,
247 ATH_INI_NUM_SPLIT,
248 };
249
250 enum ath9k_hw_caps {
251 ATH9K_HW_CAP_HT = BIT(0),
252 ATH9K_HW_CAP_RFSILENT = BIT(1),
253 ATH9K_HW_CAP_AUTOSLEEP = BIT(2),
254 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(3),
255 ATH9K_HW_CAP_EDMA = BIT(4),
256 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(5),
257 ATH9K_HW_CAP_LDPC = BIT(6),
258 ATH9K_HW_CAP_FASTCLOCK = BIT(7),
259 ATH9K_HW_CAP_SGI_20 = BIT(8),
260 ATH9K_HW_CAP_ANT_DIV_COMB = BIT(10),
261 ATH9K_HW_CAP_2GHZ = BIT(11),
262 ATH9K_HW_CAP_5GHZ = BIT(12),
263 ATH9K_HW_CAP_APM = BIT(13),
264 #ifdef CONFIG_ATH9K_PCOEM
265 ATH9K_HW_CAP_RTT = BIT(14),
266 ATH9K_HW_CAP_MCI = BIT(15),
267 ATH9K_HW_CAP_BT_ANT_DIV = BIT(17),
268 #else
269 ATH9K_HW_CAP_RTT = 0,
270 ATH9K_HW_CAP_MCI = 0,
271 ATH9K_HW_CAP_BT_ANT_DIV = 0,
272 #endif
273 ATH9K_HW_CAP_DFS = BIT(18),
274 ATH9K_HW_CAP_PAPRD = BIT(19),
275 ATH9K_HW_CAP_FCC_BAND_SWITCH = BIT(20),
276 };
277
278 /*
279 * WoW device capabilities
280 * @ATH9K_HW_WOW_DEVICE_CAPABLE: device revision is capable of WoW.
281 * @ATH9K_HW_WOW_PATTERN_MATCH_EXACT: device is capable of matching
282 * an exact user defined pattern or de-authentication/disassoc pattern.
283 * @ATH9K_HW_WOW_PATTERN_MATCH_DWORD: device requires the first four
284 * bytes of the pattern for user defined pattern, de-authentication and
285 * disassociation patterns for all types of possible frames recieved
286 * of those types.
287 */
288
289 struct ath9k_hw_wow {
290 u32 wow_event_mask;
291 u32 wow_event_mask2;
292 u8 max_patterns;
293 };
294
295 struct ath9k_hw_capabilities {
296 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
297 u16 rts_aggr_limit;
298 u8 tx_chainmask;
299 u8 rx_chainmask;
300 u8 chip_chainmask;
301 u8 max_txchains;
302 u8 max_rxchains;
303 u8 num_gpio_pins;
304 u8 rx_hp_qdepth;
305 u8 rx_lp_qdepth;
306 u8 rx_status_len;
307 u8 tx_desc_len;
308 u8 txs_len;
309 };
310
311 #define AR_NO_SPUR 0x8000
312 #define AR_BASE_FREQ_2GHZ 2300
313 #define AR_BASE_FREQ_5GHZ 4900
314 #define AR_SPUR_FEEQ_BOUND_HT40 19
315 #define AR_SPUR_FEEQ_BOUND_HT20 10
316
317 enum ath9k_hw_hang_checks {
318 HW_BB_WATCHDOG = BIT(0),
319 HW_PHYRESTART_CLC_WAR = BIT(1),
320 HW_BB_RIFS_HANG = BIT(2),
321 HW_BB_DFS_HANG = BIT(3),
322 HW_BB_RX_CLEAR_STUCK_HANG = BIT(4),
323 HW_MAC_HANG = BIT(5),
324 };
325
326 #define AR_PCIE_PLL_PWRSAVE_CONTROL BIT(0)
327 #define AR_PCIE_PLL_PWRSAVE_ON_D3 BIT(1)
328 #define AR_PCIE_PLL_PWRSAVE_ON_D0 BIT(2)
329 #define AR_PCIE_CDR_PWRSAVE_ON_D3 BIT(3)
330 #define AR_PCIE_CDR_PWRSAVE_ON_D0 BIT(4)
331
332 struct ath9k_ops_config {
333 int dma_beacon_response_time;
334 int sw_beacon_response_time;
335 bool cwm_ignore_extcca;
336 u32 pcie_waen;
337 u8 analog_shiftreg;
338 u32 ofdm_trig_low;
339 u32 ofdm_trig_high;
340 u32 cck_trig_high;
341 u32 cck_trig_low;
342 bool enable_paprd;
343 int serialize_regmode;
344 bool rx_intr_mitigation;
345 bool tx_intr_mitigation;
346 u8 max_txtrig_level;
347 u16 ani_poll_interval; /* ANI poll interval in ms */
348 u16 hw_hang_checks;
349 u16 rimt_first;
350 u16 rimt_last;
351
352 /* Platform specific config */
353 u32 aspm_l1_fix;
354 u32 xlna_gpio;
355 u32 ant_ctrl_comm2g_switch_enable;
356 bool xatten_margin_cfg;
357 bool alt_mingainidx;
358 u8 pll_pwrsave;
359 bool tx_gain_buffalo;
360 bool led_active_high;
361 };
362
363 enum ath9k_int {
364 ATH9K_INT_RX = 0x00000001,
365 ATH9K_INT_RXDESC = 0x00000002,
366 ATH9K_INT_RXHP = 0x00000001,
367 ATH9K_INT_RXLP = 0x00000002,
368 ATH9K_INT_RXNOFRM = 0x00000008,
369 ATH9K_INT_RXEOL = 0x00000010,
370 ATH9K_INT_RXORN = 0x00000020,
371 ATH9K_INT_TX = 0x00000040,
372 ATH9K_INT_TXDESC = 0x00000080,
373 ATH9K_INT_TIM_TIMER = 0x00000100,
374 ATH9K_INT_MCI = 0x00000200,
375 ATH9K_INT_BB_WATCHDOG = 0x00000400,
376 ATH9K_INT_TXURN = 0x00000800,
377 ATH9K_INT_MIB = 0x00001000,
378 ATH9K_INT_RXPHY = 0x00004000,
379 ATH9K_INT_RXKCM = 0x00008000,
380 ATH9K_INT_SWBA = 0x00010000,
381 ATH9K_INT_BMISS = 0x00040000,
382 ATH9K_INT_BNR = 0x00100000,
383 ATH9K_INT_TIM = 0x00200000,
384 ATH9K_INT_DTIM = 0x00400000,
385 ATH9K_INT_DTIMSYNC = 0x00800000,
386 ATH9K_INT_GPIO = 0x01000000,
387 ATH9K_INT_CABEND = 0x02000000,
388 ATH9K_INT_TSFOOR = 0x04000000,
389 ATH9K_INT_GENTIMER = 0x08000000,
390 ATH9K_INT_CST = 0x10000000,
391 ATH9K_INT_GTT = 0x20000000,
392 ATH9K_INT_FATAL = 0x40000000,
393 ATH9K_INT_GLOBAL = 0x80000000,
394 ATH9K_INT_BMISC = ATH9K_INT_TIM |
395 ATH9K_INT_DTIM |
396 ATH9K_INT_DTIMSYNC |
397 ATH9K_INT_TSFOOR |
398 ATH9K_INT_CABEND,
399 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
400 ATH9K_INT_RXDESC |
401 ATH9K_INT_RXEOL |
402 ATH9K_INT_RXORN |
403 ATH9K_INT_TXURN |
404 ATH9K_INT_TXDESC |
405 ATH9K_INT_MIB |
406 ATH9K_INT_RXPHY |
407 ATH9K_INT_RXKCM |
408 ATH9K_INT_SWBA |
409 ATH9K_INT_BMISS |
410 ATH9K_INT_GPIO,
411 ATH9K_INT_NOCARD = 0xffffffff
412 };
413
414 #define MAX_RTT_TABLE_ENTRY 6
415 #define MAX_IQCAL_MEASUREMENT 8
416 #define MAX_CL_TAB_ENTRY 16
417 #define CL_TAB_ENTRY(reg_base) (reg_base + (4 * j))
418
419 enum ath9k_cal_flags {
420 RTT_DONE,
421 PAPRD_PACKET_SENT,
422 PAPRD_DONE,
423 NFCAL_PENDING,
424 NFCAL_INTF,
425 TXIQCAL_DONE,
426 TXCLCAL_DONE,
427 SW_PKDET_DONE,
428 };
429
430 struct ath9k_hw_cal_data {
431 u16 channel;
432 u16 channelFlags;
433 unsigned long cal_flags;
434 int32_t CalValid;
435 int8_t iCoff;
436 int8_t qCoff;
437 u8 caldac[2];
438 u16 small_signal_gain[AR9300_MAX_CHAINS];
439 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
440 u32 num_measures[AR9300_MAX_CHAINS];
441 int tx_corr_coeff[MAX_IQCAL_MEASUREMENT][AR9300_MAX_CHAINS];
442 u32 tx_clcal[AR9300_MAX_CHAINS][MAX_CL_TAB_ENTRY];
443 u32 rtt_table[AR9300_MAX_CHAINS][MAX_RTT_TABLE_ENTRY];
444 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
445 };
446
447 struct ath9k_channel {
448 struct ieee80211_channel *chan;
449 u16 channel;
450 u16 channelFlags;
451 s16 noisefloor;
452 };
453
454 #define CHANNEL_5GHZ BIT(0)
455 #define CHANNEL_HALF BIT(1)
456 #define CHANNEL_QUARTER BIT(2)
457 #define CHANNEL_HT BIT(3)
458 #define CHANNEL_HT40PLUS BIT(4)
459 #define CHANNEL_HT40MINUS BIT(5)
460
461 #define IS_CHAN_5GHZ(_c) (!!((_c)->channelFlags & CHANNEL_5GHZ))
462 #define IS_CHAN_2GHZ(_c) (!IS_CHAN_5GHZ(_c))
463
464 #define IS_CHAN_HALF_RATE(_c) (!!((_c)->channelFlags & CHANNEL_HALF))
465 #define IS_CHAN_QUARTER_RATE(_c) (!!((_c)->channelFlags & CHANNEL_QUARTER))
466 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
467 (IS_CHAN_5GHZ(_c) && ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
468
469 #define IS_CHAN_HT(_c) ((_c)->channelFlags & CHANNEL_HT)
470
471 #define IS_CHAN_HT20(_c) (IS_CHAN_HT(_c) && !IS_CHAN_HT40(_c))
472
473 #define IS_CHAN_HT40(_c) \
474 (!!((_c)->channelFlags & (CHANNEL_HT40PLUS | CHANNEL_HT40MINUS)))
475
476 #define IS_CHAN_HT40PLUS(_c) ((_c)->channelFlags & CHANNEL_HT40PLUS)
477 #define IS_CHAN_HT40MINUS(_c) ((_c)->channelFlags & CHANNEL_HT40MINUS)
478
479 enum ath9k_power_mode {
480 ATH9K_PM_AWAKE = 0,
481 ATH9K_PM_FULL_SLEEP,
482 ATH9K_PM_NETWORK_SLEEP,
483 ATH9K_PM_UNDEFINED
484 };
485
486 enum ser_reg_mode {
487 SER_REG_MODE_OFF = 0,
488 SER_REG_MODE_ON = 1,
489 SER_REG_MODE_AUTO = 2,
490 };
491
492 enum ath9k_rx_qtype {
493 ATH9K_RX_QUEUE_HP,
494 ATH9K_RX_QUEUE_LP,
495 ATH9K_RX_QUEUE_MAX,
496 };
497
498 struct ath9k_beacon_state {
499 u32 bs_nexttbtt;
500 u32 bs_nextdtim;
501 u32 bs_intval;
502 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
503 u32 bs_dtimperiod;
504 u16 bs_bmissthreshold;
505 u32 bs_sleepduration;
506 u32 bs_tsfoor_threshold;
507 };
508
509 struct chan_centers {
510 u16 synth_center;
511 u16 ctl_center;
512 u16 ext_center;
513 };
514
515 enum {
516 ATH9K_RESET_POWER_ON,
517 ATH9K_RESET_WARM,
518 ATH9K_RESET_COLD,
519 };
520
521 struct ath9k_hw_version {
522 u32 magic;
523 u16 devid;
524 u16 subvendorid;
525 u32 macVersion;
526 u16 macRev;
527 u16 phyRev;
528 u16 analog5GhzRev;
529 u16 analog2GhzRev;
530 enum ath_usb_dev usbdev;
531 };
532
533 /* Generic TSF timer definitions */
534
535 #define ATH_MAX_GEN_TIMER 16
536
537 #define AR_GENTMR_BIT(_index) (1 << (_index))
538
539 struct ath_gen_timer_configuration {
540 u32 next_addr;
541 u32 period_addr;
542 u32 mode_addr;
543 u32 mode_mask;
544 };
545
546 struct ath_gen_timer {
547 void (*trigger)(void *arg);
548 void (*overflow)(void *arg);
549 void *arg;
550 u8 index;
551 };
552
553 struct ath_gen_timer_table {
554 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
555 u16 timer_mask;
556 bool tsf2_enabled;
557 };
558
559 struct ath_hw_antcomb_conf {
560 u8 main_lna_conf;
561 u8 alt_lna_conf;
562 u8 fast_div_bias;
563 u8 main_gaintb;
564 u8 alt_gaintb;
565 int lna1_lna2_delta;
566 int lna1_lna2_switch_delta;
567 u8 div_group;
568 };
569
570 /**
571 * struct ath_hw_radar_conf - radar detection initialization parameters
572 *
573 * @pulse_inband: threshold for checking the ratio of in-band power
574 * to total power for short radar pulses (half dB steps)
575 * @pulse_inband_step: threshold for checking an in-band power to total
576 * power ratio increase for short radar pulses (half dB steps)
577 * @pulse_height: threshold for detecting the beginning of a short
578 * radar pulse (dB step)
579 * @pulse_rssi: threshold for detecting if a short radar pulse is
580 * gone (dB step)
581 * @pulse_maxlen: maximum pulse length (0.8 us steps)
582 *
583 * @radar_rssi: RSSI threshold for starting long radar detection (dB steps)
584 * @radar_inband: threshold for checking the ratio of in-band power
585 * to total power for long radar pulses (half dB steps)
586 * @fir_power: threshold for detecting the end of a long radar pulse (dB)
587 *
588 * @ext_channel: enable extension channel radar detection
589 */
590 struct ath_hw_radar_conf {
591 unsigned int pulse_inband;
592 unsigned int pulse_inband_step;
593 unsigned int pulse_height;
594 unsigned int pulse_rssi;
595 unsigned int pulse_maxlen;
596
597 unsigned int radar_rssi;
598 unsigned int radar_inband;
599 int fir_power;
600
601 bool ext_channel;
602 };
603
604 /**
605 * struct ath_hw_private_ops - callbacks used internally by hardware code
606 *
607 * This structure contains private callbacks designed to only be used internally
608 * by the hardware core.
609 *
610 * @init_cal_settings: setup types of calibrations supported
611 * @init_cal: starts actual calibration
612 *
613 * @init_mode_gain_regs: Initialize TX/RX gain registers
614 *
615 * @rf_set_freq: change frequency
616 * @spur_mitigate_freq: spur mitigation
617 * @set_rf_regs:
618 * @compute_pll_control: compute the PLL control value to use for
619 * AR_RTC_PLL_CONTROL for a given channel
620 * @setup_calibration: set up calibration
621 * @iscal_supported: used to query if a type of calibration is supported
622 *
623 * @ani_cache_ini_regs: cache the values for ANI from the initial
624 * register settings through the register initialization.
625 */
626 struct ath_hw_private_ops {
627 void (*init_hang_checks)(struct ath_hw *ah);
628 bool (*detect_mac_hang)(struct ath_hw *ah);
629 bool (*detect_bb_hang)(struct ath_hw *ah);
630
631 /* Calibration ops */
632 void (*init_cal_settings)(struct ath_hw *ah);
633 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
634
635 void (*init_mode_gain_regs)(struct ath_hw *ah);
636 void (*setup_calibration)(struct ath_hw *ah,
637 struct ath9k_cal_list *currCal);
638
639 /* PHY ops */
640 int (*rf_set_freq)(struct ath_hw *ah,
641 struct ath9k_channel *chan);
642 void (*spur_mitigate_freq)(struct ath_hw *ah,
643 struct ath9k_channel *chan);
644 bool (*set_rf_regs)(struct ath_hw *ah,
645 struct ath9k_channel *chan,
646 u16 modesIndex);
647 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
648 void (*init_bb)(struct ath_hw *ah,
649 struct ath9k_channel *chan);
650 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
651 void (*olc_init)(struct ath_hw *ah);
652 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
653 void (*mark_phy_inactive)(struct ath_hw *ah);
654 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
655 bool (*rfbus_req)(struct ath_hw *ah);
656 void (*rfbus_done)(struct ath_hw *ah);
657 void (*restore_chainmask)(struct ath_hw *ah);
658 u32 (*compute_pll_control)(struct ath_hw *ah,
659 struct ath9k_channel *chan);
660 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
661 int param);
662 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
663 void (*set_radar_params)(struct ath_hw *ah,
664 struct ath_hw_radar_conf *conf);
665 int (*fast_chan_change)(struct ath_hw *ah, struct ath9k_channel *chan,
666 u8 *ini_reloaded);
667
668 /* ANI */
669 void (*ani_cache_ini_regs)(struct ath_hw *ah);
670
671 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
672 bool (*is_aic_enabled)(struct ath_hw *ah);
673 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
674 };
675
676 /**
677 * struct ath_spec_scan - parameters for Atheros spectral scan
678 *
679 * @enabled: enable/disable spectral scan
680 * @short_repeat: controls whether the chip is in spectral scan mode
681 * for 4 usec (enabled) or 204 usec (disabled)
682 * @count: number of scan results requested. There are special meanings
683 * in some chip revisions:
684 * AR92xx: highest bit set (>=128) for endless mode
685 * (spectral scan won't stopped until explicitly disabled)
686 * AR9300 and newer: 0 for endless mode
687 * @endless: true if endless mode is intended. Otherwise, count value is
688 * corrected to the next possible value.
689 * @period: time duration between successive spectral scan entry points
690 * (period*256*Tclk). Tclk = ath_common->clockrate
691 * @fft_period: PHY passes FFT frames to MAC every (fft_period+1)*4uS
692 *
693 * Note: Tclk = 40MHz or 44MHz depending upon operating mode.
694 * Typically it's 44MHz in 2/5GHz on later chips, but there's
695 * a "fast clock" check for this in 5GHz.
696 *
697 */
698 struct ath_spec_scan {
699 bool enabled;
700 bool short_repeat;
701 bool endless;
702 u8 count;
703 u8 period;
704 u8 fft_period;
705 };
706
707 /**
708 * struct ath_hw_ops - callbacks used by hardware code and driver code
709 *
710 * This structure contains callbacks designed to to be used internally by
711 * hardware code and also by the lower level driver.
712 *
713 * @config_pci_powersave:
714 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
715 *
716 * @spectral_scan_config: set parameters for spectral scan and enable/disable it
717 * @spectral_scan_trigger: trigger a spectral scan run
718 * @spectral_scan_wait: wait for a spectral scan run to finish
719 */
720 struct ath_hw_ops {
721 void (*config_pci_powersave)(struct ath_hw *ah,
722 bool power_off);
723 void (*rx_enable)(struct ath_hw *ah);
724 void (*set_desc_link)(void *ds, u32 link);
725 int (*calibrate)(struct ath_hw *ah, struct ath9k_channel *chan,
726 u8 rxchainmask, bool longcal);
727 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked,
728 u32 *sync_cause_p);
729 void (*set_txdesc)(struct ath_hw *ah, void *ds,
730 struct ath_tx_info *i);
731 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
732 struct ath_tx_status *ts);
733 int (*get_duration)(struct ath_hw *ah, const void *ds, int index);
734 void (*antdiv_comb_conf_get)(struct ath_hw *ah,
735 struct ath_hw_antcomb_conf *antconf);
736 void (*antdiv_comb_conf_set)(struct ath_hw *ah,
737 struct ath_hw_antcomb_conf *antconf);
738 void (*spectral_scan_config)(struct ath_hw *ah,
739 struct ath_spec_scan *param);
740 void (*spectral_scan_trigger)(struct ath_hw *ah);
741 void (*spectral_scan_wait)(struct ath_hw *ah);
742
743 void (*tx99_start)(struct ath_hw *ah, u32 qnum);
744 void (*tx99_stop)(struct ath_hw *ah);
745 void (*tx99_set_txpower)(struct ath_hw *ah, u8 power);
746
747 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
748 void (*set_bt_ant_diversity)(struct ath_hw *hw, bool enable);
749 #endif
750 };
751
752 struct ath_nf_limits {
753 s16 max;
754 s16 min;
755 s16 nominal;
756 };
757
758 enum ath_cal_list {
759 TX_IQ_CAL = BIT(0),
760 TX_IQ_ON_AGC_CAL = BIT(1),
761 TX_CL_CAL = BIT(2),
762 };
763
764 /* ah_flags */
765 #define AH_USE_EEPROM 0x1
766 #define AH_UNPLUGGED 0x2 /* The card has been physically removed. */
767 #define AH_FASTCC 0x4
768 #define AH_NO_EEP_SWAP 0x8 /* Do not swap EEPROM data */
769
770 struct ath_hw {
771 struct ath_ops reg_ops;
772
773 struct device *dev;
774 struct ieee80211_hw *hw;
775 struct ath_common common;
776 struct ath9k_hw_version hw_version;
777 struct ath9k_ops_config config;
778 struct ath9k_hw_capabilities caps;
779 struct ath9k_channel channels[ATH9K_NUM_CHANNELS];
780 struct ath9k_channel *curchan;
781
782 union {
783 struct ar5416_eeprom_def def;
784 struct ar5416_eeprom_4k map4k;
785 struct ar9287_eeprom map9287;
786 struct ar9300_eeprom ar9300_eep;
787 } eeprom;
788 const struct eeprom_ops *eep_ops;
789
790 bool sw_mgmt_crypto_tx;
791 bool sw_mgmt_crypto_rx;
792 bool is_pciexpress;
793 bool aspm_enabled;
794 bool is_monitoring;
795 bool need_an_top2_fixup;
796 u16 tx_trig_level;
797
798 u32 nf_regs[6];
799 struct ath_nf_limits nf_2g;
800 struct ath_nf_limits nf_5g;
801 u16 rfsilent;
802 u32 rfkill_gpio;
803 u32 rfkill_polarity;
804 u32 ah_flags;
805
806 bool reset_power_on;
807 bool htc_reset_init;
808
809 enum nl80211_iftype opmode;
810 enum ath9k_power_mode power_mode;
811
812 s8 noise;
813 struct ath9k_hw_cal_data *caldata;
814 struct ath9k_pacal_info pacal_info;
815 struct ar5416Stats stats;
816 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
817
818 enum ath9k_int imask;
819 u32 imrs2_reg;
820 u32 txok_interrupt_mask;
821 u32 txerr_interrupt_mask;
822 u32 txdesc_interrupt_mask;
823 u32 txeol_interrupt_mask;
824 u32 txurn_interrupt_mask;
825 atomic_t intr_ref_cnt;
826 bool chip_fullsleep;
827 u32 modes_index;
828
829 /* Calibration */
830 u32 supp_cals;
831 struct ath9k_cal_list iq_caldata;
832 struct ath9k_cal_list adcgain_caldata;
833 struct ath9k_cal_list adcdc_caldata;
834 struct ath9k_cal_list *cal_list;
835 struct ath9k_cal_list *cal_list_last;
836 struct ath9k_cal_list *cal_list_curr;
837 #define totalPowerMeasI meas0.unsign
838 #define totalPowerMeasQ meas1.unsign
839 #define totalIqCorrMeas meas2.sign
840 #define totalAdcIOddPhase meas0.unsign
841 #define totalAdcIEvenPhase meas1.unsign
842 #define totalAdcQOddPhase meas2.unsign
843 #define totalAdcQEvenPhase meas3.unsign
844 #define totalAdcDcOffsetIOddPhase meas0.sign
845 #define totalAdcDcOffsetIEvenPhase meas1.sign
846 #define totalAdcDcOffsetQOddPhase meas2.sign
847 #define totalAdcDcOffsetQEvenPhase meas3.sign
848 union {
849 u32 unsign[AR5416_MAX_CHAINS];
850 int32_t sign[AR5416_MAX_CHAINS];
851 } meas0;
852 union {
853 u32 unsign[AR5416_MAX_CHAINS];
854 int32_t sign[AR5416_MAX_CHAINS];
855 } meas1;
856 union {
857 u32 unsign[AR5416_MAX_CHAINS];
858 int32_t sign[AR5416_MAX_CHAINS];
859 } meas2;
860 union {
861 u32 unsign[AR5416_MAX_CHAINS];
862 int32_t sign[AR5416_MAX_CHAINS];
863 } meas3;
864 u16 cal_samples;
865 u8 enabled_cals;
866
867 u32 sta_id1_defaults;
868 u32 misc_mode;
869
870 /* Private to hardware code */
871 struct ath_hw_private_ops private_ops;
872 /* Accessed by the lower level driver */
873 struct ath_hw_ops ops;
874
875 /* Used to program the radio on non single-chip devices */
876 u32 *analogBank6Data;
877
878 int coverage_class;
879 u32 slottime;
880 u32 globaltxtimeout;
881
882 /* ANI */
883 u32 aniperiod;
884 enum ath9k_ani_cmd ani_function;
885 u32 ani_skip_count;
886 struct ar5416AniState ani;
887
888 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
889 struct ath_btcoex_hw btcoex_hw;
890 #endif
891
892 u32 intr_txqs;
893 u8 txchainmask;
894 u8 rxchainmask;
895
896 struct ath_hw_radar_conf radar_conf;
897
898 u32 originalGain[22];
899 int initPDADC;
900 int PDADCdelta;
901 int led_pin;
902 u32 gpio_mask;
903 u32 gpio_val;
904
905 struct ar5416IniArray ini_dfs;
906 struct ar5416IniArray iniModes;
907 struct ar5416IniArray iniCommon;
908 struct ar5416IniArray iniBB_RfGain;
909 struct ar5416IniArray iniBank6;
910 struct ar5416IniArray iniAddac;
911 struct ar5416IniArray iniPcieSerdes;
912 struct ar5416IniArray iniPcieSerdesLowPower;
913 struct ar5416IniArray iniModesFastClock;
914 struct ar5416IniArray iniAdditional;
915 struct ar5416IniArray iniModesRxGain;
916 struct ar5416IniArray ini_modes_rx_gain_bounds;
917 struct ar5416IniArray iniModesTxGain;
918 struct ar5416IniArray iniCckfirNormal;
919 struct ar5416IniArray iniCckfirJapan2484;
920 struct ar5416IniArray iniModes_9271_ANI_reg;
921 struct ar5416IniArray ini_radio_post_sys2ant;
922 struct ar5416IniArray ini_modes_rxgain_xlna;
923 struct ar5416IniArray ini_modes_rxgain_bb_core;
924 struct ar5416IniArray ini_modes_rxgain_bb_postamble;
925
926 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
927 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
928 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
929 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
930
931 u32 intr_gen_timer_trigger;
932 u32 intr_gen_timer_thresh;
933 struct ath_gen_timer_table hw_gen_timers;
934
935 struct ar9003_txs *ts_ring;
936 u32 ts_paddr_start;
937 u32 ts_paddr_end;
938 u16 ts_tail;
939 u16 ts_size;
940
941 u32 bb_watchdog_last_status;
942 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
943 u8 bb_hang_rx_ofdm; /* true if bb hang due to rx_ofdm */
944
945 unsigned int paprd_target_power;
946 unsigned int paprd_training_power;
947 unsigned int paprd_ratemask;
948 unsigned int paprd_ratemask_ht40;
949 bool paprd_table_write_done;
950 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
951 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
952 /*
953 * Store the permanent value of Reg 0x4004in WARegVal
954 * so we dont have to R/M/W. We should not be reading
955 * this register when in sleep states.
956 */
957 u32 WARegVal;
958
959 /* Enterprise mode cap */
960 u32 ent_mode;
961
962 #ifdef CONFIG_ATH9K_WOW
963 struct ath9k_hw_wow wow;
964 #endif
965 bool is_clk_25mhz;
966 int (*get_mac_revision)(void);
967 int (*external_reset)(void);
968 bool disable_2ghz;
969 bool disable_5ghz;
970
971 const struct firmware *eeprom_blob;
972
973 struct ath_dynack dynack;
974
975 bool tpc_enabled;
976 u8 tx_power[Ar5416RateSize];
977 u8 tx_power_stbc[Ar5416RateSize];
978 };
979
980 struct ath_bus_ops {
981 enum ath_bus_type ath_bus_type;
982 void (*read_cachesize)(struct ath_common *common, int *csz);
983 bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
984 void (*bt_coex_prep)(struct ath_common *common);
985 void (*aspm_init)(struct ath_common *common);
986 };
987
988 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
989 {
990 return &ah->common;
991 }
992
993 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
994 {
995 return &(ath9k_hw_common(ah)->regulatory);
996 }
997
998 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
999 {
1000 return &ah->private_ops;
1001 }
1002
1003 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
1004 {
1005 return &ah->ops;
1006 }
1007
1008 static inline u8 get_streams(int mask)
1009 {
1010 return !!(mask & BIT(0)) + !!(mask & BIT(1)) + !!(mask & BIT(2));
1011 }
1012
1013 /* Initialization, Detach, Reset */
1014 void ath9k_hw_deinit(struct ath_hw *ah);
1015 int ath9k_hw_init(struct ath_hw *ah);
1016 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1017 struct ath9k_hw_cal_data *caldata, bool fastcc);
1018 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
1019 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
1020
1021 /* GPIO / RFKILL / Antennae */
1022 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
1023 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
1024 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
1025 u32 ah_signal_type);
1026 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
1027 void ath9k_hw_request_gpio(struct ath_hw *ah, u32 gpio, const char *label);
1028 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
1029
1030 /* General Operation */
1031 void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
1032 int hw_delay);
1033 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
1034 void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
1035 int column, unsigned int *writecnt);
1036 void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size);
1037 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
1038 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
1039 u8 phy, int kbps,
1040 u32 frameLen, u16 rateix, bool shortPreamble);
1041 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
1042 struct ath9k_channel *chan,
1043 struct chan_centers *centers);
1044 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
1045 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
1046 bool ath9k_hw_phy_disable(struct ath_hw *ah);
1047 bool ath9k_hw_disable(struct ath_hw *ah);
1048 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test);
1049 void ath9k_hw_setopmode(struct ath_hw *ah);
1050 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
1051 void ath9k_hw_write_associd(struct ath_hw *ah);
1052 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
1053 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
1054 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
1055 void ath9k_hw_reset_tsf(struct ath_hw *ah);
1056 u32 ath9k_hw_get_tsf_offset(struct timespec *last, struct timespec *cur);
1057 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set);
1058 void ath9k_hw_init_global_settings(struct ath_hw *ah);
1059 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah);
1060 void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan);
1061 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
1062 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1063 const struct ath9k_beacon_state *bs);
1064 void ath9k_hw_check_nav(struct ath_hw *ah);
1065 bool ath9k_hw_check_alive(struct ath_hw *ah);
1066
1067 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
1068
1069 /* Generic hw timer primitives */
1070 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
1071 void (*trigger)(void *),
1072 void (*overflow)(void *),
1073 void *arg,
1074 u8 timer_index);
1075 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
1076 struct ath_gen_timer *timer,
1077 u32 timer_next,
1078 u32 timer_period);
1079 void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah);
1080 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
1081
1082 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
1083 void ath_gen_timer_isr(struct ath_hw *hw);
1084
1085 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
1086
1087 /* PHY */
1088 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1089 u32 *coef_mantissa, u32 *coef_exponent);
1090 void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
1091 bool test);
1092
1093 /*
1094 * Code Specific to AR5008, AR9001 or AR9002,
1095 * we stuff these here to avoid callbacks for AR9003.
1096 */
1097 int ar9002_hw_rf_claim(struct ath_hw *ah);
1098 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
1099
1100 /*
1101 * Code specific to AR9003, we stuff these here to avoid callbacks
1102 * for older families
1103 */
1104 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah);
1105 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
1106 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
1107 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
1108 void ar9003_hw_disable_phy_restart(struct ath_hw *ah);
1109 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
1110 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
1111 struct ath9k_hw_cal_data *caldata,
1112 int chain);
1113 int ar9003_paprd_create_curve(struct ath_hw *ah,
1114 struct ath9k_hw_cal_data *caldata, int chain);
1115 void ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
1116 int ar9003_paprd_init_table(struct ath_hw *ah);
1117 bool ar9003_paprd_is_done(struct ath_hw *ah);
1118 bool ar9003_is_paprd_enabled(struct ath_hw *ah);
1119 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx);
1120 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1121 struct ath9k_channel *chan);
1122 void ar5008_hw_cmn_spur_mitigate(struct ath_hw *ah,
1123 struct ath9k_channel *chan, int bin);
1124 void ar5008_hw_init_rate_txpower(struct ath_hw *ah, int16_t *rate_array,
1125 struct ath9k_channel *chan, int ht40_delta);
1126
1127 /* Hardware family op attach helpers */
1128 int ar5008_hw_attach_phy_ops(struct ath_hw *ah);
1129 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
1130 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
1131
1132 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
1133 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
1134
1135 int ar9002_hw_attach_ops(struct ath_hw *ah);
1136 void ar9003_hw_attach_ops(struct ath_hw *ah);
1137
1138 void ar9002_hw_load_ani_reg(struct ath_hw *ah, struct ath9k_channel *chan);
1139
1140 void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
1141 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
1142
1143 void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us);
1144 void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us);
1145 void ath9k_hw_setslottime(struct ath_hw *ah, u32 us);
1146
1147 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1148 void ar9003_hw_attach_aic_ops(struct ath_hw *ah);
1149 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1150 {
1151 return ah->btcoex_hw.enabled;
1152 }
1153 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1154 {
1155 return ah->common.btcoex_enabled &&
1156 (ah->caps.hw_caps & ATH9K_HW_CAP_MCI);
1157
1158 }
1159 void ath9k_hw_btcoex_enable(struct ath_hw *ah);
1160 static inline enum ath_btcoex_scheme
1161 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1162 {
1163 return ah->btcoex_hw.scheme;
1164 }
1165 #else
1166 static inline void ar9003_hw_attach_aic_ops(struct ath_hw *ah)
1167 {
1168 }
1169 static inline bool ath9k_hw_btcoex_is_enabled(struct ath_hw *ah)
1170 {
1171 return false;
1172 }
1173 static inline bool ath9k_hw_mci_is_enabled(struct ath_hw *ah)
1174 {
1175 return false;
1176 }
1177 static inline void ath9k_hw_btcoex_enable(struct ath_hw *ah)
1178 {
1179 }
1180 static inline enum ath_btcoex_scheme
1181 ath9k_hw_get_btcoex_scheme(struct ath_hw *ah)
1182 {
1183 return ATH_BTCOEX_CFG_NONE;
1184 }
1185 #endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
1186
1187
1188 #ifdef CONFIG_ATH9K_WOW
1189 int ath9k_hw_wow_apply_pattern(struct ath_hw *ah, u8 *user_pattern,
1190 u8 *user_mask, int pattern_count,
1191 int pattern_len);
1192 u32 ath9k_hw_wow_wakeup(struct ath_hw *ah);
1193 void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable);
1194 #else
1195 static inline int ath9k_hw_wow_apply_pattern(struct ath_hw *ah,
1196 u8 *user_pattern,
1197 u8 *user_mask,
1198 int pattern_count,
1199 int pattern_len)
1200 {
1201 return 0;
1202 }
1203 static inline u32 ath9k_hw_wow_wakeup(struct ath_hw *ah)
1204 {
1205 return 0;
1206 }
1207 static inline void ath9k_hw_wow_enable(struct ath_hw *ah, u32 pattern_enable)
1208 {
1209 }
1210 #endif
1211
1212 #define ATH9K_CLOCK_RATE_CCK 22
1213 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
1214 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
1215 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
1216
1217 #endif
Linux with added FPC-III support