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Linux 4.4.145
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / main.c
blob3abc64574116f17b913c94ec4738a11cf1ef785d
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
23 {
24 /*
25 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
26 * 0 for no restriction
27 * 1 for 1/4 us
28 * 2 for 1/2 us
29 * 3 for 1 us
30 * 4 for 2 us
31 * 5 for 4 us
32 * 6 for 8 us
33 * 7 for 16 us
34 */
35 switch (mpdudensity) {
36 case 0:
37 return 0;
38 case 1:
39 case 2:
40 case 3:
41 /* Our lower layer calculations limit our precision to
42 1 microsecond */
43 return 1;
44 case 4:
45 return 2;
46 case 5:
47 return 4;
48 case 6:
49 return 8;
50 case 7:
51 return 16;
52 default:
53 return 0;
54 }
55 }
56
57 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq,
58 bool sw_pending)
59 {
60 bool pending = false;
61
62 spin_lock_bh(&txq->axq_lock);
63
64 if (txq->axq_depth) {
65 pending = true;
66 goto out;
67 }
68
69 if (!sw_pending)
70 goto out;
71
72 if (txq->mac80211_qnum >= 0) {
73 struct list_head *list;
74
75 list = &sc->cur_chan->acq[txq->mac80211_qnum];
76 if (!list_empty(list))
77 pending = true;
78 }
79 out:
80 spin_unlock_bh(&txq->axq_lock);
81 return pending;
82 }
83
84 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
85 {
86 unsigned long flags;
87 bool ret;
88
89 spin_lock_irqsave(&sc->sc_pm_lock, flags);
90 ret = ath9k_hw_setpower(sc->sc_ah, mode);
91 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
92
93 return ret;
94 }
95
96 void ath_ps_full_sleep(unsigned long data)
97 {
98 struct ath_softc *sc = (struct ath_softc *) data;
99 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
100 bool reset;
101
102 spin_lock(&common->cc_lock);
103 ath_hw_cycle_counters_update(common);
104 spin_unlock(&common->cc_lock);
105
106 ath9k_hw_setrxabort(sc->sc_ah, 1);
107 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
108
109 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
110 }
111
112 void ath9k_ps_wakeup(struct ath_softc *sc)
113 {
114 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
115 unsigned long flags;
116 enum ath9k_power_mode power_mode;
117
118 spin_lock_irqsave(&sc->sc_pm_lock, flags);
119 if (++sc->ps_usecount != 1)
120 goto unlock;
121
122 del_timer_sync(&sc->sleep_timer);
123 power_mode = sc->sc_ah->power_mode;
124 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
125
126 /*
127 * While the hardware is asleep, the cycle counters contain no
128 * useful data. Better clear them now so that they don't mess up
129 * survey data results.
130 */
131 if (power_mode != ATH9K_PM_AWAKE) {
132 spin_lock(&common->cc_lock);
133 ath_hw_cycle_counters_update(common);
134 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
135 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
136 spin_unlock(&common->cc_lock);
137 }
138
139 unlock:
140 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
141 }
142
143 void ath9k_ps_restore(struct ath_softc *sc)
144 {
145 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
146 enum ath9k_power_mode mode;
147 unsigned long flags;
148
149 spin_lock_irqsave(&sc->sc_pm_lock, flags);
150 if (--sc->ps_usecount != 0)
151 goto unlock;
152
153 if (sc->ps_idle) {
154 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
155 goto unlock;
156 }
157
158 if (sc->ps_enabled &&
159 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
160 PS_WAIT_FOR_CAB |
161 PS_WAIT_FOR_PSPOLL_DATA |
162 PS_WAIT_FOR_TX_ACK |
163 PS_WAIT_FOR_ANI))) {
164 mode = ATH9K_PM_NETWORK_SLEEP;
165 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
166 ath9k_btcoex_stop_gen_timer(sc);
167 } else {
168 goto unlock;
169 }
170
171 spin_lock(&common->cc_lock);
172 ath_hw_cycle_counters_update(common);
173 spin_unlock(&common->cc_lock);
174
175 ath9k_hw_setpower(sc->sc_ah, mode);
176
177 unlock:
178 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
179 }
180
181 static void __ath_cancel_work(struct ath_softc *sc)
182 {
183 cancel_work_sync(&sc->paprd_work);
184 cancel_delayed_work_sync(&sc->tx_complete_work);
185 cancel_delayed_work_sync(&sc->hw_pll_work);
186
187 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
188 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
189 cancel_work_sync(&sc->mci_work);
190 #endif
191 }
192
193 void ath_cancel_work(struct ath_softc *sc)
194 {
195 __ath_cancel_work(sc);
196 cancel_work_sync(&sc->hw_reset_work);
197 }
198
199 void ath_restart_work(struct ath_softc *sc)
200 {
201 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
202
203 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
204 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
205 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
206
207 ath_start_ani(sc);
208 }
209
210 static bool ath_prepare_reset(struct ath_softc *sc)
211 {
212 struct ath_hw *ah = sc->sc_ah;
213 bool ret = true;
214
215 ieee80211_stop_queues(sc->hw);
216 ath_stop_ani(sc);
217 ath9k_hw_disable_interrupts(ah);
218
219 if (AR_SREV_9300_20_OR_LATER(ah)) {
220 ret &= ath_stoprecv(sc);
221 ret &= ath_drain_all_txq(sc);
222 } else {
223 ret &= ath_drain_all_txq(sc);
224 ret &= ath_stoprecv(sc);
225 }
226
227 return ret;
228 }
229
230 static bool ath_complete_reset(struct ath_softc *sc, bool start)
231 {
232 struct ath_hw *ah = sc->sc_ah;
233 struct ath_common *common = ath9k_hw_common(ah);
234 unsigned long flags;
235
236 ath9k_calculate_summary_state(sc, sc->cur_chan);
237 ath_startrecv(sc);
238 ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
239 sc->cur_chan->txpower,
240 &sc->cur_chan->cur_txpower);
241 clear_bit(ATH_OP_HW_RESET, &common->op_flags);
242
243 if (!sc->cur_chan->offchannel && start) {
244 /* restore per chanctx TSF timer */
245 if (sc->cur_chan->tsf_val) {
246 u32 offset;
247
248 offset = ath9k_hw_get_tsf_offset(&sc->cur_chan->tsf_ts,
249 NULL);
250 ath9k_hw_settsf64(ah, sc->cur_chan->tsf_val + offset);
251 }
252
253
254 if (!test_bit(ATH_OP_BEACONS, &common->op_flags))
255 goto work;
256
257 if (ah->opmode == NL80211_IFTYPE_STATION &&
258 test_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags)) {
259 spin_lock_irqsave(&sc->sc_pm_lock, flags);
260 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
261 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
262 } else {
263 ath9k_set_beacon(sc);
264 }
265 work:
266 ath_restart_work(sc);
267 ath_txq_schedule_all(sc);
268 }
269
270 sc->gtt_cnt = 0;
271
272 ath9k_hw_set_interrupts(ah);
273 ath9k_hw_enable_interrupts(ah);
274 ieee80211_wake_queues(sc->hw);
275 ath9k_p2p_ps_timer(sc);
276
277 return true;
278 }
279
280 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
281 {
282 struct ath_hw *ah = sc->sc_ah;
283 struct ath_common *common = ath9k_hw_common(ah);
284 struct ath9k_hw_cal_data *caldata = NULL;
285 bool fastcc = true;
286 int r;
287
288 __ath_cancel_work(sc);
289
290 disable_irq(sc->irq);
291 tasklet_disable(&sc->intr_tq);
292 tasklet_disable(&sc->bcon_tasklet);
293 spin_lock_bh(&sc->sc_pcu_lock);
294
295 if (!sc->cur_chan->offchannel) {
296 fastcc = false;
297 caldata = &sc->cur_chan->caldata;
298 }
299
300 if (!hchan) {
301 fastcc = false;
302 hchan = ah->curchan;
303 }
304
305 if (!ath_prepare_reset(sc))
306 fastcc = false;
307
308 if (ath9k_is_chanctx_enabled())
309 fastcc = false;
310
311 spin_lock_bh(&sc->chan_lock);
312 sc->cur_chandef = sc->cur_chan->chandef;
313 spin_unlock_bh(&sc->chan_lock);
314
315 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
316 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
317
318 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
319 if (r) {
320 ath_err(common,
321 "Unable to reset channel, reset status %d\n", r);
322
323 ath9k_hw_enable_interrupts(ah);
324 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
325
326 goto out;
327 }
328
329 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
330 sc->cur_chan->offchannel)
331 ath9k_mci_set_txpower(sc, true, false);
332
333 if (!ath_complete_reset(sc, true))
334 r = -EIO;
335
336 out:
337 enable_irq(sc->irq);
338 spin_unlock_bh(&sc->sc_pcu_lock);
339 tasklet_enable(&sc->bcon_tasklet);
340 tasklet_enable(&sc->intr_tq);
341
342 return r;
343 }
344
345 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
346 struct ieee80211_vif *vif)
347 {
348 struct ath_node *an;
349 an = (struct ath_node *)sta->drv_priv;
350
351 an->sc = sc;
352 an->sta = sta;
353 an->vif = vif;
354 memset(&an->key_idx, 0, sizeof(an->key_idx));
355
356 ath_tx_node_init(sc, an);
357
358 ath_dynack_node_init(sc->sc_ah, an);
359 }
360
361 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
362 {
363 struct ath_node *an = (struct ath_node *)sta->drv_priv;
364 ath_tx_node_cleanup(sc, an);
365
366 ath_dynack_node_deinit(sc->sc_ah, an);
367 }
368
369 void ath9k_tasklet(unsigned long data)
370 {
371 struct ath_softc *sc = (struct ath_softc *)data;
372 struct ath_hw *ah = sc->sc_ah;
373 struct ath_common *common = ath9k_hw_common(ah);
374 enum ath_reset_type type;
375 unsigned long flags;
376 u32 status;
377 u32 rxmask;
378
379 spin_lock_irqsave(&sc->intr_lock, flags);
380 status = sc->intrstatus;
381 sc->intrstatus = 0;
382 spin_unlock_irqrestore(&sc->intr_lock, flags);
383
384 ath9k_ps_wakeup(sc);
385 spin_lock(&sc->sc_pcu_lock);
386
387 if (status & ATH9K_INT_FATAL) {
388 type = RESET_TYPE_FATAL_INT;
389 ath9k_queue_reset(sc, type);
390 ath_dbg(common, RESET, "FATAL: Skipping interrupts\n");
391 goto out;
392 }
393
394 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
395 (status & ATH9K_INT_BB_WATCHDOG)) {
396 spin_lock(&common->cc_lock);
397 ath_hw_cycle_counters_update(common);
398 ar9003_hw_bb_watchdog_dbg_info(ah);
399 spin_unlock(&common->cc_lock);
400
401 if (ar9003_hw_bb_watchdog_check(ah)) {
402 type = RESET_TYPE_BB_WATCHDOG;
403 ath9k_queue_reset(sc, type);
404
405 ath_dbg(common, RESET,
406 "BB_WATCHDOG: Skipping interrupts\n");
407 goto out;
408 }
409 }
410
411 if (status & ATH9K_INT_GTT) {
412 sc->gtt_cnt++;
413
414 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
415 type = RESET_TYPE_TX_GTT;
416 ath9k_queue_reset(sc, type);
417 ath_dbg(common, RESET,
418 "GTT: Skipping interrupts\n");
419 goto out;
420 }
421 }
422
423 spin_lock_irqsave(&sc->sc_pm_lock, flags);
424 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
425 /*
426 * TSF sync does not look correct; remain awake to sync with
427 * the next Beacon.
428 */
429 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
430 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
431 }
432 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
433
434 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
435 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
436 ATH9K_INT_RXORN);
437 else
438 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
439
440 if (status & rxmask) {
441 /* Check for high priority Rx first */
442 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
443 (status & ATH9K_INT_RXHP))
444 ath_rx_tasklet(sc, 0, true);
445
446 ath_rx_tasklet(sc, 0, false);
447 }
448
449 if (status & ATH9K_INT_TX) {
450 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
451 /*
452 * For EDMA chips, TX completion is enabled for the
453 * beacon queue, so if a beacon has been transmitted
454 * successfully after a GTT interrupt, the GTT counter
455 * gets reset to zero here.
456 */
457 sc->gtt_cnt = 0;
458
459 ath_tx_edma_tasklet(sc);
460 } else {
461 ath_tx_tasklet(sc);
462 }
463
464 wake_up(&sc->tx_wait);
465 }
466
467 if (status & ATH9K_INT_GENTIMER)
468 ath_gen_timer_isr(sc->sc_ah);
469
470 ath9k_btcoex_handle_interrupt(sc, status);
471
472 /* re-enable hardware interrupt */
473 ath9k_hw_resume_interrupts(ah);
474 out:
475 spin_unlock(&sc->sc_pcu_lock);
476 ath9k_ps_restore(sc);
477 }
478
479 irqreturn_t ath_isr(int irq, void *dev)
480 {
481 #define SCHED_INTR ( \
482 ATH9K_INT_FATAL | \
483 ATH9K_INT_BB_WATCHDOG | \
484 ATH9K_INT_RXORN | \
485 ATH9K_INT_RXEOL | \
486 ATH9K_INT_RX | \
487 ATH9K_INT_RXLP | \
488 ATH9K_INT_RXHP | \
489 ATH9K_INT_TX | \
490 ATH9K_INT_BMISS | \
491 ATH9K_INT_CST | \
492 ATH9K_INT_GTT | \
493 ATH9K_INT_TSFOOR | \
494 ATH9K_INT_GENTIMER | \
495 ATH9K_INT_MCI)
496
497 struct ath_softc *sc = dev;
498 struct ath_hw *ah = sc->sc_ah;
499 struct ath_common *common = ath9k_hw_common(ah);
500 enum ath9k_int status;
501 u32 sync_cause = 0;
502 bool sched = false;
503
504 /*
505 * The hardware is not ready/present, don't
506 * touch anything. Note this can happen early
507 * on if the IRQ is shared.
508 */
509 if (!ah || test_bit(ATH_OP_INVALID, &common->op_flags))
510 return IRQ_NONE;
511
512 /* shared irq, not for us */
513 if (!ath9k_hw_intrpend(ah))
514 return IRQ_NONE;
515
516 /*
517 * Figure out the reason(s) for the interrupt. Note
518 * that the hal returns a pseudo-ISR that may include
519 * bits we haven't explicitly enabled so we mask the
520 * value to insure we only process bits we requested.
521 */
522 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
523 ath9k_debug_sync_cause(sc, sync_cause);
524 status &= ah->imask; /* discard unasked-for bits */
525
526 if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
527 return IRQ_HANDLED;
528
529 /*
530 * If there are no status bits set, then this interrupt was not
531 * for me (should have been caught above).
532 */
533 if (!status)
534 return IRQ_NONE;
535
536 /* Cache the status */
537 spin_lock(&sc->intr_lock);
538 sc->intrstatus |= status;
539 spin_unlock(&sc->intr_lock);
540
541 if (status & SCHED_INTR)
542 sched = true;
543
544 /*
545 * If a FATAL interrupt is received, we have to reset the chip
546 * immediately.
547 */
548 if (status & ATH9K_INT_FATAL)
549 goto chip_reset;
550
551 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
552 (status & ATH9K_INT_BB_WATCHDOG))
553 goto chip_reset;
554
555 if (status & ATH9K_INT_SWBA)
556 tasklet_schedule(&sc->bcon_tasklet);
557
558 if (status & ATH9K_INT_TXURN)
559 ath9k_hw_updatetxtriglevel(ah, true);
560
561 if (status & ATH9K_INT_RXEOL) {
562 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
563 ath9k_hw_set_interrupts(ah);
564 }
565
566 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
567 if (status & ATH9K_INT_TIM_TIMER) {
568 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
569 goto chip_reset;
570 /* Clear RxAbort bit so that we can
571 * receive frames */
572 ath9k_setpower(sc, ATH9K_PM_AWAKE);
573 spin_lock(&sc->sc_pm_lock);
574 ath9k_hw_setrxabort(sc->sc_ah, 0);
575 sc->ps_flags |= PS_WAIT_FOR_BEACON;
576 spin_unlock(&sc->sc_pm_lock);
577 }
578
579 chip_reset:
580
581 ath_debug_stat_interrupt(sc, status);
582
583 if (sched) {
584 /* turn off every interrupt */
585 ath9k_hw_kill_interrupts(ah);
586 tasklet_schedule(&sc->intr_tq);
587 }
588
589 return IRQ_HANDLED;
590
591 #undef SCHED_INTR
592 }
593
594 /*
595 * This function is called when a HW reset cannot be deferred
596 * and has to be immediate.
597 */
598 int ath_reset(struct ath_softc *sc, struct ath9k_channel *hchan)
599 {
600 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
601 int r;
602
603 ath9k_hw_kill_interrupts(sc->sc_ah);
604 set_bit(ATH_OP_HW_RESET, &common->op_flags);
605
606 ath9k_ps_wakeup(sc);
607 r = ath_reset_internal(sc, hchan);
608 ath9k_ps_restore(sc);
609
610 return r;
611 }
612
613 /*
614 * When a HW reset can be deferred, it is added to the
615 * hw_reset_work workqueue, but we set ATH_OP_HW_RESET before
616 * queueing.
617 */
618 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
619 {
620 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
621 #ifdef CONFIG_ATH9K_DEBUGFS
622 RESET_STAT_INC(sc, type);
623 #endif
624 ath9k_hw_kill_interrupts(sc->sc_ah);
625 set_bit(ATH_OP_HW_RESET, &common->op_flags);
626 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
627 }
628
629 void ath_reset_work(struct work_struct *work)
630 {
631 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
632
633 ath9k_ps_wakeup(sc);
634 ath_reset_internal(sc, NULL);
635 ath9k_ps_restore(sc);
636 }
637
638 /**********************/
639 /* mac80211 callbacks */
640 /**********************/
641
642 static int ath9k_start(struct ieee80211_hw *hw)
643 {
644 struct ath_softc *sc = hw->priv;
645 struct ath_hw *ah = sc->sc_ah;
646 struct ath_common *common = ath9k_hw_common(ah);
647 struct ieee80211_channel *curchan = sc->cur_chan->chandef.chan;
648 struct ath_chanctx *ctx = sc->cur_chan;
649 struct ath9k_channel *init_channel;
650 int r;
651
652 ath_dbg(common, CONFIG,
653 "Starting driver with initial channel: %d MHz\n",
654 curchan->center_freq);
655
656 ath9k_ps_wakeup(sc);
657 mutex_lock(&sc->mutex);
658
659 init_channel = ath9k_cmn_get_channel(hw, ah, &ctx->chandef);
660 sc->cur_chandef = hw->conf.chandef;
661
662 /* Reset SERDES registers */
663 ath9k_hw_configpcipowersave(ah, false);
664
665 /*
666 * The basic interface to setting the hardware in a good
667 * state is ``reset''. On return the hardware is known to
668 * be powered up and with interrupts disabled. This must
669 * be followed by initialization of the appropriate bits
670 * and then setup of the interrupt mask.
671 */
672 spin_lock_bh(&sc->sc_pcu_lock);
673
674 atomic_set(&ah->intr_ref_cnt, -1);
675
676 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
677 if (r) {
678 ath_err(common,
679 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
680 r, curchan->center_freq);
681 ah->reset_power_on = false;
682 }
683
684 /* Setup our intr mask. */
685 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
686 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
687 ATH9K_INT_GLOBAL;
688
689 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
690 ah->imask |= ATH9K_INT_RXHP |
691 ATH9K_INT_RXLP;
692 else
693 ah->imask |= ATH9K_INT_RX;
694
695 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
696 ah->imask |= ATH9K_INT_BB_WATCHDOG;
697
698 /*
699 * Enable GTT interrupts only for AR9003/AR9004 chips
700 * for now.
701 */
702 if (AR_SREV_9300_20_OR_LATER(ah))
703 ah->imask |= ATH9K_INT_GTT;
704
705 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
706 ah->imask |= ATH9K_INT_CST;
707
708 ath_mci_enable(sc);
709
710 clear_bit(ATH_OP_INVALID, &common->op_flags);
711 sc->sc_ah->is_monitoring = false;
712
713 if (!ath_complete_reset(sc, false))
714 ah->reset_power_on = false;
715
716 if (ah->led_pin >= 0) {
717 ath9k_hw_cfg_output(ah, ah->led_pin,
718 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
719 ath9k_hw_set_gpio(ah, ah->led_pin,
720 (ah->config.led_active_high) ? 1 : 0);
721 }
722
723 /*
724 * Reset key cache to sane defaults (all entries cleared) instead of
725 * semi-random values after suspend/resume.
726 */
727 ath9k_cmn_init_crypto(sc->sc_ah);
728
729 ath9k_hw_reset_tsf(ah);
730
731 spin_unlock_bh(&sc->sc_pcu_lock);
732
733 mutex_unlock(&sc->mutex);
734
735 ath9k_ps_restore(sc);
736
737 return 0;
738 }
739
740 static void ath9k_tx(struct ieee80211_hw *hw,
741 struct ieee80211_tx_control *control,
742 struct sk_buff *skb)
743 {
744 struct ath_softc *sc = hw->priv;
745 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
746 struct ath_tx_control txctl;
747 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
748 unsigned long flags;
749
750 if (sc->ps_enabled) {
751 /*
752 * mac80211 does not set PM field for normal data frames, so we
753 * need to update that based on the current PS mode.
754 */
755 if (ieee80211_is_data(hdr->frame_control) &&
756 !ieee80211_is_nullfunc(hdr->frame_control) &&
757 !ieee80211_has_pm(hdr->frame_control)) {
758 ath_dbg(common, PS,
759 "Add PM=1 for a TX frame while in PS mode\n");
760 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
761 }
762 }
763
764 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
765 /*
766 * We are using PS-Poll and mac80211 can request TX while in
767 * power save mode. Need to wake up hardware for the TX to be
768 * completed and if needed, also for RX of buffered frames.
769 */
770 ath9k_ps_wakeup(sc);
771 spin_lock_irqsave(&sc->sc_pm_lock, flags);
772 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
773 ath9k_hw_setrxabort(sc->sc_ah, 0);
774 if (ieee80211_is_pspoll(hdr->frame_control)) {
775 ath_dbg(common, PS,
776 "Sending PS-Poll to pick a buffered frame\n");
777 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
778 } else {
779 ath_dbg(common, PS, "Wake up to complete TX\n");
780 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
781 }
782 /*
783 * The actual restore operation will happen only after
784 * the ps_flags bit is cleared. We are just dropping
785 * the ps_usecount here.
786 */
787 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
788 ath9k_ps_restore(sc);
789 }
790
791 /*
792 * Cannot tx while the hardware is in full sleep, it first needs a full
793 * chip reset to recover from that
794 */
795 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
796 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
797 goto exit;
798 }
799
800 memset(&txctl, 0, sizeof(struct ath_tx_control));
801 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
802 txctl.sta = control->sta;
803
804 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
805
806 if (ath_tx_start(hw, skb, &txctl) != 0) {
807 ath_dbg(common, XMIT, "TX failed\n");
808 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
809 goto exit;
810 }
811
812 return;
813 exit:
814 ieee80211_free_txskb(hw, skb);
815 }
816
817 static void ath9k_stop(struct ieee80211_hw *hw)
818 {
819 struct ath_softc *sc = hw->priv;
820 struct ath_hw *ah = sc->sc_ah;
821 struct ath_common *common = ath9k_hw_common(ah);
822 bool prev_idle;
823
824 ath9k_deinit_channel_context(sc);
825
826 mutex_lock(&sc->mutex);
827
828 ath_cancel_work(sc);
829
830 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
831 ath_dbg(common, ANY, "Device not present\n");
832 mutex_unlock(&sc->mutex);
833 return;
834 }
835
836 /* Ensure HW is awake when we try to shut it down. */
837 ath9k_ps_wakeup(sc);
838
839 spin_lock_bh(&sc->sc_pcu_lock);
840
841 /* prevent tasklets to enable interrupts once we disable them */
842 ah->imask &= ~ATH9K_INT_GLOBAL;
843
844 /* make sure h/w will not generate any interrupt
845 * before setting the invalid flag. */
846 ath9k_hw_disable_interrupts(ah);
847
848 spin_unlock_bh(&sc->sc_pcu_lock);
849
850 /* we can now sync irq and kill any running tasklets, since we already
851 * disabled interrupts and not holding a spin lock */
852 synchronize_irq(sc->irq);
853 tasklet_kill(&sc->intr_tq);
854 tasklet_kill(&sc->bcon_tasklet);
855
856 prev_idle = sc->ps_idle;
857 sc->ps_idle = true;
858
859 spin_lock_bh(&sc->sc_pcu_lock);
860
861 if (ah->led_pin >= 0) {
862 ath9k_hw_set_gpio(ah, ah->led_pin,
863 (ah->config.led_active_high) ? 0 : 1);
864 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
865 }
866
867 ath_prepare_reset(sc);
868
869 if (sc->rx.frag) {
870 dev_kfree_skb_any(sc->rx.frag);
871 sc->rx.frag = NULL;
872 }
873
874 if (!ah->curchan)
875 ah->curchan = ath9k_cmn_get_channel(hw, ah,
876 &sc->cur_chan->chandef);
877
878 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
879
880 set_bit(ATH_OP_INVALID, &common->op_flags);
881
882 ath9k_hw_phy_disable(ah);
883
884 ath9k_hw_configpcipowersave(ah, true);
885
886 spin_unlock_bh(&sc->sc_pcu_lock);
887
888 ath9k_ps_restore(sc);
889
890 sc->ps_idle = prev_idle;
891
892 mutex_unlock(&sc->mutex);
893
894 ath_dbg(common, CONFIG, "Driver halt\n");
895 }
896
897 static bool ath9k_uses_beacons(int type)
898 {
899 switch (type) {
900 case NL80211_IFTYPE_AP:
901 case NL80211_IFTYPE_ADHOC:
902 case NL80211_IFTYPE_MESH_POINT:
903 return true;
904 default:
905 return false;
906 }
907 }
908
909 static void ath9k_vif_iter(struct ath9k_vif_iter_data *iter_data,
910 u8 *mac, struct ieee80211_vif *vif)
911 {
912 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
913 int i;
914
915 if (iter_data->has_hw_macaddr) {
916 for (i = 0; i < ETH_ALEN; i++)
917 iter_data->mask[i] &=
918 ~(iter_data->hw_macaddr[i] ^ mac[i]);
919 } else {
920 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
921 iter_data->has_hw_macaddr = true;
922 }
923
924 if (!vif->bss_conf.use_short_slot)
925 iter_data->slottime = ATH9K_SLOT_TIME_20;
926
927 switch (vif->type) {
928 case NL80211_IFTYPE_AP:
929 iter_data->naps++;
930 break;
931 case NL80211_IFTYPE_STATION:
932 iter_data->nstations++;
933 if (avp->assoc && !iter_data->primary_sta)
934 iter_data->primary_sta = vif;
935 break;
936 case NL80211_IFTYPE_OCB:
937 iter_data->nocbs++;
938 break;
939 case NL80211_IFTYPE_ADHOC:
940 iter_data->nadhocs++;
941 if (vif->bss_conf.enable_beacon)
942 iter_data->beacons = true;
943 break;
944 case NL80211_IFTYPE_MESH_POINT:
945 iter_data->nmeshes++;
946 if (vif->bss_conf.enable_beacon)
947 iter_data->beacons = true;
948 break;
949 case NL80211_IFTYPE_WDS:
950 iter_data->nwds++;
951 break;
952 default:
953 break;
954 }
955 }
956
957 static void ath9k_update_bssid_mask(struct ath_softc *sc,
958 struct ath_chanctx *ctx,
959 struct ath9k_vif_iter_data *iter_data)
960 {
961 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
962 struct ath_vif *avp;
963 int i;
964
965 if (!ath9k_is_chanctx_enabled())
966 return;
967
968 list_for_each_entry(avp, &ctx->vifs, list) {
969 if (ctx->nvifs_assigned != 1)
970 continue;
971
972 if (!avp->vif->p2p || !iter_data->has_hw_macaddr)
973 continue;
974
975 ether_addr_copy(common->curbssid, avp->bssid);
976
977 /* perm_addr will be used as the p2p device address. */
978 for (i = 0; i < ETH_ALEN; i++)
979 iter_data->mask[i] &=
980 ~(iter_data->hw_macaddr[i] ^
981 sc->hw->wiphy->perm_addr[i]);
982 }
983 }
984
985 /* Called with sc->mutex held. */
986 void ath9k_calculate_iter_data(struct ath_softc *sc,
987 struct ath_chanctx *ctx,
988 struct ath9k_vif_iter_data *iter_data)
989 {
990 struct ath_vif *avp;
991
992 /*
993 * The hardware will use primary station addr together with the
994 * BSSID mask when matching addresses.
995 */
996 memset(iter_data, 0, sizeof(*iter_data));
997 eth_broadcast_addr(iter_data->mask);
998 iter_data->slottime = ATH9K_SLOT_TIME_9;
999
1000 list_for_each_entry(avp, &ctx->vifs, list)
1001 ath9k_vif_iter(iter_data, avp->vif->addr, avp->vif);
1002
1003 ath9k_update_bssid_mask(sc, ctx, iter_data);
1004 }
1005
1006 static void ath9k_set_assoc_state(struct ath_softc *sc,
1007 struct ieee80211_vif *vif, bool changed)
1008 {
1009 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1010 struct ath_vif *avp = (struct ath_vif *)vif->drv_priv;
1011 unsigned long flags;
1012
1013 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1014
1015 ether_addr_copy(common->curbssid, avp->bssid);
1016 common->curaid = avp->aid;
1017 ath9k_hw_write_associd(sc->sc_ah);
1018
1019 if (changed) {
1020 common->last_rssi = ATH_RSSI_DUMMY_MARKER;
1021 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1022
1023 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1024 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1025 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1026 }
1027
1028 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1029 ath9k_mci_update_wlan_channels(sc, false);
1030
1031 ath_dbg(common, CONFIG,
1032 "Primary Station interface: %pM, BSSID: %pM\n",
1033 vif->addr, common->curbssid);
1034 }
1035
1036 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1037 static void ath9k_set_offchannel_state(struct ath_softc *sc)
1038 {
1039 struct ath_hw *ah = sc->sc_ah;
1040 struct ath_common *common = ath9k_hw_common(ah);
1041 struct ieee80211_vif *vif = NULL;
1042
1043 ath9k_ps_wakeup(sc);
1044
1045 if (sc->offchannel.state < ATH_OFFCHANNEL_ROC_START)
1046 vif = sc->offchannel.scan_vif;
1047 else
1048 vif = sc->offchannel.roc_vif;
1049
1050 if (WARN_ON(!vif))
1051 goto exit;
1052
1053 eth_zero_addr(common->curbssid);
1054 eth_broadcast_addr(common->bssidmask);
1055 memcpy(common->macaddr, vif->addr, ETH_ALEN);
1056 common->curaid = 0;
1057 ah->opmode = vif->type;
1058 ah->imask &= ~ATH9K_INT_SWBA;
1059 ah->imask &= ~ATH9K_INT_TSFOOR;
1060 ah->slottime = ATH9K_SLOT_TIME_9;
1061
1062 ath_hw_setbssidmask(common);
1063 ath9k_hw_setopmode(ah);
1064 ath9k_hw_write_associd(sc->sc_ah);
1065 ath9k_hw_set_interrupts(ah);
1066 ath9k_hw_init_global_settings(ah);
1067
1068 exit:
1069 ath9k_ps_restore(sc);
1070 }
1071 #endif
1072
1073 /* Called with sc->mutex held. */
1074 void ath9k_calculate_summary_state(struct ath_softc *sc,
1075 struct ath_chanctx *ctx)
1076 {
1077 struct ath_hw *ah = sc->sc_ah;
1078 struct ath_common *common = ath9k_hw_common(ah);
1079 struct ath9k_vif_iter_data iter_data;
1080 struct ath_beacon_config *cur_conf;
1081
1082 ath_chanctx_check_active(sc, ctx);
1083
1084 if (ctx != sc->cur_chan)
1085 return;
1086
1087 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1088 if (ctx == &sc->offchannel.chan)
1089 return ath9k_set_offchannel_state(sc);
1090 #endif
1091
1092 ath9k_ps_wakeup(sc);
1093 ath9k_calculate_iter_data(sc, ctx, &iter_data);
1094
1095 if (iter_data.has_hw_macaddr)
1096 memcpy(common->macaddr, iter_data.hw_macaddr, ETH_ALEN);
1097
1098 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1099 ath_hw_setbssidmask(common);
1100
1101 if (iter_data.naps > 0) {
1102 cur_conf = &ctx->beacon;
1103 ath9k_hw_set_tsfadjust(ah, true);
1104 ah->opmode = NL80211_IFTYPE_AP;
1105 if (cur_conf->enable_beacon)
1106 iter_data.beacons = true;
1107 } else {
1108 ath9k_hw_set_tsfadjust(ah, false);
1109
1110 if (iter_data.nmeshes)
1111 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1112 else if (iter_data.nocbs)
1113 ah->opmode = NL80211_IFTYPE_OCB;
1114 else if (iter_data.nwds)
1115 ah->opmode = NL80211_IFTYPE_AP;
1116 else if (iter_data.nadhocs)
1117 ah->opmode = NL80211_IFTYPE_ADHOC;
1118 else
1119 ah->opmode = NL80211_IFTYPE_STATION;
1120 }
1121
1122 ath9k_hw_setopmode(ah);
1123
1124 ctx->switch_after_beacon = false;
1125 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1126 ah->imask |= ATH9K_INT_TSFOOR;
1127 else {
1128 ah->imask &= ~ATH9K_INT_TSFOOR;
1129 if (iter_data.naps == 1 && iter_data.beacons)
1130 ctx->switch_after_beacon = true;
1131 }
1132
1133 ah->imask &= ~ATH9K_INT_SWBA;
1134 if (ah->opmode == NL80211_IFTYPE_STATION) {
1135 bool changed = (iter_data.primary_sta != ctx->primary_sta);
1136
1137 if (iter_data.primary_sta) {
1138 iter_data.beacons = true;
1139 ath9k_set_assoc_state(sc, iter_data.primary_sta,
1140 changed);
1141 ctx->primary_sta = iter_data.primary_sta;
1142 } else {
1143 ctx->primary_sta = NULL;
1144 eth_zero_addr(common->curbssid);
1145 common->curaid = 0;
1146 ath9k_hw_write_associd(sc->sc_ah);
1147 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1148 ath9k_mci_update_wlan_channels(sc, true);
1149 }
1150 } else if (iter_data.beacons) {
1151 ah->imask |= ATH9K_INT_SWBA;
1152 }
1153 ath9k_hw_set_interrupts(ah);
1154
1155 if (iter_data.beacons)
1156 set_bit(ATH_OP_BEACONS, &common->op_flags);
1157 else
1158 clear_bit(ATH_OP_BEACONS, &common->op_flags);
1159
1160 if (ah->slottime != iter_data.slottime) {
1161 ah->slottime = iter_data.slottime;
1162 ath9k_hw_init_global_settings(ah);
1163 }
1164
1165 if (iter_data.primary_sta)
1166 set_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1167 else
1168 clear_bit(ATH_OP_PRIM_STA_VIF, &common->op_flags);
1169
1170 ath_dbg(common, CONFIG,
1171 "macaddr: %pM, bssid: %pM, bssidmask: %pM\n",
1172 common->macaddr, common->curbssid, common->bssidmask);
1173
1174 ath9k_ps_restore(sc);
1175 }
1176
1177 static void ath9k_tpc_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1178 {
1179 int *power = (int *)data;
1180
1181 if (*power < vif->bss_conf.txpower)
1182 *power = vif->bss_conf.txpower;
1183 }
1184
1185 /* Called with sc->mutex held. */
1186 void ath9k_set_txpower(struct ath_softc *sc, struct ieee80211_vif *vif)
1187 {
1188 int power;
1189 struct ath_hw *ah = sc->sc_ah;
1190 struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
1191
1192 ath9k_ps_wakeup(sc);
1193 if (ah->tpc_enabled) {
1194 power = (vif) ? vif->bss_conf.txpower : -1;
1195 ieee80211_iterate_active_interfaces_atomic(
1196 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1197 ath9k_tpc_vif_iter, &power);
1198 if (power == -1)
1199 power = sc->hw->conf.power_level;
1200 } else {
1201 power = sc->hw->conf.power_level;
1202 }
1203 sc->cur_chan->txpower = 2 * power;
1204 ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
1205 sc->cur_chan->cur_txpower = reg->max_power_level;
1206 ath9k_ps_restore(sc);
1207 }
1208
1209 static void ath9k_assign_hw_queues(struct ieee80211_hw *hw,
1210 struct ieee80211_vif *vif)
1211 {
1212 int i;
1213
1214 if (!ath9k_is_chanctx_enabled())
1215 return;
1216
1217 for (i = 0; i < IEEE80211_NUM_ACS; i++)
1218 vif->hw_queue[i] = i;
1219
1220 if (vif->type == NL80211_IFTYPE_AP ||
1221 vif->type == NL80211_IFTYPE_MESH_POINT)
1222 vif->cab_queue = hw->queues - 2;
1223 else
1224 vif->cab_queue = IEEE80211_INVAL_HW_QUEUE;
1225 }
1226
1227 static int ath9k_add_interface(struct ieee80211_hw *hw,
1228 struct ieee80211_vif *vif)
1229 {
1230 struct ath_softc *sc = hw->priv;
1231 struct ath_hw *ah = sc->sc_ah;
1232 struct ath_common *common = ath9k_hw_common(ah);
1233 struct ath_vif *avp = (void *)vif->drv_priv;
1234 struct ath_node *an = &avp->mcast_node;
1235
1236 mutex_lock(&sc->mutex);
1237
1238 if (config_enabled(CONFIG_ATH9K_TX99)) {
1239 if (sc->cur_chan->nvifs >= 1) {
1240 mutex_unlock(&sc->mutex);
1241 return -EOPNOTSUPP;
1242 }
1243 sc->tx99_vif = vif;
1244 }
1245
1246 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1247 sc->cur_chan->nvifs++;
1248
1249 if (ath9k_uses_beacons(vif->type))
1250 ath9k_beacon_assign_slot(sc, vif);
1251
1252 avp->vif = vif;
1253 if (!ath9k_is_chanctx_enabled()) {
1254 avp->chanctx = sc->cur_chan;
1255 list_add_tail(&avp->list, &avp->chanctx->vifs);
1256 }
1257
1258 ath9k_calculate_summary_state(sc, avp->chanctx);
1259
1260 ath9k_assign_hw_queues(hw, vif);
1261
1262 ath9k_set_txpower(sc, vif);
1263
1264 an->sc = sc;
1265 an->sta = NULL;
1266 an->vif = vif;
1267 an->no_ps_filter = true;
1268 ath_tx_node_init(sc, an);
1269
1270 mutex_unlock(&sc->mutex);
1271 return 0;
1272 }
1273
1274 static int ath9k_change_interface(struct ieee80211_hw *hw,
1275 struct ieee80211_vif *vif,
1276 enum nl80211_iftype new_type,
1277 bool p2p)
1278 {
1279 struct ath_softc *sc = hw->priv;
1280 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1281 struct ath_vif *avp = (void *)vif->drv_priv;
1282
1283 mutex_lock(&sc->mutex);
1284
1285 if (config_enabled(CONFIG_ATH9K_TX99)) {
1286 mutex_unlock(&sc->mutex);
1287 return -EOPNOTSUPP;
1288 }
1289
1290 ath_dbg(common, CONFIG, "Change Interface\n");
1291
1292 if (ath9k_uses_beacons(vif->type))
1293 ath9k_beacon_remove_slot(sc, vif);
1294
1295 vif->type = new_type;
1296 vif->p2p = p2p;
1297
1298 if (ath9k_uses_beacons(vif->type))
1299 ath9k_beacon_assign_slot(sc, vif);
1300
1301 ath9k_assign_hw_queues(hw, vif);
1302 ath9k_calculate_summary_state(sc, avp->chanctx);
1303
1304 ath9k_set_txpower(sc, vif);
1305
1306 mutex_unlock(&sc->mutex);
1307 return 0;
1308 }
1309
1310 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1311 struct ieee80211_vif *vif)
1312 {
1313 struct ath_softc *sc = hw->priv;
1314 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1315 struct ath_vif *avp = (void *)vif->drv_priv;
1316
1317 ath_dbg(common, CONFIG, "Detach Interface\n");
1318
1319 mutex_lock(&sc->mutex);
1320
1321 ath9k_p2p_remove_vif(sc, vif);
1322
1323 sc->cur_chan->nvifs--;
1324 sc->tx99_vif = NULL;
1325 if (!ath9k_is_chanctx_enabled())
1326 list_del(&avp->list);
1327
1328 if (ath9k_uses_beacons(vif->type))
1329 ath9k_beacon_remove_slot(sc, vif);
1330
1331 ath_tx_node_cleanup(sc, &avp->mcast_node);
1332
1333 ath9k_calculate_summary_state(sc, avp->chanctx);
1334
1335 ath9k_set_txpower(sc, NULL);
1336
1337 mutex_unlock(&sc->mutex);
1338 }
1339
1340 static void ath9k_enable_ps(struct ath_softc *sc)
1341 {
1342 struct ath_hw *ah = sc->sc_ah;
1343 struct ath_common *common = ath9k_hw_common(ah);
1344
1345 if (config_enabled(CONFIG_ATH9K_TX99))
1346 return;
1347
1348 sc->ps_enabled = true;
1349 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1350 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1351 ah->imask |= ATH9K_INT_TIM_TIMER;
1352 ath9k_hw_set_interrupts(ah);
1353 }
1354 ath9k_hw_setrxabort(ah, 1);
1355 }
1356 ath_dbg(common, PS, "PowerSave enabled\n");
1357 }
1358
1359 static void ath9k_disable_ps(struct ath_softc *sc)
1360 {
1361 struct ath_hw *ah = sc->sc_ah;
1362 struct ath_common *common = ath9k_hw_common(ah);
1363
1364 if (config_enabled(CONFIG_ATH9K_TX99))
1365 return;
1366
1367 sc->ps_enabled = false;
1368 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1369 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1370 ath9k_hw_setrxabort(ah, 0);
1371 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1372 PS_WAIT_FOR_CAB |
1373 PS_WAIT_FOR_PSPOLL_DATA |
1374 PS_WAIT_FOR_TX_ACK);
1375 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1376 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1377 ath9k_hw_set_interrupts(ah);
1378 }
1379 }
1380 ath_dbg(common, PS, "PowerSave disabled\n");
1381 }
1382
1383 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1384 {
1385 struct ath_softc *sc = hw->priv;
1386 struct ath_hw *ah = sc->sc_ah;
1387 struct ath_common *common = ath9k_hw_common(ah);
1388 struct ieee80211_conf *conf = &hw->conf;
1389 struct ath_chanctx *ctx = sc->cur_chan;
1390
1391 ath9k_ps_wakeup(sc);
1392 mutex_lock(&sc->mutex);
1393
1394 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1395 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1396 if (sc->ps_idle) {
1397 ath_cancel_work(sc);
1398 ath9k_stop_btcoex(sc);
1399 } else {
1400 ath9k_start_btcoex(sc);
1401 /*
1402 * The chip needs a reset to properly wake up from
1403 * full sleep
1404 */
1405 ath_chanctx_set_channel(sc, ctx, &ctx->chandef);
1406 }
1407 }
1408
1409 /*
1410 * We just prepare to enable PS. We have to wait until our AP has
1411 * ACK'd our null data frame to disable RX otherwise we'll ignore
1412 * those ACKs and end up retransmitting the same null data frames.
1413 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1414 */
1415 if (changed & IEEE80211_CONF_CHANGE_PS) {
1416 unsigned long flags;
1417 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1418 if (conf->flags & IEEE80211_CONF_PS)
1419 ath9k_enable_ps(sc);
1420 else
1421 ath9k_disable_ps(sc);
1422 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1423 }
1424
1425 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1426 if (conf->flags & IEEE80211_CONF_MONITOR) {
1427 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1428 sc->sc_ah->is_monitoring = true;
1429 } else {
1430 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1431 sc->sc_ah->is_monitoring = false;
1432 }
1433 }
1434
1435 if (!ath9k_is_chanctx_enabled() && (changed & IEEE80211_CONF_CHANGE_CHANNEL)) {
1436 ctx->offchannel = !!(conf->flags & IEEE80211_CONF_OFFCHANNEL);
1437 ath_chanctx_set_channel(sc, ctx, &hw->conf.chandef);
1438 }
1439
1440 mutex_unlock(&sc->mutex);
1441 ath9k_ps_restore(sc);
1442
1443 return 0;
1444 }
1445
1446 #define SUPPORTED_FILTERS \
1447 (FIF_ALLMULTI | \
1448 FIF_CONTROL | \
1449 FIF_PSPOLL | \
1450 FIF_OTHER_BSS | \
1451 FIF_BCN_PRBRESP_PROMISC | \
1452 FIF_PROBE_REQ | \
1453 FIF_FCSFAIL)
1454
1455 /* FIXME: sc->sc_full_reset ? */
1456 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1457 unsigned int changed_flags,
1458 unsigned int *total_flags,
1459 u64 multicast)
1460 {
1461 struct ath_softc *sc = hw->priv;
1462 struct ath_chanctx *ctx;
1463 u32 rfilt;
1464
1465 changed_flags &= SUPPORTED_FILTERS;
1466 *total_flags &= SUPPORTED_FILTERS;
1467
1468 spin_lock_bh(&sc->chan_lock);
1469 ath_for_each_chanctx(sc, ctx)
1470 ctx->rxfilter = *total_flags;
1471 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
1472 sc->offchannel.chan.rxfilter = *total_flags;
1473 #endif
1474 spin_unlock_bh(&sc->chan_lock);
1475
1476 ath9k_ps_wakeup(sc);
1477 rfilt = ath_calcrxfilter(sc);
1478 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1479 ath9k_ps_restore(sc);
1480
1481 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1482 rfilt);
1483 }
1484
1485 static int ath9k_sta_add(struct ieee80211_hw *hw,
1486 struct ieee80211_vif *vif,
1487 struct ieee80211_sta *sta)
1488 {
1489 struct ath_softc *sc = hw->priv;
1490 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1491 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1492 struct ieee80211_key_conf ps_key = { };
1493 int key;
1494
1495 ath_node_attach(sc, sta, vif);
1496
1497 if (vif->type != NL80211_IFTYPE_AP &&
1498 vif->type != NL80211_IFTYPE_AP_VLAN)
1499 return 0;
1500
1501 key = ath_key_config(common, vif, sta, &ps_key);
1502 if (key > 0) {
1503 an->ps_key = key;
1504 an->key_idx[0] = key;
1505 }
1506
1507 return 0;
1508 }
1509
1510 static void ath9k_del_ps_key(struct ath_softc *sc,
1511 struct ieee80211_vif *vif,
1512 struct ieee80211_sta *sta)
1513 {
1514 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1515 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1516 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1517
1518 if (!an->ps_key)
1519 return;
1520
1521 ath_key_delete(common, &ps_key);
1522 an->ps_key = 0;
1523 an->key_idx[0] = 0;
1524 }
1525
1526 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1527 struct ieee80211_vif *vif,
1528 struct ieee80211_sta *sta)
1529 {
1530 struct ath_softc *sc = hw->priv;
1531
1532 ath9k_del_ps_key(sc, vif, sta);
1533 ath_node_detach(sc, sta);
1534
1535 return 0;
1536 }
1537
1538 static int ath9k_sta_state(struct ieee80211_hw *hw,
1539 struct ieee80211_vif *vif,
1540 struct ieee80211_sta *sta,
1541 enum ieee80211_sta_state old_state,
1542 enum ieee80211_sta_state new_state)
1543 {
1544 struct ath_softc *sc = hw->priv;
1545 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1546 int ret = 0;
1547
1548 if (old_state == IEEE80211_STA_NOTEXIST &&
1549 new_state == IEEE80211_STA_NONE) {
1550 ret = ath9k_sta_add(hw, vif, sta);
1551 ath_dbg(common, CONFIG,
1552 "Add station: %pM\n", sta->addr);
1553 } else if (old_state == IEEE80211_STA_NONE &&
1554 new_state == IEEE80211_STA_NOTEXIST) {
1555 ret = ath9k_sta_remove(hw, vif, sta);
1556 ath_dbg(common, CONFIG,
1557 "Remove station: %pM\n", sta->addr);
1558 }
1559
1560 if (ath9k_is_chanctx_enabled()) {
1561 if (vif->type == NL80211_IFTYPE_STATION) {
1562 if (old_state == IEEE80211_STA_ASSOC &&
1563 new_state == IEEE80211_STA_AUTHORIZED)
1564 ath_chanctx_event(sc, vif,
1565 ATH_CHANCTX_EVENT_AUTHORIZED);
1566 }
1567 }
1568
1569 return ret;
1570 }
1571
1572 static void ath9k_sta_set_tx_filter(struct ath_hw *ah,
1573 struct ath_node *an,
1574 bool set)
1575 {
1576 int i;
1577
1578 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1579 if (!an->key_idx[i])
1580 continue;
1581 ath9k_hw_set_tx_filter(ah, an->key_idx[i], set);
1582 }
1583 }
1584
1585 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1586 struct ieee80211_vif *vif,
1587 enum sta_notify_cmd cmd,
1588 struct ieee80211_sta *sta)
1589 {
1590 struct ath_softc *sc = hw->priv;
1591 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1592
1593 switch (cmd) {
1594 case STA_NOTIFY_SLEEP:
1595 an->sleeping = true;
1596 ath_tx_aggr_sleep(sta, sc, an);
1597 ath9k_sta_set_tx_filter(sc->sc_ah, an, true);
1598 break;
1599 case STA_NOTIFY_AWAKE:
1600 ath9k_sta_set_tx_filter(sc->sc_ah, an, false);
1601 an->sleeping = false;
1602 ath_tx_aggr_wakeup(sc, an);
1603 break;
1604 }
1605 }
1606
1607 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1608 struct ieee80211_vif *vif, u16 queue,
1609 const struct ieee80211_tx_queue_params *params)
1610 {
1611 struct ath_softc *sc = hw->priv;
1612 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1613 struct ath_txq *txq;
1614 struct ath9k_tx_queue_info qi;
1615 int ret = 0;
1616
1617 if (queue >= IEEE80211_NUM_ACS)
1618 return 0;
1619
1620 txq = sc->tx.txq_map[queue];
1621
1622 ath9k_ps_wakeup(sc);
1623 mutex_lock(&sc->mutex);
1624
1625 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1626
1627 qi.tqi_aifs = params->aifs;
1628 qi.tqi_cwmin = params->cw_min;
1629 qi.tqi_cwmax = params->cw_max;
1630 qi.tqi_burstTime = params->txop * 32;
1631
1632 ath_dbg(common, CONFIG,
1633 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1634 queue, txq->axq_qnum, params->aifs, params->cw_min,
1635 params->cw_max, params->txop);
1636
1637 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1638 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1639 if (ret)
1640 ath_err(common, "TXQ Update failed\n");
1641
1642 mutex_unlock(&sc->mutex);
1643 ath9k_ps_restore(sc);
1644
1645 return ret;
1646 }
1647
1648 static int ath9k_set_key(struct ieee80211_hw *hw,
1649 enum set_key_cmd cmd,
1650 struct ieee80211_vif *vif,
1651 struct ieee80211_sta *sta,
1652 struct ieee80211_key_conf *key)
1653 {
1654 struct ath_softc *sc = hw->priv;
1655 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1656 struct ath_node *an = NULL;
1657 int ret = 0, i;
1658
1659 if (ath9k_modparam_nohwcrypt)
1660 return -ENOSPC;
1661
1662 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1663 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1664 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1665 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1666 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1667 /*
1668 * For now, disable hw crypto for the RSN IBSS group keys. This
1669 * could be optimized in the future to use a modified key cache
1670 * design to support per-STA RX GTK, but until that gets
1671 * implemented, use of software crypto for group addressed
1672 * frames is a acceptable to allow RSN IBSS to be used.
1673 */
1674 return -EOPNOTSUPP;
1675 }
1676
1677 mutex_lock(&sc->mutex);
1678 ath9k_ps_wakeup(sc);
1679 ath_dbg(common, CONFIG, "Set HW Key %d\n", cmd);
1680 if (sta)
1681 an = (struct ath_node *)sta->drv_priv;
1682
1683 switch (cmd) {
1684 case SET_KEY:
1685 if (sta)
1686 ath9k_del_ps_key(sc, vif, sta);
1687
1688 key->hw_key_idx = 0;
1689 ret = ath_key_config(common, vif, sta, key);
1690 if (ret >= 0) {
1691 key->hw_key_idx = ret;
1692 /* push IV and Michael MIC generation to stack */
1693 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1694 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1695 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1696 if (sc->sc_ah->sw_mgmt_crypto_tx &&
1697 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1698 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1699 ret = 0;
1700 }
1701 if (an && key->hw_key_idx) {
1702 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1703 if (an->key_idx[i])
1704 continue;
1705 an->key_idx[i] = key->hw_key_idx;
1706 break;
1707 }
1708 WARN_ON(i == ARRAY_SIZE(an->key_idx));
1709 }
1710 break;
1711 case DISABLE_KEY:
1712 ath_key_delete(common, key);
1713 if (an) {
1714 for (i = 0; i < ARRAY_SIZE(an->key_idx); i++) {
1715 if (an->key_idx[i] != key->hw_key_idx)
1716 continue;
1717 an->key_idx[i] = 0;
1718 break;
1719 }
1720 }
1721 key->hw_key_idx = 0;
1722 break;
1723 default:
1724 ret = -EINVAL;
1725 }
1726
1727 ath9k_ps_restore(sc);
1728 mutex_unlock(&sc->mutex);
1729
1730 return ret;
1731 }
1732
1733 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1734 struct ieee80211_vif *vif,
1735 struct ieee80211_bss_conf *bss_conf,
1736 u32 changed)
1737 {
1738 #define CHECK_ANI \
1739 (BSS_CHANGED_ASSOC | \
1740 BSS_CHANGED_IBSS | \
1741 BSS_CHANGED_BEACON_ENABLED)
1742
1743 struct ath_softc *sc = hw->priv;
1744 struct ath_hw *ah = sc->sc_ah;
1745 struct ath_common *common = ath9k_hw_common(ah);
1746 struct ath_vif *avp = (void *)vif->drv_priv;
1747 int slottime;
1748
1749 ath9k_ps_wakeup(sc);
1750 mutex_lock(&sc->mutex);
1751
1752 if (changed & BSS_CHANGED_ASSOC) {
1753 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1754 bss_conf->bssid, bss_conf->assoc);
1755
1756 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
1757 avp->aid = bss_conf->aid;
1758 avp->assoc = bss_conf->assoc;
1759
1760 ath9k_calculate_summary_state(sc, avp->chanctx);
1761 }
1762
1763 if ((changed & BSS_CHANGED_IBSS) ||
1764 (changed & BSS_CHANGED_OCB)) {
1765 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1766 common->curaid = bss_conf->aid;
1767 ath9k_hw_write_associd(sc->sc_ah);
1768 }
1769
1770 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1771 (changed & BSS_CHANGED_BEACON_INT) ||
1772 (changed & BSS_CHANGED_BEACON_INFO)) {
1773 ath9k_beacon_config(sc, vif, changed);
1774 if (changed & BSS_CHANGED_BEACON_ENABLED)
1775 ath9k_calculate_summary_state(sc, avp->chanctx);
1776 }
1777
1778 if ((avp->chanctx == sc->cur_chan) &&
1779 (changed & BSS_CHANGED_ERP_SLOT)) {
1780 if (bss_conf->use_short_slot)
1781 slottime = 9;
1782 else
1783 slottime = 20;
1784 if (vif->type == NL80211_IFTYPE_AP) {
1785 /*
1786 * Defer update, so that connected stations can adjust
1787 * their settings at the same time.
1788 * See beacon.c for more details
1789 */
1790 sc->beacon.slottime = slottime;
1791 sc->beacon.updateslot = UPDATE;
1792 } else {
1793 ah->slottime = slottime;
1794 ath9k_hw_init_global_settings(ah);
1795 }
1796 }
1797
1798 if (changed & BSS_CHANGED_P2P_PS)
1799 ath9k_p2p_bss_info_changed(sc, vif);
1800
1801 if (changed & CHECK_ANI)
1802 ath_check_ani(sc);
1803
1804 if (changed & BSS_CHANGED_TXPOWER) {
1805 ath_dbg(common, CONFIG, "vif %pM power %d dbm power_type %d\n",
1806 vif->addr, bss_conf->txpower, bss_conf->txpower_type);
1807 ath9k_set_txpower(sc, vif);
1808 }
1809
1810 mutex_unlock(&sc->mutex);
1811 ath9k_ps_restore(sc);
1812
1813 #undef CHECK_ANI
1814 }
1815
1816 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1817 {
1818 struct ath_softc *sc = hw->priv;
1819 u64 tsf;
1820
1821 mutex_lock(&sc->mutex);
1822 ath9k_ps_wakeup(sc);
1823 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1824 ath9k_ps_restore(sc);
1825 mutex_unlock(&sc->mutex);
1826
1827 return tsf;
1828 }
1829
1830 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1831 struct ieee80211_vif *vif,
1832 u64 tsf)
1833 {
1834 struct ath_softc *sc = hw->priv;
1835
1836 mutex_lock(&sc->mutex);
1837 ath9k_ps_wakeup(sc);
1838 ath9k_hw_settsf64(sc->sc_ah, tsf);
1839 ath9k_ps_restore(sc);
1840 mutex_unlock(&sc->mutex);
1841 }
1842
1843 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1844 {
1845 struct ath_softc *sc = hw->priv;
1846
1847 mutex_lock(&sc->mutex);
1848
1849 ath9k_ps_wakeup(sc);
1850 ath9k_hw_reset_tsf(sc->sc_ah);
1851 ath9k_ps_restore(sc);
1852
1853 mutex_unlock(&sc->mutex);
1854 }
1855
1856 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1857 struct ieee80211_vif *vif,
1858 struct ieee80211_ampdu_params *params)
1859 {
1860 struct ath_softc *sc = hw->priv;
1861 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1862 bool flush = false;
1863 int ret = 0;
1864 struct ieee80211_sta *sta = params->sta;
1865 enum ieee80211_ampdu_mlme_action action = params->action;
1866 u16 tid = params->tid;
1867 u16 *ssn = &params->ssn;
1868
1869 mutex_lock(&sc->mutex);
1870
1871 switch (action) {
1872 case IEEE80211_AMPDU_RX_START:
1873 break;
1874 case IEEE80211_AMPDU_RX_STOP:
1875 break;
1876 case IEEE80211_AMPDU_TX_START:
1877 if (ath9k_is_chanctx_enabled()) {
1878 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
1879 ret = -EBUSY;
1880 break;
1881 }
1882 }
1883 ath9k_ps_wakeup(sc);
1884 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1885 if (!ret)
1886 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1887 ath9k_ps_restore(sc);
1888 break;
1889 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1890 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1891 flush = true;
1892 case IEEE80211_AMPDU_TX_STOP_CONT:
1893 ath9k_ps_wakeup(sc);
1894 ath_tx_aggr_stop(sc, sta, tid);
1895 if (!flush)
1896 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1897 ath9k_ps_restore(sc);
1898 break;
1899 case IEEE80211_AMPDU_TX_OPERATIONAL:
1900 ath9k_ps_wakeup(sc);
1901 ath_tx_aggr_resume(sc, sta, tid);
1902 ath9k_ps_restore(sc);
1903 break;
1904 default:
1905 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1906 }
1907
1908 mutex_unlock(&sc->mutex);
1909
1910 return ret;
1911 }
1912
1913 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1914 struct survey_info *survey)
1915 {
1916 struct ath_softc *sc = hw->priv;
1917 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1918 struct ieee80211_supported_band *sband;
1919 struct ieee80211_channel *chan;
1920 int pos;
1921
1922 if (config_enabled(CONFIG_ATH9K_TX99))
1923 return -EOPNOTSUPP;
1924
1925 spin_lock_bh(&common->cc_lock);
1926 if (idx == 0)
1927 ath_update_survey_stats(sc);
1928
1929 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1930 if (sband && idx >= sband->n_channels) {
1931 idx -= sband->n_channels;
1932 sband = NULL;
1933 }
1934
1935 if (!sband)
1936 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1937
1938 if (!sband || idx >= sband->n_channels) {
1939 spin_unlock_bh(&common->cc_lock);
1940 return -ENOENT;
1941 }
1942
1943 chan = &sband->channels[idx];
1944 pos = chan->hw_value;
1945 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1946 survey->channel = chan;
1947 spin_unlock_bh(&common->cc_lock);
1948
1949 return 0;
1950 }
1951
1952 static void ath9k_enable_dynack(struct ath_softc *sc)
1953 {
1954 #ifdef CONFIG_ATH9K_DYNACK
1955 u32 rfilt;
1956 struct ath_hw *ah = sc->sc_ah;
1957
1958 ath_dynack_reset(ah);
1959
1960 ah->dynack.enabled = true;
1961 rfilt = ath_calcrxfilter(sc);
1962 ath9k_hw_setrxfilter(ah, rfilt);
1963 #endif
1964 }
1965
1966 static void ath9k_set_coverage_class(struct ieee80211_hw *hw,
1967 s16 coverage_class)
1968 {
1969 struct ath_softc *sc = hw->priv;
1970 struct ath_hw *ah = sc->sc_ah;
1971
1972 if (config_enabled(CONFIG_ATH9K_TX99))
1973 return;
1974
1975 mutex_lock(&sc->mutex);
1976
1977 if (coverage_class >= 0) {
1978 ah->coverage_class = coverage_class;
1979 if (ah->dynack.enabled) {
1980 u32 rfilt;
1981
1982 ah->dynack.enabled = false;
1983 rfilt = ath_calcrxfilter(sc);
1984 ath9k_hw_setrxfilter(ah, rfilt);
1985 }
1986 ath9k_ps_wakeup(sc);
1987 ath9k_hw_init_global_settings(ah);
1988 ath9k_ps_restore(sc);
1989 } else if (!ah->dynack.enabled) {
1990 ath9k_enable_dynack(sc);
1991 }
1992
1993 mutex_unlock(&sc->mutex);
1994 }
1995
1996 static bool ath9k_has_tx_pending(struct ath_softc *sc,
1997 bool sw_pending)
1998 {
1999 int i, npend = 0;
2000
2001 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2002 if (!ATH_TXQ_SETUP(sc, i))
2003 continue;
2004
2005 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i],
2006 sw_pending);
2007 if (npend)
2008 break;
2009 }
2010
2011 return !!npend;
2012 }
2013
2014 static void ath9k_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2015 u32 queues, bool drop)
2016 {
2017 struct ath_softc *sc = hw->priv;
2018 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2019
2020 if (ath9k_is_chanctx_enabled()) {
2021 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2022 goto flush;
2023
2024 /*
2025 * If MCC is active, extend the flush timeout
2026 * and wait for the HW/SW queues to become
2027 * empty. This needs to be done outside the
2028 * sc->mutex lock to allow the channel scheduler
2029 * to switch channel contexts.
2030 *
2031 * The vif queues have been stopped in mac80211,
2032 * so there won't be any incoming frames.
2033 */
2034 __ath9k_flush(hw, queues, drop, true, true);
2035 return;
2036 }
2037 flush:
2038 mutex_lock(&sc->mutex);
2039 __ath9k_flush(hw, queues, drop, true, false);
2040 mutex_unlock(&sc->mutex);
2041 }
2042
2043 void __ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop,
2044 bool sw_pending, bool timeout_override)
2045 {
2046 struct ath_softc *sc = hw->priv;
2047 struct ath_hw *ah = sc->sc_ah;
2048 struct ath_common *common = ath9k_hw_common(ah);
2049 int timeout;
2050 bool drain_txq;
2051
2052 cancel_delayed_work_sync(&sc->tx_complete_work);
2053
2054 if (ah->ah_flags & AH_UNPLUGGED) {
2055 ath_dbg(common, ANY, "Device has been unplugged!\n");
2056 return;
2057 }
2058
2059 if (test_bit(ATH_OP_INVALID, &common->op_flags)) {
2060 ath_dbg(common, ANY, "Device not present\n");
2061 return;
2062 }
2063
2064 spin_lock_bh(&sc->chan_lock);
2065 if (timeout_override)
2066 timeout = HZ / 5;
2067 else
2068 timeout = sc->cur_chan->flush_timeout;
2069 spin_unlock_bh(&sc->chan_lock);
2070
2071 ath_dbg(common, CHAN_CTX,
2072 "Flush timeout: %d\n", jiffies_to_msecs(timeout));
2073
2074 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc, sw_pending),
2075 timeout) > 0)
2076 drop = false;
2077
2078 if (drop) {
2079 ath9k_ps_wakeup(sc);
2080 spin_lock_bh(&sc->sc_pcu_lock);
2081 drain_txq = ath_drain_all_txq(sc);
2082 spin_unlock_bh(&sc->sc_pcu_lock);
2083
2084 if (!drain_txq)
2085 ath_reset(sc, NULL);
2086
2087 ath9k_ps_restore(sc);
2088 }
2089
2090 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
2091 }
2092
2093 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
2094 {
2095 struct ath_softc *sc = hw->priv;
2096
2097 return ath9k_has_tx_pending(sc, true);
2098 }
2099
2100 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
2101 {
2102 struct ath_softc *sc = hw->priv;
2103 struct ath_hw *ah = sc->sc_ah;
2104 struct ieee80211_vif *vif;
2105 struct ath_vif *avp;
2106 struct ath_buf *bf;
2107 struct ath_tx_status ts;
2108 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2109 int status;
2110
2111 vif = sc->beacon.bslot[0];
2112 if (!vif)
2113 return 0;
2114
2115 if (!vif->bss_conf.enable_beacon)
2116 return 0;
2117
2118 avp = (void *)vif->drv_priv;
2119
2120 if (!sc->beacon.tx_processed && !edma) {
2121 tasklet_disable(&sc->bcon_tasklet);
2122
2123 bf = avp->av_bcbuf;
2124 if (!bf || !bf->bf_mpdu)
2125 goto skip;
2126
2127 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
2128 if (status == -EINPROGRESS)
2129 goto skip;
2130
2131 sc->beacon.tx_processed = true;
2132 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2133
2134 skip:
2135 tasklet_enable(&sc->bcon_tasklet);
2136 }
2137
2138 return sc->beacon.tx_last;
2139 }
2140
2141 static int ath9k_get_stats(struct ieee80211_hw *hw,
2142 struct ieee80211_low_level_stats *stats)
2143 {
2144 struct ath_softc *sc = hw->priv;
2145 struct ath_hw *ah = sc->sc_ah;
2146 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
2147
2148 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
2149 stats->dot11RTSFailureCount = mib_stats->rts_bad;
2150 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
2151 stats->dot11RTSSuccessCount = mib_stats->rts_good;
2152 return 0;
2153 }
2154
2155 static u32 fill_chainmask(u32 cap, u32 new)
2156 {
2157 u32 filled = 0;
2158 int i;
2159
2160 for (i = 0; cap && new; i++, cap >>= 1) {
2161 if (!(cap & BIT(0)))
2162 continue;
2163
2164 if (new & BIT(0))
2165 filled |= BIT(i);
2166
2167 new >>= 1;
2168 }
2169
2170 return filled;
2171 }
2172
2173 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2174 {
2175 if (AR_SREV_9300_20_OR_LATER(ah))
2176 return true;
2177
2178 switch (val & 0x7) {
2179 case 0x1:
2180 case 0x3:
2181 case 0x7:
2182 return true;
2183 case 0x2:
2184 return (ah->caps.rx_chainmask == 1);
2185 default:
2186 return false;
2187 }
2188 }
2189
2190 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2191 {
2192 struct ath_softc *sc = hw->priv;
2193 struct ath_hw *ah = sc->sc_ah;
2194
2195 if (ah->caps.rx_chainmask != 1)
2196 rx_ant |= tx_ant;
2197
2198 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2199 return -EINVAL;
2200
2201 sc->ant_rx = rx_ant;
2202 sc->ant_tx = tx_ant;
2203
2204 if (ah->caps.rx_chainmask == 1)
2205 return 0;
2206
2207 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2208 if (AR_SREV_9100(ah))
2209 ah->rxchainmask = 0x7;
2210 else
2211 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2212
2213 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2214 ath9k_cmn_reload_chainmask(ah);
2215
2216 return 0;
2217 }
2218
2219 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2220 {
2221 struct ath_softc *sc = hw->priv;
2222
2223 *tx_ant = sc->ant_tx;
2224 *rx_ant = sc->ant_rx;
2225 return 0;
2226 }
2227
2228 static void ath9k_sw_scan_start(struct ieee80211_hw *hw,
2229 struct ieee80211_vif *vif,
2230 const u8 *mac_addr)
2231 {
2232 struct ath_softc *sc = hw->priv;
2233 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2234 set_bit(ATH_OP_SCANNING, &common->op_flags);
2235 }
2236
2237 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw,
2238 struct ieee80211_vif *vif)
2239 {
2240 struct ath_softc *sc = hw->priv;
2241 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2242 clear_bit(ATH_OP_SCANNING, &common->op_flags);
2243 }
2244
2245 #ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
2246
2247 static void ath9k_cancel_pending_offchannel(struct ath_softc *sc)
2248 {
2249 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2250
2251 if (sc->offchannel.roc_vif) {
2252 ath_dbg(common, CHAN_CTX,
2253 "%s: Aborting RoC\n", __func__);
2254
2255 del_timer_sync(&sc->offchannel.timer);
2256 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2257 ath_roc_complete(sc, ATH_ROC_COMPLETE_ABORT);
2258 }
2259
2260 if (test_bit(ATH_OP_SCANNING, &common->op_flags)) {
2261 ath_dbg(common, CHAN_CTX,
2262 "%s: Aborting HW scan\n", __func__);
2263
2264 del_timer_sync(&sc->offchannel.timer);
2265 ath_scan_complete(sc, true);
2266 }
2267 }
2268
2269 static int ath9k_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2270 struct ieee80211_scan_request *hw_req)
2271 {
2272 struct cfg80211_scan_request *req = &hw_req->req;
2273 struct ath_softc *sc = hw->priv;
2274 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2275 int ret = 0;
2276
2277 mutex_lock(&sc->mutex);
2278
2279 if (WARN_ON(sc->offchannel.scan_req)) {
2280 ret = -EBUSY;
2281 goto out;
2282 }
2283
2284 ath9k_ps_wakeup(sc);
2285 set_bit(ATH_OP_SCANNING, &common->op_flags);
2286 sc->offchannel.scan_vif = vif;
2287 sc->offchannel.scan_req = req;
2288 sc->offchannel.scan_idx = 0;
2289
2290 ath_dbg(common, CHAN_CTX, "HW scan request received on vif: %pM\n",
2291 vif->addr);
2292
2293 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2294 ath_dbg(common, CHAN_CTX, "Starting HW scan\n");
2295 ath_offchannel_next(sc);
2296 }
2297
2298 out:
2299 mutex_unlock(&sc->mutex);
2300
2301 return ret;
2302 }
2303
2304 static void ath9k_cancel_hw_scan(struct ieee80211_hw *hw,
2305 struct ieee80211_vif *vif)
2306 {
2307 struct ath_softc *sc = hw->priv;
2308 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2309
2310 ath_dbg(common, CHAN_CTX, "Cancel HW scan on vif: %pM\n", vif->addr);
2311
2312 mutex_lock(&sc->mutex);
2313 del_timer_sync(&sc->offchannel.timer);
2314 ath_scan_complete(sc, true);
2315 mutex_unlock(&sc->mutex);
2316 }
2317
2318 static int ath9k_remain_on_channel(struct ieee80211_hw *hw,
2319 struct ieee80211_vif *vif,
2320 struct ieee80211_channel *chan, int duration,
2321 enum ieee80211_roc_type type)
2322 {
2323 struct ath_softc *sc = hw->priv;
2324 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2325 int ret = 0;
2326
2327 mutex_lock(&sc->mutex);
2328
2329 if (WARN_ON(sc->offchannel.roc_vif)) {
2330 ret = -EBUSY;
2331 goto out;
2332 }
2333
2334 ath9k_ps_wakeup(sc);
2335 sc->offchannel.roc_vif = vif;
2336 sc->offchannel.roc_chan = chan;
2337 sc->offchannel.roc_duration = duration;
2338
2339 ath_dbg(common, CHAN_CTX,
2340 "RoC request on vif: %pM, type: %d duration: %d\n",
2341 vif->addr, type, duration);
2342
2343 if (sc->offchannel.state == ATH_OFFCHANNEL_IDLE) {
2344 ath_dbg(common, CHAN_CTX, "Starting RoC period\n");
2345 ath_offchannel_next(sc);
2346 }
2347
2348 out:
2349 mutex_unlock(&sc->mutex);
2350
2351 return ret;
2352 }
2353
2354 static int ath9k_cancel_remain_on_channel(struct ieee80211_hw *hw)
2355 {
2356 struct ath_softc *sc = hw->priv;
2357 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2358
2359 mutex_lock(&sc->mutex);
2360
2361 ath_dbg(common, CHAN_CTX, "Cancel RoC\n");
2362 del_timer_sync(&sc->offchannel.timer);
2363
2364 if (sc->offchannel.roc_vif) {
2365 if (sc->offchannel.state >= ATH_OFFCHANNEL_ROC_START)
2366 ath_roc_complete(sc, ATH_ROC_COMPLETE_CANCEL);
2367 }
2368
2369 mutex_unlock(&sc->mutex);
2370
2371 return 0;
2372 }
2373
2374 static int ath9k_add_chanctx(struct ieee80211_hw *hw,
2375 struct ieee80211_chanctx_conf *conf)
2376 {
2377 struct ath_softc *sc = hw->priv;
2378 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2379 struct ath_chanctx *ctx, **ptr;
2380 int pos;
2381
2382 mutex_lock(&sc->mutex);
2383
2384 ath_for_each_chanctx(sc, ctx) {
2385 if (ctx->assigned)
2386 continue;
2387
2388 ptr = (void *) conf->drv_priv;
2389 *ptr = ctx;
2390 ctx->assigned = true;
2391 pos = ctx - &sc->chanctx[0];
2392 ctx->hw_queue_base = pos * IEEE80211_NUM_ACS;
2393
2394 ath_dbg(common, CHAN_CTX,
2395 "Add channel context: %d MHz\n",
2396 conf->def.chan->center_freq);
2397
2398 ath_chanctx_set_channel(sc, ctx, &conf->def);
2399
2400 mutex_unlock(&sc->mutex);
2401 return 0;
2402 }
2403
2404 mutex_unlock(&sc->mutex);
2405 return -ENOSPC;
2406 }
2407
2408
2409 static void ath9k_remove_chanctx(struct ieee80211_hw *hw,
2410 struct ieee80211_chanctx_conf *conf)
2411 {
2412 struct ath_softc *sc = hw->priv;
2413 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2414 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2415
2416 mutex_lock(&sc->mutex);
2417
2418 ath_dbg(common, CHAN_CTX,
2419 "Remove channel context: %d MHz\n",
2420 conf->def.chan->center_freq);
2421
2422 ctx->assigned = false;
2423 ctx->hw_queue_base = 0;
2424 ath_chanctx_event(sc, NULL, ATH_CHANCTX_EVENT_UNASSIGN);
2425
2426 mutex_unlock(&sc->mutex);
2427 }
2428
2429 static void ath9k_change_chanctx(struct ieee80211_hw *hw,
2430 struct ieee80211_chanctx_conf *conf,
2431 u32 changed)
2432 {
2433 struct ath_softc *sc = hw->priv;
2434 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2435 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2436
2437 mutex_lock(&sc->mutex);
2438 ath_dbg(common, CHAN_CTX,
2439 "Change channel context: %d MHz\n",
2440 conf->def.chan->center_freq);
2441 ath_chanctx_set_channel(sc, ctx, &conf->def);
2442 mutex_unlock(&sc->mutex);
2443 }
2444
2445 static int ath9k_assign_vif_chanctx(struct ieee80211_hw *hw,
2446 struct ieee80211_vif *vif,
2447 struct ieee80211_chanctx_conf *conf)
2448 {
2449 struct ath_softc *sc = hw->priv;
2450 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2451 struct ath_vif *avp = (void *)vif->drv_priv;
2452 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2453 int i;
2454
2455 ath9k_cancel_pending_offchannel(sc);
2456
2457 mutex_lock(&sc->mutex);
2458
2459 ath_dbg(common, CHAN_CTX,
2460 "Assign VIF (addr: %pM, type: %d, p2p: %d) to channel context: %d MHz\n",
2461 vif->addr, vif->type, vif->p2p,
2462 conf->def.chan->center_freq);
2463
2464 avp->chanctx = ctx;
2465 ctx->nvifs_assigned++;
2466 list_add_tail(&avp->list, &ctx->vifs);
2467 ath9k_calculate_summary_state(sc, ctx);
2468 for (i = 0; i < IEEE80211_NUM_ACS; i++)
2469 vif->hw_queue[i] = ctx->hw_queue_base + i;
2470
2471 mutex_unlock(&sc->mutex);
2472
2473 return 0;
2474 }
2475
2476 static void ath9k_unassign_vif_chanctx(struct ieee80211_hw *hw,
2477 struct ieee80211_vif *vif,
2478 struct ieee80211_chanctx_conf *conf)
2479 {
2480 struct ath_softc *sc = hw->priv;
2481 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2482 struct ath_vif *avp = (void *)vif->drv_priv;
2483 struct ath_chanctx *ctx = ath_chanctx_get(conf);
2484 int ac;
2485
2486 ath9k_cancel_pending_offchannel(sc);
2487
2488 mutex_lock(&sc->mutex);
2489
2490 ath_dbg(common, CHAN_CTX,
2491 "Remove VIF (addr: %pM, type: %d, p2p: %d) from channel context: %d MHz\n",
2492 vif->addr, vif->type, vif->p2p,
2493 conf->def.chan->center_freq);
2494
2495 avp->chanctx = NULL;
2496 ctx->nvifs_assigned--;
2497 list_del(&avp->list);
2498 ath9k_calculate_summary_state(sc, ctx);
2499 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
2500 vif->hw_queue[ac] = IEEE80211_INVAL_HW_QUEUE;
2501
2502 mutex_unlock(&sc->mutex);
2503 }
2504
2505 static void ath9k_mgd_prepare_tx(struct ieee80211_hw *hw,
2506 struct ieee80211_vif *vif)
2507 {
2508 struct ath_softc *sc = hw->priv;
2509 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2510 struct ath_vif *avp = (struct ath_vif *) vif->drv_priv;
2511 struct ath_beacon_config *cur_conf;
2512 struct ath_chanctx *go_ctx;
2513 unsigned long timeout;
2514 bool changed = false;
2515 u32 beacon_int;
2516
2517 if (!test_bit(ATH_OP_MULTI_CHANNEL, &common->op_flags))
2518 return;
2519
2520 if (!avp->chanctx)
2521 return;
2522
2523 mutex_lock(&sc->mutex);
2524
2525 spin_lock_bh(&sc->chan_lock);
2526 if (sc->next_chan || (sc->cur_chan != avp->chanctx))
2527 changed = true;
2528 spin_unlock_bh(&sc->chan_lock);
2529
2530 if (!changed)
2531 goto out;
2532
2533 ath9k_cancel_pending_offchannel(sc);
2534
2535 go_ctx = ath_is_go_chanctx_present(sc);
2536
2537 if (go_ctx) {
2538 /*
2539 * Wait till the GO interface gets a chance
2540 * to send out an NoA.
2541 */
2542 spin_lock_bh(&sc->chan_lock);
2543 sc->sched.mgd_prepare_tx = true;
2544 cur_conf = &go_ctx->beacon;
2545 beacon_int = TU_TO_USEC(cur_conf->beacon_interval);
2546 spin_unlock_bh(&sc->chan_lock);
2547
2548 timeout = usecs_to_jiffies(beacon_int * 2);
2549 init_completion(&sc->go_beacon);
2550
2551 mutex_unlock(&sc->mutex);
2552
2553 if (wait_for_completion_timeout(&sc->go_beacon,
2554 timeout) == 0) {
2555 ath_dbg(common, CHAN_CTX,
2556 "Failed to send new NoA\n");
2557
2558 spin_lock_bh(&sc->chan_lock);
2559 sc->sched.mgd_prepare_tx = false;
2560 spin_unlock_bh(&sc->chan_lock);
2561 }
2562
2563 mutex_lock(&sc->mutex);
2564 }
2565
2566 ath_dbg(common, CHAN_CTX,
2567 "%s: Set chanctx state to FORCE_ACTIVE for vif: %pM\n",
2568 __func__, vif->addr);
2569
2570 spin_lock_bh(&sc->chan_lock);
2571 sc->next_chan = avp->chanctx;
2572 sc->sched.state = ATH_CHANCTX_STATE_FORCE_ACTIVE;
2573 spin_unlock_bh(&sc->chan_lock);
2574
2575 ath_chanctx_set_next(sc, true);
2576 out:
2577 mutex_unlock(&sc->mutex);
2578 }
2579
2580 void ath9k_fill_chanctx_ops(void)
2581 {
2582 if (!ath9k_is_chanctx_enabled())
2583 return;
2584
2585 ath9k_ops.hw_scan = ath9k_hw_scan;
2586 ath9k_ops.cancel_hw_scan = ath9k_cancel_hw_scan;
2587 ath9k_ops.remain_on_channel = ath9k_remain_on_channel;
2588 ath9k_ops.cancel_remain_on_channel = ath9k_cancel_remain_on_channel;
2589 ath9k_ops.add_chanctx = ath9k_add_chanctx;
2590 ath9k_ops.remove_chanctx = ath9k_remove_chanctx;
2591 ath9k_ops.change_chanctx = ath9k_change_chanctx;
2592 ath9k_ops.assign_vif_chanctx = ath9k_assign_vif_chanctx;
2593 ath9k_ops.unassign_vif_chanctx = ath9k_unassign_vif_chanctx;
2594 ath9k_ops.mgd_prepare_tx = ath9k_mgd_prepare_tx;
2595 }
2596
2597 #endif
2598
2599 static int ath9k_get_txpower(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2600 int *dbm)
2601 {
2602 struct ath_softc *sc = hw->priv;
2603 struct ath_vif *avp = (void *)vif->drv_priv;
2604
2605 mutex_lock(&sc->mutex);
2606 if (avp->chanctx)
2607 *dbm = avp->chanctx->cur_txpower;
2608 else
2609 *dbm = sc->cur_chan->cur_txpower;
2610 mutex_unlock(&sc->mutex);
2611
2612 *dbm /= 2;
2613
2614 return 0;
2615 }
2616
2617 struct ieee80211_ops ath9k_ops = {
2618 .tx = ath9k_tx,
2619 .start = ath9k_start,
2620 .stop = ath9k_stop,
2621 .add_interface = ath9k_add_interface,
2622 .change_interface = ath9k_change_interface,
2623 .remove_interface = ath9k_remove_interface,
2624 .config = ath9k_config,
2625 .configure_filter = ath9k_configure_filter,
2626 .sta_state = ath9k_sta_state,
2627 .sta_notify = ath9k_sta_notify,
2628 .conf_tx = ath9k_conf_tx,
2629 .bss_info_changed = ath9k_bss_info_changed,
2630 .set_key = ath9k_set_key,
2631 .get_tsf = ath9k_get_tsf,
2632 .set_tsf = ath9k_set_tsf,
2633 .reset_tsf = ath9k_reset_tsf,
2634 .ampdu_action = ath9k_ampdu_action,
2635 .get_survey = ath9k_get_survey,
2636 .rfkill_poll = ath9k_rfkill_poll_state,
2637 .set_coverage_class = ath9k_set_coverage_class,
2638 .flush = ath9k_flush,
2639 .tx_frames_pending = ath9k_tx_frames_pending,
2640 .tx_last_beacon = ath9k_tx_last_beacon,
2641 .release_buffered_frames = ath9k_release_buffered_frames,
2642 .get_stats = ath9k_get_stats,
2643 .set_antenna = ath9k_set_antenna,
2644 .get_antenna = ath9k_get_antenna,
2645
2646 #ifdef CONFIG_ATH9K_WOW
2647 .suspend = ath9k_suspend,
2648 .resume = ath9k_resume,
2649 .set_wakeup = ath9k_set_wakeup,
2650 #endif
2651
2652 #ifdef CONFIG_ATH9K_DEBUGFS
2653 .get_et_sset_count = ath9k_get_et_sset_count,
2654 .get_et_stats = ath9k_get_et_stats,
2655 .get_et_strings = ath9k_get_et_strings,
2656 #endif
2657
2658 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2659 .sta_add_debugfs = ath9k_sta_add_debugfs,
2660 #endif
2661 .sw_scan_start = ath9k_sw_scan_start,
2662 .sw_scan_complete = ath9k_sw_scan_complete,
2663 .get_txpower = ath9k_get_txpower,
2664 };
Linux with added FPC-III support